yosys2digitaljs 0.7.0 → 0.9.0

package/dist/types.d.ts

@@ -0,0 +1,174 @@
+declare namespace Digitaljs {
+    type FilePosition = {
+        line: number;
+        column: number;
+    };
+    type SourcePosition = {
+        name: string;
+        from: FilePosition;
+        to: FilePosition;
+    };
+    type MemReadPort = {
+        clock_polarity?: boolean;
+        enable_polarity?: boolean;
+        arst_polarity?: boolean;
+        srst_polarity?: boolean;
+        enable_srst?: boolean;
+        transparent?: boolean | boolean[];
+        collision?: boolean | boolean[];
+        init_value?: string;
+        arst_value?: string;
+        srst_value?: string;
+    };
+    type MemWritePort = {
+        clock_polarity?: boolean;
+        enable_polarity?: boolean;
+        no_bit_enable?: boolean;
+    };
+    type Device = {
+        type: string;
+        source_positions?: SourcePosition[];
+        [key: string]: any;
+    };
+    type Port = {
+        id: string;
+        port: string;
+    };
+    type Connector = {
+        from: Port;
+        to: Port;
+        name?: string;
+        source_positions?: SourcePosition[];
+    };
+    type Module = {
+        devices: {
+            [key: string]: Device;
+        };
+        connectors: Connector[];
+    };
+    type TopModule = Module & {
+        subcircuits: {
+            [key: string]: Module;
+        };
+    };
+}
+declare namespace Yosys {
+    const ConstChars: readonly ["0", "1", "x", "z"];
+    type BitChar = (typeof ConstChars)[number];
+    type Bit = number | BitChar;
+    type BitVector = Bit[];
+    type Port = {
+        direction: 'input' | 'output' | 'inout';
+        bits: any;
+    };
+    type Parameters = {
+        WIDTH?: JsonConstant;
+        A_WIDTH?: JsonConstant;
+        B_WIDTH?: JsonConstant;
+        S_WIDTH?: JsonConstant;
+        Y_WIDTH?: JsonConstant;
+        A_SIGNED?: JsonConstant;
+        B_SIGNED?: JsonConstant;
+        CLK_POLARITY?: JsonConstant;
+        EN_POLARITY?: JsonConstant;
+        ARST_POLARITY?: JsonConstant;
+        ARST_VALUE: JsonConstant;
+        CTRL_IN_WIDTH?: JsonConstant;
+        CTRL_OUT_WIDTH?: JsonConstant;
+        TRANS_NUM?: JsonConstant;
+        STATE_NUM?: JsonConstant;
+        STATE_NUM_LOG2?: JsonConstant;
+        STATE_RST?: JsonConstant;
+        RD_PORTS?: JsonConstant;
+        WR_PORTS?: JsonConstant;
+        RD_CLK_POLARITY?: JsonConstant;
+        RD_CLK_ENABLE?: JsonConstant;
+        RD_CLK_TRANSPARENT?: JsonConstant;
+        WR_CLK_POLARITY?: JsonConstant;
+        WR_CLK_ENABLE?: JsonConstant;
+        [key: string]: any;
+    };
+    type JsonConstant = number | string;
+    type Attributes = {
+        init: JsonConstant;
+        [key: string]: any;
+    };
+    type Cell = {
+        hide_name: 0 | 1;
+        type: string;
+        parameters: Parameters;
+        attributes: Attributes;
+        port_directions: {
+            [key: string]: 'input' | 'output';
+        };
+        connections: {
+            [key: string]: BitVector;
+        };
+    };
+    type Net = {
+        hide_name: 0 | 1;
+        bits: BitVector;
+        attributes: {
+            [key: string]: string;
+        };
+    };
+    type Module = {
+        ports: {
+            [key: string]: Port;
+        };
+        cells: {
+            [key: string]: Cell;
+        };
+        netnames: {
+            [key: string]: Net;
+        };
+    };
+    type Output = {
+        modules: {
+            [key: string]: Module;
+        };
+    };
+}
+type ConvertOptions = {
+    propagation?: number;
+};
+type Options = ConvertOptions & {
+    optimize?: boolean;
+    fsmexpand?: boolean;
+    fsm?: boolean | "nomap";
+    timeout?: number;
+    lint?: boolean;
+};
+type Output = {
+    output?: Digitaljs.TopModule;
+    yosys_output?: any;
+    yosys_stdout: string;
+    yosys_stderr: string;
+    lint?: LintMessage[];
+};
+type Portmap = {
+    [key: string]: string;
+};
+type Portmaps = {
+    [key: string]: Portmap;
+};
+type Bit = Yosys.Bit | `bit${number}`;
+type Net = Bit[];
+type NetInfo = {
+    source: undefined | Digitaljs.Port;
+    targets: Digitaljs.Port[];
+    name: undefined | string;
+    source_positions: Digitaljs.SourcePosition[];
+};
+type BitInfo = {
+    id: string;
+    port: string;
+    num: number;
+};
+type LintMessage = {
+    type: string;
+    file: string;
+    line: number;
+    column: number;
+    message: string;
+};

package/dist/types.js

@@ -0,0 +1,6 @@
+;
+var Yosys;
+(function (Yosys) {
+    Yosys.ConstChars = ["0", "1", "x", "z"];
+})(Yosys || (Yosys = {}));
+;

package/package.json

@@ -1,8 +1,8 @@
 {
   "name": "yosys2digitaljs",
-  "version": "0.7.0",
+  "version": "0.9.0",
   "description": "Export Yosys netlists to a logic simulator",
-  "main": "dist/index",
+  "main": "dist/index.js",
   "types": "dist/index.d.ts",
   "scripts": {
     "prepare": "npm run build",
@@ -10,15 +10,28 @@
     "build": "npm run cjs",
     "test": "./run_tests.sh"
   },
+  "exports": {
+    "./core": {
+      "types": "./dist/core.d.ts",
+      "import": "./dist/core.js",
+      "require": "./dist/core.js"
+    },
+    "./node": {
+      "types": "./dist/index.d.ts",
+      "import": "./dist/index.js",
+      "require": "./dist/index.js"
+    }
+  },
   "author": "Marek Materzok",
   "license": "BSD-2-Clause",
   "dependencies": {
     "3vl": "^1.0.1",
-    "big-integer": "^1.6.49",
+    "assert": "^2.1.0",
+    "big-integer": "^1.6.52",
     "hashmap": "^2.4.0",
-    "minimist": "^1.2.5",
+    "minimist": "^1.2.8",
     "sanitize-filename": "^1.6.3",
-    "tmp-promise": "^1.1.0",
+    "tmp-promise": "^3.0.3",
     "topsort": "^0.0.2"
   },
   "engines": {
@@ -30,7 +43,7 @@
     "url": "https://github.com/tilk/yosys2digitaljs.git"
   },
   "devDependencies": {
-    "@types/node": "^16.10.3",
-    "typescript": "^4.4.3"
+    "@types/node": "^24.10.1",
+    "typescript": "^5.9.3"
   }
 }

package/process.js

@@ -3,7 +3,7 @@
 
 const fs = require('fs');
 const argv = require('minimist')(
-    process.argv.slice(2), 
+    process.argv.slice(2),
     {boolean: ["optimize", "yosys_out", "yosys_output", "html", "no_io_ui", "tmpdir", "noindent", "fsmexpand"],
      string: ["fsm"],
      default: {fsm: true}}
@@ -31,6 +31,7 @@ if (argv._.length === 0) {
     console.error('No Verilog files passed!');
     process.exit(1);
 }
+const yosys2digitaljs_core = require('./dist/core.js');
 const yosys2digitaljs = require('./dist/index.js');
 const opts = {};
 if (argv.optimize) opts.optimize = true;
@@ -62,7 +63,7 @@ result.then(res => {
         console.log('*/');
     }
     const output = res.output;
-    if (!argv.no_io_ui) yosys2digitaljs.io_ui(output);
+    if (!argv.no_io_ui) yosys2digitaljs_core.io_ui(output);
     console.log(JSON.stringify(output, null, argv.noindent ? 0 : 2));
     if (argv.html) {
         console.log(');const paper = circuit.displayOn($(\'#paper\'));circuit.start();</script></body></html>');