yosys2digitaljs 0.2.3 → 0.6.0

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@@ -5,7 +5,7 @@ module cycleadder
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  input rst,
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  input en,
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  input [WIDTH-1:0] A,
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- output [WIDTH-1:0] O
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+ output logic [WIDTH-1:0] O
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  );
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  always_ff @(posedge clk)
@@ -5,7 +5,7 @@ module cycleadder
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  input rst,
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  input en,
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  input [WIDTH-1:0] A,
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- output [WIDTH-1:0] O
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+ output logic [WIDTH-1:0] O
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  );
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  always_ff @(posedge clk or posedge rst)
@@ -4,7 +4,7 @@ module d_latch(
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  output q, nq
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  );
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- logic s, r;
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+ logic s, r, nd;
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  nor g1(q, r, nq);
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  nor g2(nq, s, q);
@@ -4,7 +4,7 @@ module d_latch(
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  output q, nq
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  );
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- logic s, r;
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+ logic s, r, nd;
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  nor g1(q, r, nq);
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  nor g2(nq, s, q);
package/tests/fsm.sv CHANGED
@@ -1,6 +1,7 @@
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  // Write your modules here!
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- module fsm(input clk, rst, a, output b);
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+ module fsm(input clk, rst, a, output logic b);
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+ (* fsm_encoding = "auto" *)
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  logic [1:0] state;
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  localparam A = 2'b00;
@@ -10,7 +11,7 @@ module fsm(input clk, rst, a, output b);
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  always_ff @(posedge clk or posedge rst)
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  if (rst) state <= B;
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- else casex(state)
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+ else unique case(state)
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  A: state <= C;
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  B: state <= D;
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  C: if (a) state <= D; else state <= B;
@@ -19,7 +20,7 @@ module fsm(input clk, rst, a, output b);
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  always_comb begin
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  b = 1'bx;
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- case(state)
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+ unique case(state)
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  A, D: b = 0;
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  B: b = 1;
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  C: if (a) b = 1; else b = 0;
package/tsconfig.json ADDED
@@ -0,0 +1,15 @@
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+ {
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+ "compilerOptions": {
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+ "moduleResolution": "node",
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+ "module": "es2015",
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+ "target": "es2017",
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+ "declaration": true,
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+ "allowSyntheticDefaultImports": true,
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+ "outDir": "./dist",
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+ "lib": ["es2017"],
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+ "types": ["node"]
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+ },
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+ "include": [
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+ "src/**/*"
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+ ]
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+ }
package/.travis.yml DELETED
@@ -1,8 +0,0 @@
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- before_install:
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- - sudo add-apt-repository ppa:saltmakrell/ppa -y
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- - sudo apt-get update
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- - sudo apt-get install -y yosys
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-
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- language: node_js
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- node_js:
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- - "8"