yosys2digitaljs 0.2.3 → 0.6.0

package/ChangeLog.md

@@ -0,0 +1,33 @@
+# Changelog
+All notable changes to this project will be documented in this file.
+
+## [0.6.0] -- 2022-02-02
+
+### Added
+
+- Support for Yosys 0.11 cells `$aldff`, `$aldffe`
+- Added a function `yosys2digitaljs` for converting a Yosys JSON output obtained elsewhere, without running Yosys locally
+
+## [0.5.0] -- 2021-10-06
+
+### Added
+
+- Support for Yosys 0.10 cells `$adffe`, `$sdff`, `$sdffe`, `$sdffce`, `$adlatch`, `$sr`, `$dffsr`, `$dffsre`
+- Support for Yosys 0.10 improved memory cell `$mem_v2`
+- Support for source code positions
+
+### Changed
+
+- Support for JSON output generated by Yosys 0.10
+
+## [0.4.0] -- 2021-08-20
+
+### Added
+
+- Linting via Verilator
+
+### Changed
+
+- Ported to TypeScript
+- Removed ad-hoc transformations, as they are now performed in DigitalJS
+

package/README.md

@@ -1,4 +1,3 @@
-[![Build Status](https://travis-ci.org/tilk/yosys2digitaljs.svg?branch=master)](https://travis-ci.org/tilk/yosys2digitaljs)
 # yosys2digitaljs
 This program converts JSON netlist output generated by [Yosys](http://www.clifford.at/yosys/)
 circuit synthesis software for use with the
@@ -25,9 +24,10 @@ The generated JSON is printed on standard output.
 # API
 Yosys2digitaljs can be used as a library. The API is promise (or async/await) based. Available functions are:
 
- - `process_sv(sv_text)` - converts a single SystemVerilog source passed as a string.
- - `process_files(texts)` - converts multiple Verilog/SystemVerilog sources. The `texts` parameter is an object, with keys being file names, and corresponding values containing the file contents as strings. Example: `{ 'test.sv': 'module test; ...' }`.
- - `process(filenames, dirname)` - converts Verilog/SystemVerilog sources saved on the filesystem under names `filenames` in the directory `dirname`.
+ - `yosys2digitaljs(json, options)` - converts the Yosys JSON output `json` (passed as an JS object) to a DigitalJS representation of the same circuit.
+ - `process_sv(sv_text, options)` - converts a single SystemVerilog source passed as a string.
+ - `process_files(texts, options)` - converts multiple Verilog/SystemVerilog sources. The `texts` parameter is an object, with keys being file names, and corresponding values containing the file contents as strings. Example: `{ 'test.sv': 'module test; ...' }`.
+ - `process(filenames, dirname, options)` - converts Verilog/SystemVerilog sources saved on the filesystem under names `filenames` in the directory `dirname`.
 
 The functions return a promise, which fulfills with an object value with following keys:
 

package/dist/index.d.ts

@@ -0,0 +1,164 @@
+#!/usr/bin/env node
+declare namespace Digitaljs {
+    type FilePosition = {
+        line: number;
+        column: number;
+    };
+    type SourcePosition = {
+        name: string;
+        from: FilePosition;
+        to: FilePosition;
+    };
+    type MemReadPort = {
+        clock_polarity?: boolean;
+        enable_polarity?: boolean;
+        arst_polarity?: boolean;
+        srst_polarity?: boolean;
+        enable_srst?: boolean;
+        transparent?: boolean | boolean[];
+        collision?: boolean | boolean[];
+        init_value?: string;
+        arst_value?: string;
+        srst_value?: string;
+    };
+    type MemWritePort = {
+        clock_polarity?: boolean;
+        enable_polarity?: boolean;
+        no_bit_enable?: boolean;
+    };
+    type Device = {
+        type: string;
+        source_positions?: SourcePosition[];
+        [key: string]: any;
+    };
+    type Port = {
+        id: string;
+        port: string;
+    };
+    type Connector = {
+        from: Port;
+        to: Port;
+        name?: string;
+        source_positions?: SourcePosition[];
+    };
+    type Module = {
+        devices: {
+            [key: string]: Device;
+        };
+        connectors: Connector[];
+    };
+    type TopModule = Module & {
+        subcircuits: {
+            [key: string]: Module;
+        };
+    };
+}
+declare namespace Yosys {
+    type BitChar = '0' | '1' | 'x';
+    type Bit = number | '0' | '1' | 'x';
+    type BitVector = Bit[];
+    type Port = {
+        direction: 'input' | 'output' | 'inout';
+        bits: any;
+    };
+    type Parameters = {
+        WIDTH?: JsonConstant;
+        A_WIDTH?: JsonConstant;
+        B_WIDTH?: JsonConstant;
+        S_WIDTH?: JsonConstant;
+        Y_WIDTH?: JsonConstant;
+        A_SIGNED?: JsonConstant;
+        B_SIGNED?: JsonConstant;
+        CLK_POLARITY?: JsonConstant;
+        EN_POLARITY?: JsonConstant;
+        ARST_POLARITY?: JsonConstant;
+        ARST_VALUE: JsonConstant;
+        CTRL_IN_WIDTH?: JsonConstant;
+        CTRL_OUT_WIDTH?: JsonConstant;
+        TRANS_NUM?: JsonConstant;
+        STATE_NUM?: JsonConstant;
+        STATE_NUM_LOG2?: JsonConstant;
+        STATE_RST?: JsonConstant;
+        RD_PORTS?: JsonConstant;
+        WR_PORTS?: JsonConstant;
+        RD_CLK_POLARITY?: JsonConstant;
+        RD_CLK_ENABLE?: JsonConstant;
+        RD_CLK_TRANSPARENT?: JsonConstant;
+        WR_CLK_POLARITY?: JsonConstant;
+        WR_CLK_ENABLE?: JsonConstant;
+        [key: string]: any;
+    };
+    type JsonConstant = number | string;
+    type Attributes = {
+        init: JsonConstant;
+        [key: string]: any;
+    };
+    type Cell = {
+        hide_name: 0 | 1;
+        type: string;
+        parameters: Parameters;
+        attributes: Attributes;
+        port_directions: {
+            [key: string]: 'input' | 'output';
+        };
+        connections: {
+            [key: string]: BitVector;
+        };
+    };
+    type Net = {
+        hide_name: 0 | 1;
+        bits: BitVector;
+        attributes: {
+            [key: string]: string;
+        };
+    };
+    type Module = {
+        ports: {
+            [key: string]: Port;
+        };
+        cells: {
+            [key: string]: Cell;
+        };
+        netnames: {
+            [key: string]: Net;
+        };
+    };
+    type Output = {
+        modules: {
+            [key: string]: Module;
+        };
+    };
+}
+declare type ConvertOptions = {
+    propagation?: number;
+};
+declare type Options = ConvertOptions & {
+    optimize?: boolean;
+    fsmexpand?: boolean;
+    fsm?: boolean | "nomap";
+    timeout?: number;
+    lint?: boolean;
+};
+declare type Output = {
+    output?: Digitaljs.TopModule;
+    yosys_output?: any;
+    yosys_stdout: string;
+    yosys_stderr: string;
+    lint?: LintMessage[];
+};
+declare type LintMessage = {
+    type: string;
+    file: string;
+    line: number;
+    column: number;
+    message: string;
+};
+export declare function verilator_lint(filenames: string[], dirname?: string, options?: Options): Promise<LintMessage[]>;
+export declare function yosys2digitaljs(obj: Yosys.Output, options?: ConvertOptions): Digitaljs.TopModule;
+export declare function process(filenames: string[], dirname?: string, options?: Options): Promise<Output>;
+export declare function io_ui(output: Digitaljs.Module): void;
+export declare function process_files(data: {
+    [key: string]: string;
+}, options?: Options): Promise<Output>;
+export declare function process_sv(text: string, options?: Options): Promise<Output>;
+export {};