web-a2e 1.0.0

package/src/core/cards/mockingboard/ay8910.hpp

@@ -0,0 +1,159 @@
+/*
+ * ay8910.hpp - AY-3-8910 sound chip emulation
+ *
+ * Written by
+ *  Mike Daley <michael_daley@icloud.com>
+ */
+
+#pragma once
+
+#include <cstdint>
+#include <array>
+#include <vector>
+#include <functional>
+
+namespace a2e {
+
+// AY-3-8910 Programmable Sound Generator emulation
+// Used in the Mockingboard sound card (2 chips per card)
+class AY8910 {
+public:
+    static constexpr int NUM_CHANNELS = 3;
+    // Mockingboard uses the Apple II CPU clock divided down
+    // Apple IIe runs at 1.023 MHz (actually 1.0227272... MHz from 14.31818 MHz / 14)
+    static constexpr int PSG_CLOCK = 1023000;  // ~1.023 MHz for accuracy
+
+    using CycleCallback = std::function<uint64_t()>;
+
+    AY8910();
+
+    // Set PSG ID for debug logging (1 or 2)
+    void setPsgId(int id);
+
+    // Enable/disable console debug logging
+    static void setDebugLogging(bool enabled);
+
+    // Set callback to get current CPU cycle (for timestamping register writes)
+    void setCycleCallback(CycleCallback callback) { cycleCallback_ = std::move(callback); }
+
+    // Register access via 6522 VIA
+    void setRegisterAddress(uint8_t address);
+    void writeRegister(uint8_t value);
+    uint8_t readRegister() const;
+
+    // Audio generation - pass cycle range for proper timing
+    void generateSamples(float* buffer, int count, int sampleRate, uint64_t startCycle, uint64_t endCycle);
+    // Legacy version without timing (uses immediate register values)
+    void generateSamples(float* buffer, int count, int sampleRate);
+    void generateChannelSamples(float* buffer, int count, int sampleRate, int channel);
+
+    // Generate a single audio sample at 48kHz using current register state.
+    // Advances PSG internal state by the appropriate number of ticks.
+    // Used for per-instruction incremental audio generation.
+    float generateSingleSample();
+
+    // Channel muting (for debug/mixing purposes)
+    void setChannelMute(int channel, bool muted);
+    bool isChannelMuted(int channel) const;
+
+    // Reset
+    void reset();
+
+    // State access for debugging
+    uint8_t getRegister(int reg) const {
+        return (reg >= 0 && reg < 16) ? registers_[reg] : 0;
+    }
+
+    // Debug: track writes
+    uint32_t getWriteCount() const { return writeCount_; }
+    uint8_t getLastWriteReg() const { return lastWriteReg_; }
+    uint8_t getLastWriteVal() const { return lastWriteVal_; }
+    uint8_t getCurrentRegister() const { return currentRegister_; }
+
+    // State serialization
+    size_t exportState(uint8_t* buffer) const;
+    void importState(const uint8_t* buffer);
+    static constexpr size_t STATE_SIZE = 48;  // Expanded to include noise/envelope counters
+
+private:
+    // Registers
+    static constexpr int REG_TONE_A_FINE = 0;
+    static constexpr int REG_TONE_A_COARSE = 1;
+    static constexpr int REG_TONE_B_FINE = 2;
+    static constexpr int REG_TONE_B_COARSE = 3;
+    static constexpr int REG_TONE_C_FINE = 4;
+    static constexpr int REG_TONE_C_COARSE = 5;
+    static constexpr int REG_NOISE_PERIOD = 6;
+    static constexpr int REG_MIXER = 7;
+    static constexpr int REG_AMP_A = 8;
+    static constexpr int REG_AMP_B = 9;
+    static constexpr int REG_AMP_C = 10;
+    static constexpr int REG_ENV_FINE = 11;
+    static constexpr int REG_ENV_COARSE = 12;
+    static constexpr int REG_ENV_SHAPE = 13;
+    static constexpr int REG_IO_PORT_A = 14;
+    static constexpr int REG_IO_PORT_B = 15;
+
+    // Register array
+    std::array<uint8_t, 16> registers_{};
+    uint8_t currentRegister_ = 0;
+
+    // Tone generator state (3 channels)
+    std::array<uint32_t, 3> toneCounters_{};
+    std::array<bool, 3> toneOutput_{};
+
+    // Channel mute state (for debug/visualization)
+    std::array<bool, 3> channelMuted_{};
+
+    // Noise generator state
+    uint32_t noiseCounter_ = 0;
+    uint32_t noiseShiftReg_ = 1;  // 17-bit LFSR, must not be 0
+    bool noiseToggle_ = false;    // Legacy (kept for state serialization compat)
+
+    // Envelope generator state
+    uint32_t envCounter_ = 0;
+    uint8_t envVolume_ = 0;
+    bool envHolding_ = false;
+    bool envContinue_ = false;   // Bit 3: Continue after first cycle
+    bool envAttack_ = false;     // Bit 2: Attack direction (1=up, 0=down)
+    bool envAlternate_ = false;  // Bit 1: Alternate direction each cycle
+    bool envHold_ = false;       // Bit 0: Hold final value
+
+    // Fractional accumulator for sample rate conversion
+    double phaseAccumulator_ = 0.0;
+
+    // Volume table (4-bit to amplitude)
+    static const float volumeTable_[16];
+
+    // Debug counters
+    uint32_t writeCount_ = 0;
+    uint8_t lastWriteReg_ = 0;
+    uint8_t lastWriteVal_ = 0;
+    int psgId_ = 1;  // PSG identifier for logging
+
+    // Timestamped register writes for accurate sample generation
+    struct RegisterWrite {
+        uint64_t cycle;
+        uint8_t reg;
+        uint8_t value;
+    };
+    std::vector<RegisterWrite> pendingWrites_;
+    CycleCallback cycleCallback_;
+
+    // Apply a register write (internal, doesn't timestamp)
+    void applyRegisterWrite(uint8_t reg, uint8_t value);
+
+    // Helper methods
+    uint16_t getTonePeriod(int channel) const;
+    uint8_t getNoisePeriod() const;
+    uint16_t getEnvPeriod() const;
+    void updateToneGenerator(int channel);
+    void updateNoiseGenerator();
+    void updateEnvelopeGenerator();
+    void handleEnvelopeCycleEnd();
+    float getChannelOutput(int channel) const;
+    // Compute raw mixer output (sum of all unmuted channels, normalized)
+    float computeMixerOutput() const;
+};
+
+} // namespace a2e

package/src/core/cards/mockingboard/via6522.cpp

@@ -0,0 +1,530 @@
+/*
+ * via6522.cpp - VIA 6522 timer chip emulation implementation
+ *
+ * Written by
+ *  Mike Daley <michael_daley@icloud.com>
+ */
+
+#include "via6522.hpp"
+#include "ay8910.hpp"
+#ifdef __EMSCRIPTEN__
+#include <emscripten.h>
+#endif
+
+namespace a2e {
+
+// Debug logging flag
+static bool viaDebugLogging_ = false;
+
+void VIA6522::setDebugLogging(bool enabled) {
+    viaDebugLogging_ = enabled;
+}
+
+void VIA6522::setViaId(int id) {
+    viaId_ = id;
+}
+
+VIA6522::VIA6522() {
+    reset();
+}
+
+void VIA6522::reset() {
+    ora_ = 0;
+    orb_ = 0;
+    ddra_ = 0;
+    ddrb_ = 0;
+    ira_ = 0xFF;  // Floating high
+    irb_ = 0xFF;
+
+    t1Counter_ = 0xFFFF;
+    t1Latch_ = 0xFFFF;
+    t1Running_ = false;
+    t1Fired_ = false;
+
+    t2Counter_ = 0xFFFF;
+    t2LatchLow_ = 0xFF;
+    t2Running_ = false;
+    t2Fired_ = false;
+
+    sr_ = 0;
+    acr_ = 0;
+    pcr_ = 0;
+    ifr_ = 0;
+    ier_ = 0;
+
+    prevPsgControl_ = 0;
+    psgAddressLatched_ = false;
+    psgState_ = PSG_INACTIVE;
+    busDriven_ = false;
+    prevIrqActive_ = false;
+    t1IrqDelay_ = 0;
+    t2IrqDelay_ = 0;
+}
+
+uint8_t VIA6522::read(uint8_t reg) {
+    reg &= 0x0F;
+
+    switch (reg) {
+        case REG_ORB:
+            // Reading ORB clears CB1/CB2 interrupt flags
+            ifr_ &= ~(IRQ_CB1 | IRQ_CB2);
+            checkIRQ();
+            // Return output bits where direction is output, input where direction is input
+            return (orb_ & ddrb_) | (irb_ & ~ddrb_);
+
+        case REG_ORA:
+        case REG_ORA_NH:
+            // Reading ORA clears CA1/CA2 interrupt flags (unless ORA_NH)
+            if (reg == REG_ORA) {
+                ifr_ &= ~(IRQ_CA1 | IRQ_CA2);
+                checkIRQ();
+            }
+            {
+                // Input pins: driven by PSG if in READ mode (use ira_), else float high
+                uint8_t inputBits = busDriven_ ? ira_ : 0xFF;
+                return (ora_ & ddra_) | (inputBits & ~ddra_);
+            }
+
+        case REG_DDRB:
+            return ddrb_;
+
+        case REG_DDRA:
+            return ddra_;
+
+        case REG_T1CL:
+            // Reading T1CL clears T1 interrupt flag
+            ifr_ &= ~IRQ_T1;
+            checkIRQ();
+            return t1Counter_ & 0xFF;
+
+        case REG_T1CH:
+            return (t1Counter_ >> 8) & 0xFF;
+
+        case REG_T1LL:
+            return t1Latch_ & 0xFF;
+
+        case REG_T1LH:
+            return (t1Latch_ >> 8) & 0xFF;
+
+        case REG_T2CL:
+            // Reading T2CL clears T2 interrupt flag
+            ifr_ &= ~IRQ_T2;
+            checkIRQ();
+            return t2Counter_ & 0xFF;
+
+        case REG_T2CH:
+            return (t2Counter_ >> 8) & 0xFF;
+
+        case REG_SR:
+            return sr_;
+
+        case REG_ACR:
+            return acr_;
+
+        case REG_PCR:
+            return pcr_;
+
+        case REG_IFR:
+            // Bit 7 is set if any enabled interrupt flag is set
+            if (ifr_ & ier_ & 0x7F) {
+                return ifr_ | IRQ_ANY;
+            }
+            return ifr_;
+
+        case REG_IER:
+            // Reading IER returns bit 7 = 1
+            return ier_ | 0x80;
+
+        default:
+            return 0xFF;
+    }
+}
+
+void VIA6522::write(uint8_t reg, uint8_t value) {
+    reg &= 0x0F;
+
+    switch (reg) {
+        case REG_ORB:
+            orb_ = value;
+            // Writing ORB clears CB1/CB2 interrupt flags
+            ifr_ &= ~(IRQ_CB1 | IRQ_CB2);
+            checkIRQ();
+            updatePSG();
+            break;
+
+        case REG_ORA:
+        case REG_ORA_NH:
+            ora_ = value;
+            // Writing ORA clears CA1/CA2 interrupt flags (unless ORA_NH)
+            if (reg == REG_ORA) {
+                ifr_ &= ~(IRQ_CA1 | IRQ_CA2);
+                checkIRQ();
+            }
+            updatePSG();
+            break;
+
+        case REG_DDRB:
+            ddrb_ = value;
+            break;
+
+        case REG_DDRA:
+            ddra_ = value;
+            break;
+
+        case REG_T1CL:
+        case REG_T1LL:
+            t1Latch_ = (t1Latch_ & 0xFF00) | value;
+            break;
+
+        case REG_T1CH:
+            t1Latch_ = (t1Latch_ & 0x00FF) | (value << 8);
+            // Writing T1CH also loads counter and clears interrupt
+            // Real 6522 period = latch + 2 (Rockwell datasheet Fig.16)
+            // Counter starts at latch + 1 (the +2nd cycle is the write itself)
+            t1Counter_ = t1Latch_ + 1;
+            t1Running_ = true;
+            t1Fired_ = false;
+            ifr_ &= ~IRQ_T1;
+            checkIRQ();
+            break;
+
+        case REG_T1LH:
+            t1Latch_ = (t1Latch_ & 0x00FF) | (value << 8);
+            // Just updates latch, doesn't affect counter
+            ifr_ &= ~IRQ_T1;  // Clears interrupt flag
+            checkIRQ();
+            break;
+
+        case REG_T2CL:
+            t2LatchLow_ = value;
+            break;
+
+        case REG_T2CH:
+            t2Counter_ = t2LatchLow_ | (value << 8);
+            t2Counter_ += 1;  // +1 extra cycle for proper period (total = latch + 2)
+            t2Running_ = true;
+            t2Fired_ = false;
+            ifr_ &= ~IRQ_T2;
+            checkIRQ();
+            break;
+
+        case REG_SR:
+            sr_ = value;
+            break;
+
+        case REG_ACR: {
+            uint8_t oldAcr = acr_;
+            acr_ = value;
+            // If Timer 1 mode changed (one-shot <-> free-running), reset fired flag
+            // so the timer can fire again after a mode transition
+            if ((oldAcr & 0x40) != (value & 0x40)) {
+                t1Fired_ = false;
+            }
+            break;
+        }
+
+        case REG_PCR:
+            pcr_ = value;
+            break;
+
+        case REG_IFR:
+            // Writing 1 to a bit clears that interrupt flag
+            ifr_ &= ~(value & 0x7F);
+            checkIRQ();
+            break;
+
+        case REG_IER:
+            // Bit 7 controls set/clear mode
+            if (value & 0x80) {
+                // Set bits
+                ier_ |= (value & 0x7F);
+            } else {
+                // Clear bits
+                ier_ &= ~(value & 0x7F);
+            }
+            checkIRQ();
+            break;
+    }
+}
+
+void VIA6522::update(int cycles) {
+    if (cycles <= 0) return;
+
+    uint32_t cyclesToProcess = static_cast<uint32_t>(cycles);
+
+    // Update Timer 1
+    // Counter always decrements (needed for detection to verify card presence)
+    // But interrupts and proper reload only happen when timer is "armed" (T1CH written)
+    if (cyclesToProcess > t1Counter_) {
+        // Timer 1 underflowed
+        uint32_t overflow = cyclesToProcess - t1Counter_ - 1;
+
+        if (t1Running_) {
+            // Timer is armed - generate interrupt and handle reload
+            if (!t1Fired_) {
+                ifr_ |= IRQ_T1;
+                checkIRQ();
+                t1Fired_ = true;
+            }
+
+            // Check ACR for timer mode
+            if (acr_ & 0x40) {
+                // Free-running mode - reload from latch and continue
+                // Real 6522 period = latch + 2 (Rockwell datasheet)
+                uint32_t period = static_cast<uint32_t>(t1Latch_) + 2;
+                overflow = overflow % period;
+                t1Counter_ = static_cast<uint16_t>(t1Latch_ + 1 - overflow);
+                t1Fired_ = false;  // Can fire again next time
+            } else {
+                // One-shot mode - counter wraps but doesn't reload or re-fire
+                t1Counter_ = static_cast<uint16_t>(0xFFFF - (overflow % 0x10000));
+            }
+        } else {
+            // Timer not armed - just wrap counter naturally (for detection)
+            t1Counter_ = static_cast<uint16_t>(0xFFFF - (overflow % 0x10000));
+        }
+    } else {
+        t1Counter_ -= static_cast<uint16_t>(cyclesToProcess);
+    }
+
+    // Update Timer 2
+    // Timer 2 also always decrements (in timed mode)
+    if (!(acr_ & 0x20)) {  // Timed mode (not pulse counting)
+        if (cyclesToProcess > t2Counter_) {
+            // Timer 2 underflowed
+            uint32_t overflow = cyclesToProcess - t2Counter_ - 1;
+
+            if (t2Running_ && !t2Fired_) {
+                ifr_ |= IRQ_T2;
+                checkIRQ();
+                t2Fired_ = true;
+            }
+            // Timer 2 is one-shot only - wraps but doesn't reload or re-fire
+            t2Counter_ = static_cast<uint16_t>(0xFFFF - (overflow % 0x10000));
+        } else {
+            t2Counter_ -= static_cast<uint16_t>(cyclesToProcess);
+        }
+    }
+}
+
+void VIA6522::updatePSG() {
+    if (!psg_) return;
+
+    // Port B controls the PSG via BC1, BDIR, and RESET lines
+    // BC1 = bit 0, BDIR = bit 1, ~RESET = bit 2 (active low)
+    // Note: Only look at bits that are configured as outputs
+    uint8_t control = orb_ & ddrb_ & 0x07;
+
+    // Check for PSG reset - bit 2 going low resets the PSG
+    // This is used by software to silence the PSG when done playing
+    bool resetActive = (control & 0x04) == 0;  // Bit 2 = 0 means reset active
+    bool wasResetActive = (prevPsgControl_ & 0x04) == 0;
+
+    if (resetActive && !wasResetActive) {
+        // Reset just became active - reset the PSG
+        psg_->reset();
+#ifdef __EMSCRIPTEN__
+        if (viaDebugLogging_) {
+            EM_ASM({
+                console.log("VIA" + $0 + ": PSG RESET asserted");
+            }, viaId_);
+        }
+#endif
+    }
+
+    // Only perform PSG operations on state TRANSITIONS
+    if (control == prevPsgControl_) {
+        return;  // No change in control state
+    }
+
+    uint8_t prevControl = prevPsgControl_;
+    prevPsgControl_ = control;
+
+#ifdef __EMSCRIPTEN__
+    if (viaDebugLogging_) {
+        EM_ASM({
+            console.log("VIA" + $4 + ": ctrl " + $0 + "->" + $1 + " ORA=0x" + $2.toString(16) + " DDRA=0x" + $3.toString(16));
+        }, prevControl, control, ora_, ddra_, viaId_);
+    }
+#endif
+
+    // Compute PSG function from control bits: BC1=bit0, BDIR=bit1
+    // 0b00=INACTIVE, 0b01=READ, 0b10=WRITE, 0b11=LATCH
+    uint8_t psgFunc = control & 0x03;  // Mask out reset bit
+    PsgState newState;
+    switch (psgFunc) {
+        case 0x00: newState = PSG_INACTIVE; break;
+        case 0x01: newState = PSG_READ;     break;
+        case 0x02: newState = PSG_WRITE;    break;
+        case 0x03: newState = PSG_LATCH;    break;
+        default:   newState = PSG_INACTIVE; break;
+    }
+
+    // AppleWin-style: operations only execute when transitioning FROM inactive
+    if (psgState_ != PSG_INACTIVE) {
+        // Not inactive - just update state and return, no operation
+        busDriven_ = (newState == PSG_READ && psgAddressLatched_);
+        psgState_ = newState;
+        return;
+    }
+
+    // Was inactive - execute the operation, then update state
+    psgState_ = newState;
+
+    if (newState == PSG_INACTIVE) {
+        busDriven_ = false;
+        return;
+    }
+
+    if (newState == PSG_LATCH) {
+        busDriven_ = false;
+        uint8_t addr = ora_ & ddra_;
+        if (addr <= 0x0F) {
+            psg_->setRegisterAddress(addr);
+            psgAddressLatched_ = true;
+        } else {
+            psgAddressLatched_ = false;
+#ifdef __EMSCRIPTEN__
+            if (viaDebugLogging_) {
+                EM_ASM({
+                    console.log("VIA: Rejected invalid address 0x" + $0.toString(16).toUpperCase());
+                }, addr);
+            }
+#endif
+        }
+        return;
+    }
+
+    if (newState == PSG_WRITE) {
+        busDriven_ = false;
+        if (psgAddressLatched_) {
+            psg_->writeRegister(ora_ & ddra_);
+        } else {
+#ifdef __EMSCRIPTEN__
+            if (viaDebugLogging_) {
+                EM_ASM({
+                    console.log("VIA: Write rejected - no address latched, data=0x" + $0.toString(16).toUpperCase());
+                }, ora_ & ddra_);
+            }
+#endif
+        }
+        return;
+    }
+
+    if (newState == PSG_READ) {
+        if (psgAddressLatched_) {
+            ira_ = psg_->readRegister();
+            busDriven_ = true;
+        } else {
+            busDriven_ = false;
+        }
+    }
+}
+
+void VIA6522::checkIRQ() {
+    bool irqActive = (ifr_ & ier_ & 0x7F) != 0;
+
+    // Only trigger callback on transition from inactive to active
+    // This prevents multiple IRQ assertions during a single interrupt handler
+    if (irqActive && !prevIrqActive_) {
+        if (irqCallback_) {
+            irqCallback_();
+        }
+    }
+
+    prevIrqActive_ = irqActive;
+}
+
+size_t VIA6522::exportState(uint8_t* buffer) const {
+    size_t offset = 0;
+
+    // Port registers
+    buffer[offset++] = ora_;
+    buffer[offset++] = orb_;
+    buffer[offset++] = ddra_;
+    buffer[offset++] = ddrb_;
+    buffer[offset++] = ira_;
+    buffer[offset++] = irb_;
+
+    // Timer 1
+    buffer[offset++] = t1Counter_ & 0xFF;
+    buffer[offset++] = (t1Counter_ >> 8) & 0xFF;
+    buffer[offset++] = t1Latch_ & 0xFF;
+    buffer[offset++] = (t1Latch_ >> 8) & 0xFF;
+    buffer[offset++] = (t1Running_ ? 1 : 0) | (t1Fired_ ? 2 : 0);
+
+    // Timer 2
+    buffer[offset++] = t2Counter_ & 0xFF;
+    buffer[offset++] = (t2Counter_ >> 8) & 0xFF;
+    buffer[offset++] = t2LatchLow_;
+    buffer[offset++] = (t2Running_ ? 1 : 0) | (t2Fired_ ? 2 : 0);
+
+    // Control registers
+    buffer[offset++] = sr_;
+    buffer[offset++] = acr_;
+    buffer[offset++] = pcr_;
+    buffer[offset++] = ifr_;
+    buffer[offset++] = ier_;
+
+    // PSG control state
+    buffer[offset++] = prevPsgControl_;
+    buffer[offset++] = psgAddressLatched_ ? 1 : 0;
+    buffer[offset++] = static_cast<uint8_t>(psgState_);
+    buffer[offset++] = busDriven_ ? 1 : 0;
+
+    // Pad to STATE_SIZE for consistent serialization
+    while (offset < STATE_SIZE) {
+        buffer[offset++] = 0;
+    }
+
+    return offset;  // Exactly STATE_SIZE bytes
+}
+
+void VIA6522::importState(const uint8_t* buffer) {
+    size_t offset = 0;
+
+    // Port registers
+    ora_ = buffer[offset++];
+    orb_ = buffer[offset++];
+    ddra_ = buffer[offset++];
+    ddrb_ = buffer[offset++];
+    ira_ = buffer[offset++];
+    irb_ = buffer[offset++];
+
+    // Timer 1
+    t1Counter_ = buffer[offset] | (buffer[offset + 1] << 8);
+    offset += 2;
+    t1Latch_ = buffer[offset] | (buffer[offset + 1] << 8);
+    offset += 2;
+    uint8_t t1Flags = buffer[offset++];
+    t1Running_ = (t1Flags & 1) != 0;
+    t1Fired_ = (t1Flags & 2) != 0;
+
+    // Timer 2
+    t2Counter_ = buffer[offset] | (buffer[offset + 1] << 8);
+    offset += 2;
+    t2LatchLow_ = buffer[offset++];
+    uint8_t t2Flags = buffer[offset++];
+    t2Running_ = (t2Flags & 1) != 0;
+    t2Fired_ = (t2Flags & 2) != 0;
+
+    // Control registers
+    sr_ = buffer[offset++];
+    acr_ = buffer[offset++];
+    pcr_ = buffer[offset++];
+    ifr_ = buffer[offset++];
+    ier_ = buffer[offset++];
+
+    // PSG control state
+    prevPsgControl_ = buffer[offset++];
+    psgAddressLatched_ = buffer[offset++] != 0;
+    psgState_ = static_cast<PsgState>(buffer[offset++]);
+    busDriven_ = buffer[offset++] != 0;
+
+    // Restore IRQ state
+    prevIrqActive_ = (ifr_ & ier_ & 0x7F) != 0;
+    t1IrqDelay_ = 0;
+    t2IrqDelay_ = 0;
+}
+
+} // namespace a2e