tasmota-webserial-esptool 9.2.7 → 9.2.9

package/src/const.ts

@@ -80,7 +80,7 @@ export const ESP8266_SPI_MOSI_DLEN_OFFS = -1;
 export const ESP8266_SPI_MISO_DLEN_OFFS = -1;
 export const ESP8266_SPI_W0_OFFS = 0x40;
 export const ESP8266_UART_DATE_REG_ADDR = 0x60000078;
-export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0000;
 
 export const ESP32_SPI_REG_BASE = 0x3ff42000;
 export const ESP32_BASEFUSEADDR = 0x3ff5a000;
@@ -105,12 +105,23 @@ export const ESP32S2_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32S2_SPI_W0_OFFS = 0x58;
 export const ESP32S2_UART_DATE_REG_ADDR = 0x60000078;
 export const ESP32S2_BOOTLOADER_FLASH_OFFSET = 0x1000;
-
 // ESP32-S2 RTC Watchdog Timer registers for USB-OTG reset
-export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = 0x3f4080ac;
-export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = 0x3f408094;
-export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = 0x3f408098;
+export const ESP32S2_RTCCNTL_BASE_REG = 0x3f408000;
+export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32S2_RTCCNTL_BASE_REG + 0x00ac;
+export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32S2_RTCCNTL_BASE_REG + 0x0094;
+export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32S2_RTCCNTL_BASE_REG + 0x0098;
 export const ESP32S2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+// ESP32-S2 GPIO strap register and boot mode control
+export const ESP32S2_GPIO_STRAP_REG = 0x3f404038;
+export const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
+export const ESP32S2_GPIO_STRAP_VDDSPI_MASK = 1 << 4; // SPI voltage (1.8V vs 3.3V)
+export const ESP32S2_RTC_CNTL_OPTION1_REG = 0x3f408128;
+export const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
+export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which indicates the port in use
+export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
 
 export const ESP32S3_SPI_REG_BASE = 0x60002000;
 export const ESP32S3_BASEFUSEADDR = 0x60007000;
@@ -122,13 +133,25 @@ export const ESP32S3_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32S3_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32S3_SPI_W0_OFFS = 0x58;
 export const ESP32S3_UART_DATE_REG_ADDR = 0x60000080;
-export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0;
-
+export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0000;
 // ESP32-S3 RTC Watchdog Timer registers for USB-OTG reset
-export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = 0x600080b0;
-export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = 0x60008098;
-export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = 0x6000809c;
+export const ESP32S3_RTCCNTL_BASE_REG = 0x60008000;
+export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32S3_RTCCNTL_BASE_REG + 0x00b0;
+export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32S3_RTCCNTL_BASE_REG + 0x0098;
+export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32S3_RTCCNTL_BASE_REG + 0x009c;
 export const ESP32S3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+// ESP32-S3 GPIO strap register and boot mode control
+export const ESP32S3_GPIO_STRAP_REG = 0x60004038;
+export const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
+export const ESP32S3_GPIO_STRAP_VDDSPI_MASK = 1 << 4;
+export const ESP32S3_RTC_CNTL_OPTION1_REG = 0x6000812c;
+export const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
+export const ESP32S3_UARTDEV_BUF_NO = 0x3fcef14c; // Variable in ROM .bss which indicates the port in use
+export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG is used
+export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
 
 export const ESP32C2_SPI_REG_BASE = 0x60002000;
 export const ESP32C2_BASEFUSEADDR = 0x60008800;
@@ -140,10 +163,20 @@ export const ESP32C2_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C2_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C2_SPI_W0_OFFS = 0x58;
 export const ESP32C2_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C2 RTC Watchdog Timer registers
+export const ESP32C2_RTCCNTL_BASE_REG = 0x60008000;
+export const ESP32C2_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32C2_RTCCNTL_BASE_REG + 0x009c;
+export const ESP32C2_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32C2_RTCCNTL_BASE_REG + 0x0084;
+export const ESP32C2_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32C2_RTCCNTL_BASE_REG + 0x0088;
+export const ESP32C2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
 
 export const ESP32C3_SPI_REG_BASE = 0x60002000;
 export const ESP32C3_BASEFUSEADDR = 0x60008800;
+export const ESP32C3_EFUSE_BLOCK1_ADDR = ESP32C3_BASEFUSEADDR + 0x044;
 export const ESP32C3_MACFUSEADDR = 0x60008800 + 0x044;
 export const ESP32C3_SPI_USR_OFFS = 0x18;
 export const ESP32C3_SPI_USR1_OFFS = 0x1c;
@@ -152,7 +185,28 @@ export const ESP32C3_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C3_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C3_SPI_W0_OFFS = 0x58;
 export const ESP32C3_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C3 RTC Watchdog Timer registers
+export const ESP32C3_RTC_CNTL_BASE_REG = 0x60008000;
+export const ESP32C3_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32C3_RTC_CNTL_BASE_REG + 0x00a8;
+export const ESP32C3_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32C3_RTC_CNTL_BASE_REG + 0x0090;
+export const ESP32C3_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32C3_RTC_CNTL_BASE_REG + 0x0094;
+export const ESP32C3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32C3_RTC_CNTL_SWD_WKEY = 0x8f1d312a;
+export const ESP32C3_RTC_CNTL_SWD_CONF_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00ac;
+export const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31;
+export const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG =
+  ESP32C3_RTC_CNTL_BASE_REG + 0x00b0;
+export const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
+export const ESP32C3_BUF_UART_NO_OFFSET = 24;
+// Note: ESP32C3_BSS_UART_DEV_ADDR is calculated dynamically based on chip revision in esp_loader.ts
+// Revision < 101: 0x3FCDF064, Revision >= 101: 0x3FCDF060
+// ESP32-C3 EFUSE registers for chip revision detection
+export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
+export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
 
 export const ESP32C5_SPI_REG_BASE = 0x60003000;
 export const ESP32C5_BASEFUSEADDR = 0x600b4800;
@@ -165,6 +219,9 @@ export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C5_SPI_W0_OFFS = 0x58;
 export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
 export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-C5 USB-JTAG/Serial detection
+export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
+export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 
 export const ESP32C6_SPI_REG_BASE = 0x60003000;
 export const ESP32C6_BASEFUSEADDR = 0x600b0800;
@@ -176,7 +233,35 @@ export const ESP32C6_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C6_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C6_SPI_W0_OFFS = 0x58;
 export const ESP32C6_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-C6 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32C6_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32C6_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32C6_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32C6_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-C6 USB-JTAG/Serial detection
+export const ESP32C6_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
+export const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
+
+// ESP32-C5/C6 LP Watchdog Timer registers (Low Power WDT)
+export const ESP32C5_C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY
+export const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG =
+  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_SWD_CONFIG_REG
+export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
+export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG =
+  ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
 
 export const ESP32C61_SPI_REG_BASE = 0x60003000;
 export const ESP32C61_BASEFUSEADDR = 0x600b4800;
@@ -188,7 +273,7 @@ export const ESP32C61_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32C61_SPI_W0_OFFS = 0x58;
 export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
 
 export const ESP32H2_SPI_REG_BASE = 0x60003000;
 export const ESP32H2_BASEFUSEADDR = 0x600b0800;
@@ -200,7 +285,20 @@ export const ESP32H2_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32H2_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H2_SPI_W0_OFFS = 0x58;
 export const ESP32H2_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-H2 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32H2_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32H2_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32H2_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32H2_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32H2_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32H2_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32H2_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H2_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32H2_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-H2 USB-JTAG/Serial detection
+export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which indicates the port in use
+export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
 
 export const ESP32H4_SPI_REG_BASE = 0x60099000;
 export const ESP32H4_BASEFUSEADDR = 0x600b1800;
@@ -213,6 +311,16 @@ export const ESP32H4_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H4_SPI_W0_OFFS = 0x58;
 export const ESP32H4_UART_DATE_REG_ADDR = 0x60012000 + 0x7c;
 export const ESP32H4_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-H4 RTC Watchdog Timer registers
+export const ESP32H4_DR_REG_LP_WDT_BASE = 0x600b5400;
+export const ESP32H4_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32H4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
+export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32H4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
+export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
+export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 
 export const ESP32H21_SPI_REG_BASE = 0x60003000;
 export const ESP32H21_BASEFUSEADDR = 0x600b4000;
@@ -224,7 +332,17 @@ export const ESP32H21_SPI_MOSI_DLEN_OFFS = 0x24;
 export const ESP32H21_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32H21_SPI_W0_OFFS = 0x58;
 export const ESP32H21_UART_DATE_REG_ADDR = 0x6000007c;
-export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0;
+export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0000;
+// ESP32-H21 RTC Watchdog Timer registers (LP_WDT)
+export const ESP32H21_DR_REG_LP_WDT_BASE = 0x600b1c00;
+export const ESP32H21_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32H21_DR_REG_LP_WDT_BASE + 0x001c;
+export const ESP32H21_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32H21_DR_REG_LP_WDT_BASE + 0x0000;
+export const ESP32H21_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32H21_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
+export const ESP32H21_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32H21_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
 
 export const ESP32P4_SPI_REG_BASE = 0x5008d000;
 export const ESP32P4_BASEFUSEADDR = 0x5012d000;
@@ -238,6 +356,33 @@ export const ESP32P4_SPI_MISO_DLEN_OFFS = 0x28;
 export const ESP32P4_SPI_W0_OFFS = 0x58;
 export const ESP32P4_UART_DATE_REG_ADDR = 0x500ca000 + 0x8c;
 export const ESP32P4_BOOTLOADER_FLASH_OFFSET = 0x2000;
+// ESP32-P4 RTC Watchdog Timer registers
+export const ESP32P4_DR_REG_LP_WDT_BASE = 0x50116000;
+export const ESP32P4_RTC_CNTL_WDTWPROTECT_REG =
+  ESP32P4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_WPROTECT_REG
+export const ESP32P4_RTC_CNTL_WDTCONFIG0_REG =
+  ESP32P4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_CONFIG0_REG
+export const ESP32P4_RTC_CNTL_WDTCONFIG1_REG =
+  ESP32P4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_CONFIG1_REG
+export const ESP32P4_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
+export const ESP32P4_RTC_CNTL_SWD_CONF_REG =
+  ESP32P4_DR_REG_LP_WDT_BASE + 0x001c; // RTC_WDT_SWD_CONFIG_REG
+export const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
+export const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG =
+  ESP32P4_DR_REG_LP_WDT_BASE + 0x0020; // RTC_WDT_SWD_WPROTECT_REG
+export const ESP32P4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // RTC_WDT_SWD_WKEY, same as WDT key in this case
+// ESP32-P4 USB-JTAG/Serial and USB-OTG detection
+// Note: UARTDEV_BUF_NO is dynamic based on chip revision
+// Revision < 300: 0x4FF3FEB0 + 24 = 0x4FF3FEC8
+// Revision >= 300: 0x4FFBFEB0 + 24 = 0x4FFBFEC8
+export const ESP32P4_UARTDEV_BUF_NO_REV0 = 0x4ff3fec8; // Variable in ROM .bss (revision < 300)
+export const ESP32P4_UARTDEV_BUF_NO_REV300 = 0x4ffbfec8; // Variable in ROM .bss (revision >= 300)
+export const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5; // The above var when USB-OTG is used
+export const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6; // The above var when USB-JTAG/Serial is used
+export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
+export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
+export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
+export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?
 
 export const ESP32S31_SPI_REG_BASE = 0x20500000;
 export const ESP32S31_BASEFUSEADDR = 0x20715000;