tasmota-webserial-esptool 9.2.7 → 9.2.9

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Files changed (9) hide show
  1. package/dist/const.d.ts +97 -6
  2. package/dist/const.js +125 -14
  3. package/dist/esp_loader.d.ts +108 -2
  4. package/dist/esp_loader.js +634 -44
  5. package/dist/web/index.js +1 -1
  6. package/js/modules/esptool.js +1 -1
  7. package/package.json +1 -1
  8. package/src/const.ts +161 -16
  9. package/src/esp_loader.ts +774 -43
package/dist/const.d.ts CHANGED
@@ -67,10 +67,18 @@ export declare const ESP32S2_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32S2_SPI_W0_OFFS = 88;
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  export declare const ESP32S2_UART_DATE_REG_ADDR = 1610612856;
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  export declare const ESP32S2_BOOTLOADER_FLASH_OFFSET = 4096;
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- export declare const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = 1061191852;
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- export declare const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = 1061191828;
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- export declare const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = 1061191832;
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+ export declare const ESP32S2_RTCCNTL_BASE_REG = 1061191680;
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+ export declare const ESP32S2_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32S2_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32S2_RTC_CNTL_WDTCONFIG1_REG: number;
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  export declare const ESP32S2_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32S2_GPIO_STRAP_REG = 1061175352;
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+ export declare const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK: number;
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+ export declare const ESP32S2_GPIO_STRAP_VDDSPI_MASK: number;
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+ export declare const ESP32S2_RTC_CNTL_OPTION1_REG = 1061191976;
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+ export declare const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
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+ export declare const ESP32S2_UARTDEV_BUF_NO = 1073741076;
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+ export declare const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2;
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  export declare const ESP32S3_SPI_REG_BASE = 1610620928;
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  export declare const ESP32S3_BASEFUSEADDR = 1610641408;
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  export declare const ESP32S3_MACFUSEADDR: number;
@@ -82,10 +90,19 @@ export declare const ESP32S3_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32S3_SPI_W0_OFFS = 88;
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  export declare const ESP32S3_UART_DATE_REG_ADDR = 1610612864;
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  export declare const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0;
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- export declare const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = 1610645680;
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- export declare const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = 1610645656;
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- export declare const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = 1610645660;
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+ export declare const ESP32S3_RTCCNTL_BASE_REG = 1610645504;
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+ export declare const ESP32S3_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32S3_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32S3_RTC_CNTL_WDTCONFIG1_REG: number;
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  export declare const ESP32S3_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32S3_GPIO_STRAP_REG = 1610629176;
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+ export declare const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK: number;
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+ export declare const ESP32S3_GPIO_STRAP_VDDSPI_MASK: number;
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+ export declare const ESP32S3_RTC_CNTL_OPTION1_REG = 1610645804;
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+ export declare const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 1;
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+ export declare const ESP32S3_UARTDEV_BUF_NO = 1070526796;
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+ export declare const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3;
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+ export declare const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4;
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  export declare const ESP32C2_SPI_REG_BASE = 1610620928;
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  export declare const ESP32C2_BASEFUSEADDR = 1610647552;
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  export declare const ESP32C2_MACFUSEADDR: number;
@@ -97,8 +114,14 @@ export declare const ESP32C2_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32C2_SPI_W0_OFFS = 88;
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  export declare const ESP32C2_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0;
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+ export declare const ESP32C2_RTCCNTL_BASE_REG = 1610645504;
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+ export declare const ESP32C2_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32C2_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32C2_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32C2_RTC_CNTL_WDT_WKEY = 1356348065;
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  export declare const ESP32C3_SPI_REG_BASE = 1610620928;
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  export declare const ESP32C3_BASEFUSEADDR = 1610647552;
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+ export declare const ESP32C3_EFUSE_BLOCK1_ADDR: number;
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  export declare const ESP32C3_MACFUSEADDR: number;
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  export declare const ESP32C3_SPI_USR_OFFS = 24;
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  export declare const ESP32C3_SPI_USR1_OFFS = 28;
@@ -108,6 +131,19 @@ export declare const ESP32C3_SPI_MISO_DLEN_OFFS = 40;
108
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  export declare const ESP32C3_SPI_W0_OFFS = 88;
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  export declare const ESP32C3_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0;
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+ export declare const ESP32C3_RTC_CNTL_BASE_REG = 1610645504;
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+ export declare const ESP32C3_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32C3_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32C3_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32C3_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32C3_RTC_CNTL_SWD_WKEY = 2401055018;
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+ export declare const ESP32C3_RTC_CNTL_SWD_CONF_REG: number;
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+ export declare const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN: number;
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+ export declare const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG: number;
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+ export declare const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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+ export declare const ESP32C3_BUF_UART_NO_OFFSET = 24;
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+ export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 1610647632;
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+ export declare const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 1610647640;
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  export declare const ESP32C5_SPI_REG_BASE = 1610625024;
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  export declare const ESP32C5_BASEFUSEADDR = 1611352064;
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  export declare const ESP32C5_MACFUSEADDR: number;
@@ -119,6 +155,8 @@ export declare const ESP32C5_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32C5_SPI_W0_OFFS = 88;
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  export declare const ESP32C5_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32C5_BOOTLOADER_FLASH_OFFSET = 8192;
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+ export declare const ESP32C5_UARTDEV_BUF_NO = 1082520852;
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+ export declare const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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  export declare const ESP32C6_SPI_REG_BASE = 1610625024;
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  export declare const ESP32C6_BASEFUSEADDR = 1611335680;
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  export declare const ESP32C6_MACFUSEADDR: number;
@@ -130,6 +168,22 @@ export declare const ESP32C6_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32C6_SPI_W0_OFFS = 88;
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  export declare const ESP32C6_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0;
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+ export declare const ESP32C6_DR_REG_LP_WDT_BASE = 1611340800;
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+ export declare const ESP32C6_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32C6_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32C6_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32C6_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32C6_RTC_CNTL_SWD_WKEY = 1356348065;
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+ export declare const ESP32C6_UARTDEV_BUF_NO = 1082652032;
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+ export declare const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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+ export declare const ESP32C5_C6_DR_REG_LP_WDT_BASE = 1611340800;
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+ export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG: number;
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+ export declare const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN: number;
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+ export declare const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG: number;
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  export declare const ESP32C61_SPI_REG_BASE = 1610625024;
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  export declare const ESP32C61_BASEFUSEADDR = 1611352064;
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  export declare const ESP32C61_MACFUSEADDR: number;
@@ -152,6 +206,14 @@ export declare const ESP32H2_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32H2_SPI_W0_OFFS = 88;
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  export declare const ESP32H2_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0;
209
+ export declare const ESP32H2_DR_REG_LP_WDT_BASE = 1611340800;
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+ export declare const ESP32H2_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32H2_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32H2_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32H2_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32H2_RTC_CNTL_SWD_WKEY = 1356348065;
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+ export declare const ESP32H2_UARTDEV_BUF_NO = 1082457852;
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+ export declare const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3;
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  export declare const ESP32H4_SPI_REG_BASE = 1611239424;
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  export declare const ESP32H4_BASEFUSEADDR = 1611339776;
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  export declare const ESP32H4_MACFUSEADDR: number;
@@ -163,6 +225,12 @@ export declare const ESP32H4_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32H4_SPI_W0_OFFS = 88;
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  export declare const ESP32H4_UART_DATE_REG_ADDR: number;
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  export declare const ESP32H4_BOOTLOADER_FLASH_OFFSET = 8192;
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+ export declare const ESP32H4_DR_REG_LP_WDT_BASE = 1611355136;
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+ export declare const ESP32H4_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32H4_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32H4_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32H4_RTC_CNTL_WDT_WKEY = 1356348065;
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+ export declare const ESP32H4_RTC_CNTL_SWD_WKEY = 1356348065;
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  export declare const ESP32H21_SPI_REG_BASE = 1610625024;
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  export declare const ESP32H21_BASEFUSEADDR = 1611350016;
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  export declare const ESP32H21_MACFUSEADDR: number;
@@ -174,6 +242,12 @@ export declare const ESP32H21_SPI_MISO_DLEN_OFFS = 40;
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  export declare const ESP32H21_SPI_W0_OFFS = 88;
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  export declare const ESP32H21_UART_DATE_REG_ADDR = 1610612860;
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  export declare const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0;
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+ export declare const ESP32H21_DR_REG_LP_WDT_BASE = 1611340800;
246
+ export declare const ESP32H21_RTC_CNTL_WDTWPROTECT_REG: number;
247
+ export declare const ESP32H21_RTC_CNTL_WDTCONFIG0_REG: number;
248
+ export declare const ESP32H21_RTC_CNTL_WDTCONFIG1_REG: number;
249
+ export declare const ESP32H21_RTC_CNTL_WDT_WKEY = 1356348065;
250
+ export declare const ESP32H21_RTC_CNTL_SWD_WKEY = 1356348065;
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  export declare const ESP32P4_SPI_REG_BASE = 1342754816;
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  export declare const ESP32P4_BASEFUSEADDR = 1343410176;
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  export declare const ESP32P4_EFUSE_BLOCK1_ADDR: number;
@@ -186,6 +260,23 @@ export declare const ESP32P4_SPI_MISO_DLEN_OFFS = 40;
186
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  export declare const ESP32P4_SPI_W0_OFFS = 88;
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  export declare const ESP32P4_UART_DATE_REG_ADDR: number;
188
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  export declare const ESP32P4_BOOTLOADER_FLASH_OFFSET = 8192;
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+ export declare const ESP32P4_DR_REG_LP_WDT_BASE = 1343315968;
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+ export declare const ESP32P4_RTC_CNTL_WDTWPROTECT_REG: number;
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+ export declare const ESP32P4_RTC_CNTL_WDTCONFIG0_REG: number;
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+ export declare const ESP32P4_RTC_CNTL_WDTCONFIG1_REG: number;
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+ export declare const ESP32P4_RTC_CNTL_WDT_WKEY = 1356348065;
268
+ export declare const ESP32P4_RTC_CNTL_SWD_CONF_REG: number;
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+ export declare const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN: number;
270
+ export declare const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG: number;
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+ export declare const ESP32P4_RTC_CNTL_SWD_WKEY = 1356348065;
272
+ export declare const ESP32P4_UARTDEV_BUF_NO_REV0 = 1341390536;
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+ export declare const ESP32P4_UARTDEV_BUF_NO_REV300 = 1341914824;
274
+ export declare const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5;
275
+ export declare const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6;
276
+ export declare const ESP32P4_GPIO_STRAP_REG = 1343094840;
277
+ export declare const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 8;
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+ export declare const ESP32P4_RTC_CNTL_OPTION1_REG = 1343291400;
279
+ export declare const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 4;
189
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  export declare const ESP32S31_SPI_REG_BASE = 542113792;
190
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  export declare const ESP32S31_BASEFUSEADDR = 544296960;
191
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  export declare const ESP32S31_EFUSE_BLOCK1_ADDR: number;
package/dist/const.js CHANGED
@@ -63,7 +63,7 @@ export const ESP8266_SPI_MOSI_DLEN_OFFS = -1;
63
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  export const ESP8266_SPI_MISO_DLEN_OFFS = -1;
64
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  export const ESP8266_SPI_W0_OFFS = 0x40;
65
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  export const ESP8266_UART_DATE_REG_ADDR = 0x60000078;
66
- export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0;
66
+ export const ESP8266_BOOTLOADER_FLASH_OFFSET = 0x0000;
67
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  export const ESP32_SPI_REG_BASE = 0x3ff42000;
68
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  export const ESP32_BASEFUSEADDR = 0x3ff5a000;
69
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  export const ESP32_MACFUSEADDR = 0x3ff5a000;
@@ -87,10 +87,19 @@ export const ESP32S2_SPI_W0_OFFS = 0x58;
87
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  export const ESP32S2_UART_DATE_REG_ADDR = 0x60000078;
88
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  export const ESP32S2_BOOTLOADER_FLASH_OFFSET = 0x1000;
89
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  // ESP32-S2 RTC Watchdog Timer registers for USB-OTG reset
90
- export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = 0x3f4080ac;
91
- export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = 0x3f408094;
92
- export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = 0x3f408098;
90
+ export const ESP32S2_RTCCNTL_BASE_REG = 0x3f408000;
91
+ export const ESP32S2_RTC_CNTL_WDTWPROTECT_REG = ESP32S2_RTCCNTL_BASE_REG + 0x00ac;
92
+ export const ESP32S2_RTC_CNTL_WDTCONFIG0_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0094;
93
+ export const ESP32S2_RTC_CNTL_WDTCONFIG1_REG = ESP32S2_RTCCNTL_BASE_REG + 0x0098;
93
94
  export const ESP32S2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
95
+ // ESP32-S2 GPIO strap register and boot mode control
96
+ export const ESP32S2_GPIO_STRAP_REG = 0x3f404038;
97
+ export const ESP32S2_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
98
+ export const ESP32S2_GPIO_STRAP_VDDSPI_MASK = 1 << 4; // SPI voltage (1.8V vs 3.3V)
99
+ export const ESP32S2_RTC_CNTL_OPTION1_REG = 0x3f408128;
100
+ export const ESP32S2_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
101
+ export const ESP32S2_UARTDEV_BUF_NO = 0x3ffffd14; // Variable in ROM .bss which indicates the port in use
102
+ export const ESP32S2_UARTDEV_BUF_NO_USB_OTG = 2; // Value of the above indicating that USB-OTG is in use
94
103
  export const ESP32S3_SPI_REG_BASE = 0x60002000;
95
104
  export const ESP32S3_BASEFUSEADDR = 0x60007000;
96
105
  export const ESP32S3_MACFUSEADDR = 0x60007000 + 0x044;
@@ -101,12 +110,22 @@ export const ESP32S3_SPI_MOSI_DLEN_OFFS = 0x24;
101
110
  export const ESP32S3_SPI_MISO_DLEN_OFFS = 0x28;
102
111
  export const ESP32S3_SPI_W0_OFFS = 0x58;
103
112
  export const ESP32S3_UART_DATE_REG_ADDR = 0x60000080;
104
- export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0;
113
+ export const ESP32S3_BOOTLOADER_FLASH_OFFSET = 0x0000;
105
114
  // ESP32-S3 RTC Watchdog Timer registers for USB-OTG reset
106
- export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = 0x600080b0;
107
- export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = 0x60008098;
108
- export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = 0x6000809c;
115
+ export const ESP32S3_RTCCNTL_BASE_REG = 0x60008000;
116
+ export const ESP32S3_RTC_CNTL_WDTWPROTECT_REG = ESP32S3_RTCCNTL_BASE_REG + 0x00b0;
117
+ export const ESP32S3_RTC_CNTL_WDTCONFIG0_REG = ESP32S3_RTCCNTL_BASE_REG + 0x0098;
118
+ export const ESP32S3_RTC_CNTL_WDTCONFIG1_REG = ESP32S3_RTCCNTL_BASE_REG + 0x009c;
109
119
  export const ESP32S3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
120
+ // ESP32-S3 GPIO strap register and boot mode control
121
+ export const ESP32S3_GPIO_STRAP_REG = 0x60004038;
122
+ export const ESP32S3_GPIO_STRAP_SPI_BOOT_MASK = 1 << 3; // Not download mode
123
+ export const ESP32S3_GPIO_STRAP_VDDSPI_MASK = 1 << 4;
124
+ export const ESP32S3_RTC_CNTL_OPTION1_REG = 0x6000812c;
125
+ export const ESP32S3_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1; // Is download mode forced over USB?
126
+ export const ESP32S3_UARTDEV_BUF_NO = 0x3fcef14c; // Variable in ROM .bss which indicates the port in use
127
+ export const ESP32S3_UARTDEV_BUF_NO_USB_OTG = 3; // The above var when USB-OTG is used
128
+ export const ESP32S3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4; // The above var when USB-JTAG/Serial is used
110
129
  export const ESP32C2_SPI_REG_BASE = 0x60002000;
111
130
  export const ESP32C2_BASEFUSEADDR = 0x60008800;
112
131
  export const ESP32C2_MACFUSEADDR = 0x60008800 + 0x044;
@@ -117,9 +136,16 @@ export const ESP32C2_SPI_MOSI_DLEN_OFFS = 0x24;
117
136
  export const ESP32C2_SPI_MISO_DLEN_OFFS = 0x28;
118
137
  export const ESP32C2_SPI_W0_OFFS = 0x58;
119
138
  export const ESP32C2_UART_DATE_REG_ADDR = 0x6000007c;
120
- export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0;
139
+ export const ESP32C2_BOOTLOADER_FLASH_OFFSET = 0x0000;
140
+ // ESP32-C2 RTC Watchdog Timer registers
141
+ export const ESP32C2_RTCCNTL_BASE_REG = 0x60008000;
142
+ export const ESP32C2_RTC_CNTL_WDTWPROTECT_REG = ESP32C2_RTCCNTL_BASE_REG + 0x009c;
143
+ export const ESP32C2_RTC_CNTL_WDTCONFIG0_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0084;
144
+ export const ESP32C2_RTC_CNTL_WDTCONFIG1_REG = ESP32C2_RTCCNTL_BASE_REG + 0x0088;
145
+ export const ESP32C2_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
121
146
  export const ESP32C3_SPI_REG_BASE = 0x60002000;
122
147
  export const ESP32C3_BASEFUSEADDR = 0x60008800;
148
+ export const ESP32C3_EFUSE_BLOCK1_ADDR = ESP32C3_BASEFUSEADDR + 0x044;
123
149
  export const ESP32C3_MACFUSEADDR = 0x60008800 + 0x044;
124
150
  export const ESP32C3_SPI_USR_OFFS = 0x18;
125
151
  export const ESP32C3_SPI_USR1_OFFS = 0x1c;
@@ -128,7 +154,24 @@ export const ESP32C3_SPI_MOSI_DLEN_OFFS = 0x24;
128
154
  export const ESP32C3_SPI_MISO_DLEN_OFFS = 0x28;
129
155
  export const ESP32C3_SPI_W0_OFFS = 0x58;
130
156
  export const ESP32C3_UART_DATE_REG_ADDR = 0x6000007c;
131
- export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0;
157
+ export const ESP32C3_BOOTLOADER_FLASH_OFFSET = 0x0000;
158
+ // ESP32-C3 RTC Watchdog Timer registers
159
+ export const ESP32C3_RTC_CNTL_BASE_REG = 0x60008000;
160
+ export const ESP32C3_RTC_CNTL_WDTWPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00a8;
161
+ export const ESP32C3_RTC_CNTL_WDTCONFIG0_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0090;
162
+ export const ESP32C3_RTC_CNTL_WDTCONFIG1_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x0094;
163
+ export const ESP32C3_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
164
+ export const ESP32C3_RTC_CNTL_SWD_WKEY = 0x8f1d312a;
165
+ export const ESP32C3_RTC_CNTL_SWD_CONF_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00ac;
166
+ export const ESP32C3_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 31;
167
+ export const ESP32C3_RTC_CNTL_SWD_WPROTECT_REG = ESP32C3_RTC_CNTL_BASE_REG + 0x00b0;
168
+ export const ESP32C3_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
169
+ export const ESP32C3_BUF_UART_NO_OFFSET = 24;
170
+ // Note: ESP32C3_BSS_UART_DEV_ADDR is calculated dynamically based on chip revision in esp_loader.ts
171
+ // Revision < 101: 0x3FCDF064, Revision >= 101: 0x3FCDF060
172
+ // ESP32-C3 EFUSE registers for chip revision detection
173
+ export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_3_REG = 0x60008850;
174
+ export const ESP32C3_EFUSE_RD_MAC_SPI_SYS_5_REG = 0x60008858;
132
175
  export const ESP32C5_SPI_REG_BASE = 0x60003000;
133
176
  export const ESP32C5_BASEFUSEADDR = 0x600b4800;
134
177
  export const ESP32C5_MACFUSEADDR = 0x600b4800 + 0x044;
@@ -140,6 +183,9 @@ export const ESP32C5_SPI_MISO_DLEN_OFFS = 0x28;
140
183
  export const ESP32C5_SPI_W0_OFFS = 0x58;
141
184
  export const ESP32C5_UART_DATE_REG_ADDR = 0x6000007c;
142
185
  export const ESP32C5_BOOTLOADER_FLASH_OFFSET = 0x2000;
186
+ // ESP32-C5 USB-JTAG/Serial detection
187
+ export const ESP32C5_UARTDEV_BUF_NO = 0x4085f514; // Variable in ROM .bss which indicates the port in use
188
+ export const ESP32C5_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
143
189
  export const ESP32C6_SPI_REG_BASE = 0x60003000;
144
190
  export const ESP32C6_BASEFUSEADDR = 0x600b0800;
145
191
  export const ESP32C6_MACFUSEADDR = 0x600b0800 + 0x044;
@@ -150,7 +196,26 @@ export const ESP32C6_SPI_MOSI_DLEN_OFFS = 0x24;
150
196
  export const ESP32C6_SPI_MISO_DLEN_OFFS = 0x28;
151
197
  export const ESP32C6_SPI_W0_OFFS = 0x58;
152
198
  export const ESP32C6_UART_DATE_REG_ADDR = 0x6000007c;
153
- export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0;
199
+ export const ESP32C6_BOOTLOADER_FLASH_OFFSET = 0x0000;
200
+ // ESP32-C6 RTC Watchdog Timer registers (LP_WDT)
201
+ export const ESP32C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
202
+ export const ESP32C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
203
+ export const ESP32C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
204
+ export const ESP32C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
205
+ export const ESP32C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
206
+ export const ESP32C6_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
207
+ // ESP32-C6 USB-JTAG/Serial detection
208
+ export const ESP32C6_UARTDEV_BUF_NO = 0x4087f580; // Variable in ROM .bss which indicates the port in use
209
+ export const ESP32C6_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
210
+ // ESP32-C5/C6 LP Watchdog Timer registers (Low Power WDT)
211
+ export const ESP32C5_C6_DR_REG_LP_WDT_BASE = 0x600b1c00;
212
+ export const ESP32C5_C6_RTC_CNTL_WDTCONFIG0_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
213
+ export const ESP32C5_C6_RTC_CNTL_WDTCONFIG1_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
214
+ export const ESP32C5_C6_RTC_CNTL_WDTWPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
215
+ export const ESP32C5_C6_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY
216
+ export const ESP32C5_C6_RTC_CNTL_SWD_CONF_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_SWD_CONFIG_REG
217
+ export const ESP32C5_C6_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
218
+ export const ESP32C5_C6_RTC_CNTL_SWD_WPROTECT_REG = ESP32C5_C6_DR_REG_LP_WDT_BASE + 0x0020; // LP_WDT_SWD_WPROTECT_REG
154
219
  export const ESP32C61_SPI_REG_BASE = 0x60003000;
155
220
  export const ESP32C61_BASEFUSEADDR = 0x600b4800;
156
221
  export const ESP32C61_MACFUSEADDR = 0x600b4800 + 0x044;
@@ -161,7 +226,7 @@ export const ESP32C61_SPI_MOSI_DLEN_OFFS = 0x24;
161
226
  export const ESP32C61_SPI_MISO_DLEN_OFFS = 0x28;
162
227
  export const ESP32C61_SPI_W0_OFFS = 0x58;
163
228
  export const ESP32C61_UART_DATE_REG_ADDR = 0x6000007c;
164
- export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0;
229
+ export const ESP32C61_BOOTLOADER_FLASH_OFFSET = 0x0000;
165
230
  export const ESP32H2_SPI_REG_BASE = 0x60003000;
166
231
  export const ESP32H2_BASEFUSEADDR = 0x600b0800;
167
232
  export const ESP32H2_MACFUSEADDR = 0x600b0800 + 0x044;
@@ -172,7 +237,17 @@ export const ESP32H2_SPI_MOSI_DLEN_OFFS = 0x24;
172
237
  export const ESP32H2_SPI_MISO_DLEN_OFFS = 0x28;
173
238
  export const ESP32H2_SPI_W0_OFFS = 0x58;
174
239
  export const ESP32H2_UART_DATE_REG_ADDR = 0x6000007c;
175
- export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0;
240
+ export const ESP32H2_BOOTLOADER_FLASH_OFFSET = 0x0000;
241
+ // ESP32-H2 RTC Watchdog Timer registers (LP_WDT)
242
+ export const ESP32H2_DR_REG_LP_WDT_BASE = 0x600b1c00;
243
+ export const ESP32H2_RTC_CNTL_WDTWPROTECT_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x001c; // LP_WDT_RWDT_WPROTECT_REG
244
+ export const ESP32H2_RTC_CNTL_WDTCONFIG0_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
245
+ export const ESP32H2_RTC_CNTL_WDTCONFIG1_REG = ESP32H2_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
246
+ export const ESP32H2_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
247
+ export const ESP32H2_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
248
+ // ESP32-H2 USB-JTAG/Serial detection
249
+ export const ESP32H2_UARTDEV_BUF_NO = 0x4084fefc; // Variable in ROM .bss which indicates the port in use
250
+ export const ESP32H2_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3; // The above var when USB-JTAG/Serial is used
176
251
  export const ESP32H4_SPI_REG_BASE = 0x60099000;
177
252
  export const ESP32H4_BASEFUSEADDR = 0x600b1800;
178
253
  export const ESP32H4_MACFUSEADDR = 0x600b1800 + 0x044;
@@ -184,6 +259,13 @@ export const ESP32H4_SPI_MISO_DLEN_OFFS = 0x28;
184
259
  export const ESP32H4_SPI_W0_OFFS = 0x58;
185
260
  export const ESP32H4_UART_DATE_REG_ADDR = 0x60012000 + 0x7c;
186
261
  export const ESP32H4_BOOTLOADER_FLASH_OFFSET = 0x2000;
262
+ // ESP32-H4 RTC Watchdog Timer registers
263
+ export const ESP32H4_DR_REG_LP_WDT_BASE = 0x600b5400;
264
+ export const ESP32H4_RTC_CNTL_WDTWPROTECT_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_RWDT_WPROTECT_REG
265
+ export const ESP32H4_RTC_CNTL_WDTCONFIG0_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_RWDT_CONFIG0_REG
266
+ export const ESP32H4_RTC_CNTL_WDTCONFIG1_REG = ESP32H4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
267
+ export const ESP32H4_RTC_CNTL_WDT_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
268
+ export const ESP32H4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
187
269
  export const ESP32H21_SPI_REG_BASE = 0x60003000;
188
270
  export const ESP32H21_BASEFUSEADDR = 0x600b4000;
189
271
  export const ESP32H21_MACFUSEADDR = 0x600b4000 + 0x044;
@@ -194,7 +276,14 @@ export const ESP32H21_SPI_MOSI_DLEN_OFFS = 0x24;
194
276
  export const ESP32H21_SPI_MISO_DLEN_OFFS = 0x28;
195
277
  export const ESP32H21_SPI_W0_OFFS = 0x58;
196
278
  export const ESP32H21_UART_DATE_REG_ADDR = 0x6000007c;
197
- export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0;
279
+ export const ESP32H21_BOOTLOADER_FLASH_OFFSET = 0x0000;
280
+ // ESP32-H21 RTC Watchdog Timer registers (LP_WDT)
281
+ export const ESP32H21_DR_REG_LP_WDT_BASE = 0x600b1c00;
282
+ export const ESP32H21_RTC_CNTL_WDTWPROTECT_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x001c;
283
+ export const ESP32H21_RTC_CNTL_WDTCONFIG0_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0000;
284
+ export const ESP32H21_RTC_CNTL_WDTCONFIG1_REG = ESP32H21_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_RWDT_CONFIG1_REG
285
+ export const ESP32H21_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
286
+ export const ESP32H21_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // LP_WDT_SWD_WKEY, same as WDT key in this case
198
287
  export const ESP32P4_SPI_REG_BASE = 0x5008d000;
199
288
  export const ESP32P4_BASEFUSEADDR = 0x5012d000;
200
289
  export const ESP32P4_EFUSE_BLOCK1_ADDR = ESP32P4_BASEFUSEADDR + 0x044;
@@ -207,6 +296,28 @@ export const ESP32P4_SPI_MISO_DLEN_OFFS = 0x28;
207
296
  export const ESP32P4_SPI_W0_OFFS = 0x58;
208
297
  export const ESP32P4_UART_DATE_REG_ADDR = 0x500ca000 + 0x8c;
209
298
  export const ESP32P4_BOOTLOADER_FLASH_OFFSET = 0x2000;
299
+ // ESP32-P4 RTC Watchdog Timer registers
300
+ export const ESP32P4_DR_REG_LP_WDT_BASE = 0x50116000;
301
+ export const ESP32P4_RTC_CNTL_WDTWPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0018; // LP_WDT_WPROTECT_REG
302
+ export const ESP32P4_RTC_CNTL_WDTCONFIG0_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0000; // LP_WDT_CONFIG0_REG
303
+ export const ESP32P4_RTC_CNTL_WDTCONFIG1_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0004; // LP_WDT_CONFIG1_REG
304
+ export const ESP32P4_RTC_CNTL_WDT_WKEY = 0x50d83aa1;
305
+ export const ESP32P4_RTC_CNTL_SWD_CONF_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x001c; // RTC_WDT_SWD_CONFIG_REG
306
+ export const ESP32P4_RTC_CNTL_SWD_AUTO_FEED_EN = 1 << 18;
307
+ export const ESP32P4_RTC_CNTL_SWD_WPROTECT_REG = ESP32P4_DR_REG_LP_WDT_BASE + 0x0020; // RTC_WDT_SWD_WPROTECT_REG
308
+ export const ESP32P4_RTC_CNTL_SWD_WKEY = 0x50d83aa1; // RTC_WDT_SWD_WKEY, same as WDT key in this case
309
+ // ESP32-P4 USB-JTAG/Serial and USB-OTG detection
310
+ // Note: UARTDEV_BUF_NO is dynamic based on chip revision
311
+ // Revision < 300: 0x4FF3FEB0 + 24 = 0x4FF3FEC8
312
+ // Revision >= 300: 0x4FFBFEB0 + 24 = 0x4FFBFEC8
313
+ export const ESP32P4_UARTDEV_BUF_NO_REV0 = 0x4ff3fec8; // Variable in ROM .bss (revision < 300)
314
+ export const ESP32P4_UARTDEV_BUF_NO_REV300 = 0x4ffbfec8; // Variable in ROM .bss (revision >= 300)
315
+ export const ESP32P4_UARTDEV_BUF_NO_USB_OTG = 5; // The above var when USB-OTG is used
316
+ export const ESP32P4_UARTDEV_BUF_NO_USB_JTAG_SERIAL = 6; // The above var when USB-JTAG/Serial is used
317
+ export const ESP32P4_GPIO_STRAP_REG = 0x500e0038;
318
+ export const ESP32P4_GPIO_STRAP_SPI_BOOT_MASK = 0x8; // Not download mode
319
+ export const ESP32P4_RTC_CNTL_OPTION1_REG = 0x50110008;
320
+ export const ESP32P4_RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x4; // Is download mode forced over USB?
210
321
  export const ESP32S31_SPI_REG_BASE = 0x20500000;
211
322
  export const ESP32S31_BASEFUSEADDR = 0x20715000;
212
323
  export const ESP32S31_EFUSE_BLOCK1_ADDR = ESP32S31_BASEFUSEADDR + 0x044;
package/dist/esp_loader.d.ts CHANGED
@@ -24,6 +24,14 @@ export declare class ESPLoader extends EventTarget {
24
24
  private __commandLock;
25
25
  private __isReconfiguring;
26
26
  private __abandonCurrentOperation;
27
+ private _suppressDisconnect;
28
+ private __consoleMode;
29
+ _isUsbJtagOrOtg: boolean | undefined;
30
+ /**
31
+ * Check if device is using USB-JTAG or USB-OTG (not external serial chip)
32
+ * Returns undefined if not yet determined
33
+ */
34
+ get isUsbJtagOrOtg(): boolean | undefined;
27
35
  private __adaptiveBlockMultiplier;
28
36
  private __adaptiveMaxInFlightMultiplier;
29
37
  private __consecutiveSuccessfulChunks;
@@ -38,6 +46,9 @@ export declare class ESPLoader extends EventTarget {
38
46
  set chipRevision(value: number | null);
39
47
  get chipVariant(): string | null;
40
48
  set chipVariant(value: string | null);
49
+ private get _consoleMode();
50
+ private set _consoleMode(value);
51
+ setConsoleMode(value: boolean): void;
41
52
  private get _inputBuffer();
42
53
  private get _inputBufferReadIndex();
43
54
  private set _inputBufferReadIndex(value);
@@ -108,6 +119,16 @@ export declare class ESPLoader extends EventTarget {
108
119
  * Classic reset for Web Serial (Desktop) DTR = IO0, RTS = EN
109
120
  */
110
121
  hardResetClassic(): Promise<void>;
122
+ /**
123
+ * Reset to firmware mode (not bootloader) for Web Serial
124
+ * Keeps IO0=HIGH during reset so chip boots into firmware
125
+ */
126
+ hardResetToFirmware(): Promise<void>;
127
+ /**
128
+ * Reset to firmware mode (not bootloader) for WebUSB
129
+ * Keeps IO0=HIGH during reset so chip boots into firmware
130
+ */
131
+ hardResetToFirmwareWebUSB(): Promise<void>;
111
132
  /**
112
133
  * @name hardResetUnixTight
113
134
  * Unix Tight reset for Web Serial (Desktop) - sets DTR and RTS simultaneously
@@ -174,10 +195,52 @@ export declare class ESPLoader extends EventTarget {
174
195
  connectWithResetStrategies(): Promise<void>;
175
196
  /**
176
197
  * @name watchdogReset
177
- * Watchdog reset for ESP32-S2/S3 with USB-OTG
198
+ * Watchdog reset for ESP32-S2/S3/C3 with USB-OTG or USB-JTAG/Serial
178
199
  * Uses RTC watchdog timer to reset the chip - works when DTR/RTS signals are not available
200
+ * This is an alias for rtcWdtResetChipSpecific() for backwards compatibility
179
201
  */
180
202
  watchdogReset(): Promise<void>;
203
+ /**
204
+ * Check if current chip is using USB-OTG
205
+ * Supports ESP32-S2 and ESP32-S3
206
+ */
207
+ usingUsbOtg(): Promise<boolean>;
208
+ /**
209
+ * Check if current chip is using USB-JTAG/Serial
210
+ * Supports ESP32-S3 and ESP32-C3
211
+ */
212
+ usingUsbJtagSerial(): Promise<boolean>;
213
+ /**
214
+ * Get chip revision for ESP32-C3
215
+ * Reads from EFUSE registers and calculates revision
216
+ */
217
+ getChipRevisionC3(): Promise<number>;
218
+ /**
219
+ * RTC watchdog timer reset for ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, and ESP32-P4
220
+ * Uses specific registers for each chip family
221
+ * Note: ESP32-H2 does NOT support WDT reset
222
+ */
223
+ rtcWdtResetChipSpecific(): Promise<void>;
224
+ /**
225
+ * Helper: Check if USB-based WDT reset should be used for S2/S3
226
+ * Returns true if WDT reset was performed, false otherwise
227
+ */
228
+ private tryUsbWdtReset;
229
+ /**
230
+ * Chip-specific hard reset for ESP32-S2
231
+ * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
232
+ */
233
+ hardResetS2(): Promise<void>;
234
+ /**
235
+ * Chip-specific hard reset for ESP32-S3
236
+ * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
237
+ */
238
+ hardResetS3(): Promise<void>;
239
+ /**
240
+ * Chip-specific hard reset for ESP32-C3
241
+ * Checks if using USB-JTAG/Serial and uses watchdog reset if necessary
242
+ */
243
+ hardResetC3(): Promise<void>;
181
244
  hardReset(bootloader?: boolean): Promise<void>;
182
245
  /**
183
246
  * @name macAddr
@@ -322,6 +385,41 @@ export declare class ESPLoader extends EventTarget {
322
385
  private set _currentBaudRate(value);
323
386
  writeToStream(data: number[]): Promise<void>;
324
387
  disconnect(): Promise<void>;
388
+ /**
389
+ * @name releaseReaderWriter
390
+ * Release reader and writer locks without closing the port
391
+ * Used when switching to console mode
392
+ */
393
+ releaseReaderWriter(): Promise<void>;
394
+ /**
395
+ * @name resetToFirmware
396
+ * Public method to reset device from bootloader to firmware for console mode
397
+ * Automatically detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
398
+ * @returns true if reset was performed, false if not needed
399
+ */
400
+ resetToFirmware(): Promise<boolean>;
401
+ /**
402
+ * @name detectUsbConnectionType
403
+ * Detect if device is using USB-JTAG/Serial or USB-OTG (not external serial chip)
404
+ * This helper extracts the detection logic from initialize() for reuse
405
+ * @returns true if USB-JTAG or USB-OTG, false if external serial chip
406
+ * @throws Error if detection fails and chipFamily is not set
407
+ */
408
+ private detectUsbConnectionType;
409
+ /**
410
+ * @name enterConsoleMode
411
+ * Prepare device for console mode by resetting to firmware
412
+ * Handles both USB-JTAG/OTG devices (closes port) and external serial chips (keeps port open)
413
+ * @returns true if port was closed (USB-JTAG), false if port stays open (serial chip)
414
+ */
415
+ enterConsoleMode(): Promise<boolean>;
416
+ /**
417
+ * @name _resetToFirmwareIfNeeded
418
+ * Reset device from bootloader to firmware when switching to console mode
419
+ * Detects USB-JTAG/Serial and USB-OTG devices and performs appropriate reset
420
+ * @returns true if reconnect was performed, false otherwise
421
+ */
422
+ private _resetToFirmwareIfNeeded;
325
423
  /**
326
424
  * @name reconnectAndResume
327
425
  * Reconnect the serial port to flush browser buffers and reload stub
@@ -356,9 +454,17 @@ export declare class ESPLoader extends EventTarget {
356
454
  * @param addr - Address to read from
357
455
  * @param size - Number of bytes to read
358
456
  * @param onPacketReceived - Optional callback function called when packet is received
457
+ * @param options - Optional parameters for advanced control
458
+ * - chunkSize: Amount of data to request from ESP in one command (bytes)
459
+ * - blockSize: Size of each data block sent by ESP (bytes)
460
+ * - maxInFlight: Maximum unacknowledged bytes (bytes)
359
461
  * @returns Uint8Array containing the flash data
360
462
  */
361
- readFlash(addr: number, size: number, onPacketReceived?: (packet: Uint8Array, progress: number, totalSize: number) => void): Promise<Uint8Array>;
463
+ readFlash(addr: number, size: number, onPacketReceived?: (packet: Uint8Array, progress: number, totalSize: number) => void, options?: {
464
+ chunkSize?: number;
465
+ blockSize?: number;
466
+ maxInFlight?: number;
467
+ }): Promise<Uint8Array>;
362
468
  }
363
469
  declare class EspStubLoader extends ESPLoader {
364
470
  IS_STUB: boolean;