react-native-quick-crypto 1.0.18 → 1.1.0

package/deps/simdutf/src/arm64/arm_find.cpp

@@ -0,0 +1,199 @@
+simdutf_really_inline const char *util_find(const char *start, const char *end,
+                                            char character) noexcept {
+  // Handle empty or invalid range
+  if (start >= end)
+    return end;
+
+  const size_t widestep = 64;
+  const size_t step = 16;
+  uint8x16_t char_vec = vdupq_n_u8(static_cast<uint8_t>(character));
+
+  // Handle unaligned beginning
+  uintptr_t misalignment = reinterpret_cast<uintptr_t>(start) % step;
+  if (misalignment != 0) {
+    size_t adjustment = step - misalignment;
+    if (size_t(end - start) < adjustment) {
+      adjustment = end - start;
+    }
+    for (size_t i = 0; i < adjustment; ++i) {
+      if (start[i] == character) {
+        return start + i;
+      }
+    }
+    start += adjustment;
+  }
+
+  // Main loop for full 64-byte chunks
+  while (size_t(end - start) >= widestep) {
+    uint8x16_t data1 = vld1q_u8(reinterpret_cast<const uint8_t *>(start));
+    uint8x16_t data2 = vld1q_u8(reinterpret_cast<const uint8_t *>(start) + 16);
+    uint8x16_t data3 = vld1q_u8(reinterpret_cast<const uint8_t *>(start) + 32);
+    uint8x16_t data4 = vld1q_u8(reinterpret_cast<const uint8_t *>(start) + 48);
+
+    uint8x16_t cmp1 = vceqq_u8(data1, char_vec);
+    uint8x16_t cmp2 = vceqq_u8(data2, char_vec);
+    uint8x16_t cmp3 = vceqq_u8(data3, char_vec);
+    uint8x16_t cmp4 = vceqq_u8(data4, char_vec);
+    uint8x16_t cmpall = vorrq_u8(vorrq_u8(cmp1, cmp2), vorrq_u8(cmp3, cmp4));
+
+    uint64_t mask = vget_lane_u64(
+        vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmpall), 4)), 0);
+
+    if (mask != 0) {
+      // Found a match, return the first one
+      uint64_t mask1 = vget_lane_u64(
+          vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmp1), 4)), 0);
+      if (mask1 != 0) {
+        // Found a match in the first chunk
+        int index = trailing_zeroes(mask1) / 4; // Each character maps to 4 bits
+        return start + index;
+      }
+      uint64_t mask2 = vget_lane_u64(
+          vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmp2), 4)), 0);
+      if (mask2 != 0) {
+        // Found a match in the second chunk
+        int index = trailing_zeroes(mask2) / 4; // Each character maps to 4 bits
+        return start + index + 16;
+      }
+      uint64_t mask3 = vget_lane_u64(
+          vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmp3), 4)), 0);
+      if (mask3 != 0) {
+        // Found a match in the third chunk
+        int index = trailing_zeroes(mask3) / 4; // Each character maps to 4 bits
+        return start + index + 32;
+      }
+      uint64_t mask4 = vget_lane_u64(
+          vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmp4), 4)), 0);
+      if (mask4 != 0) {
+        // Found a match in the fourth chunk
+        int index = trailing_zeroes(mask4) / 4; // Each character maps to 4 bits
+        return start + index + 48;
+      }
+    }
+
+    start += widestep;
+  }
+
+  // Main loop for full 16-byte chunks
+  while (size_t(end - start) >= step) {
+    uint8x16_t data = vld1q_u8(reinterpret_cast<const uint8_t *>(start));
+    uint8x16_t cmp = vceqq_u8(data, char_vec);
+    uint64_t mask = vget_lane_u64(
+        vreinterpret_u64_u8(vshrn_n_u16(vreinterpretq_u16_u8(cmp), 4)), 0);
+
+    if (mask != 0) {
+      // Found a match, return the first one
+      int index = trailing_zeroes(mask) / 4; // Each character maps to 4 bits
+      return start + index;
+    }
+
+    start += step;
+  }
+
+  // Handle remaining bytes with scalar loop
+  for (; start < end; ++start) {
+    if (*start == character) {
+      return start;
+    }
+  }
+
+  return end;
+}
+
+simdutf_really_inline const char16_t *util_find(const char16_t *start,
+                                                const char16_t *end,
+                                                char16_t character) noexcept {
+  // Handle empty or invalid range
+  if (start >= end)
+    return end;
+
+  const size_t step = 8;
+  uint16x8_t char_vec = vdupq_n_u16(character);
+
+  // Handle unaligned beginning
+  uintptr_t misalignment =
+      reinterpret_cast<uintptr_t>(start) % (step * sizeof(char16_t));
+  if (misalignment != 0 && misalignment % 2 == 0) {
+    size_t adjustment =
+        (step * sizeof(char16_t) - misalignment) / sizeof(char16_t);
+    if (size_t(end - start) < adjustment) {
+      adjustment = end - start;
+    }
+    for (size_t i = 0; i < adjustment; ++i) {
+      if (start[i] == character) {
+        return start + i;
+      }
+    }
+    start += adjustment;
+  }
+
+  // Main loop for full 8-element chunks with unrolling
+  while (size_t(end - start) >= 4 * step) {
+    uint16x8_t data1 = vld1q_u16(reinterpret_cast<const uint16_t *>(start));
+    uint16x8_t data2 =
+        vld1q_u16(reinterpret_cast<const uint16_t *>(start) + step);
+    uint16x8_t data3 =
+        vld1q_u16(reinterpret_cast<const uint16_t *>(start) + 2 * step);
+    uint16x8_t data4 =
+        vld1q_u16(reinterpret_cast<const uint16_t *>(start) + 3 * step);
+
+    uint16x8_t cmp1 = vceqq_u16(data1, char_vec);
+    uint16x8_t cmp2 = vceqq_u16(data2, char_vec);
+    uint16x8_t cmp3 = vceqq_u16(data3, char_vec);
+    uint16x8_t cmp4 = vceqq_u16(data4, char_vec);
+
+    uint64_t mask1 = vget_lane_u64(
+        vreinterpret_u64_u16(vshrn_n_u32(vreinterpretq_u32_u16(cmp1), 4)), 0);
+    if (mask1 != 0) {
+      int index = trailing_zeroes(mask1) / 8;
+      return start + index;
+    }
+
+    uint64_t mask2 = vget_lane_u64(
+        vreinterpret_u64_u16(vshrn_n_u32(vreinterpretq_u32_u16(cmp2), 4)), 0);
+    if (mask2 != 0) {
+      int index = trailing_zeroes(mask2) / 8;
+      return start + index + step;
+    }
+
+    uint64_t mask3 = vget_lane_u64(
+        vreinterpret_u64_u16(vshrn_n_u32(vreinterpretq_u32_u16(cmp3), 4)), 0);
+    if (mask3 != 0) {
+      int index = trailing_zeroes(mask3) / 8;
+      return start + index + 2 * step;
+    }
+
+    uint64_t mask4 = vget_lane_u64(
+        vreinterpret_u64_u16(vshrn_n_u32(vreinterpretq_u32_u16(cmp4), 4)), 0);
+    if (mask4 != 0) {
+      int index = trailing_zeroes(mask4) / 8;
+      return start + index + 3 * step;
+    }
+
+    start += 4 * step;
+  }
+
+  // Main loop for full 8-element chunks
+  while (size_t(end - start) >= step) {
+    uint16x8_t data = vld1q_u16(reinterpret_cast<const uint16_t *>(start));
+    uint16x8_t cmp = vceqq_u16(data, char_vec);
+    uint64_t mask = vget_lane_u64(
+        vreinterpret_u64_u16(vshrn_n_u32(vreinterpretq_u32_u16(cmp), 4)), 0);
+
+    if (mask != 0) {
+      int index = trailing_zeroes(mask) / 8;
+      return start + index;
+    }
+
+    start += step;
+  }
+
+  // Handle remaining elements with scalar loop
+  for (; start < end; ++start) {
+    if (*start == character) {
+      return start;
+    }
+  }
+
+  return end;
+}

package/deps/simdutf/src/arm64/arm_utf16fix.cpp

@@ -0,0 +1,185 @@
+
+/*
+ * Returns if a vector of type uint8x16_t is all zero.
+ */
+simdutf_really_inline int veq_non_zero(uint8x16_t v) {
+  // might compile to two instructions:
+  //	umaxv   s0, v0.4s
+  //	fmov	w0, s0
+  // On Apple hardware, they both have a latency of 3 cycles, with a throughput
+  // of four instructions per cycle. So that's 6 cycles of latency (!!!) for the
+  // two instructions. A narrowing shift has the same latency and throughput.
+  return vmaxvq_u32(vreinterpretq_u32_u8(v));
+}
+
+/*
+ * Process one block of 16 characters.  If in_place is false,
+ * copy the block from in to out.  If there is a sequencing
+ * error in the block, overwrite the illsequenced characters
+ * with the replacement character.  This function reads one
+ * character before the beginning of the buffer as a lookback.
+ * If that character is illsequenced, it too is overwritten.
+ */
+template <endianness big_endian, bool inplace>
+void utf16fix_block(char16_t *out, const char16_t *in) {
+  const char16_t replacement = scalar::utf16::replacement<big_endian>();
+  uint8x16x2_t lb, block;
+  uint8x16_t lb_masked, block_masked, lb_is_high, block_is_low;
+  uint8x16_t illseq;
+
+  constexpr int idx = !match_system(big_endian) ? 0 : 1;
+
+  /* TODO: compute lookback using shifts */
+  lb = vld2q_u8((const uint8_t *)(in - 1));
+  block = vld2q_u8((const uint8_t *)in);
+  lb_masked = vandq_u8(lb.val[idx], vdupq_n_u8(0xfc));
+  block_masked = vandq_u8(block.val[idx], vdupq_n_u8(0xfc));
+  lb_is_high = vceqq_u8(lb_masked, vdupq_n_u8(0xd8));
+  block_is_low = vceqq_u8(block_masked, vdupq_n_u8(0xdc));
+
+  illseq = veorq_u8(lb_is_high, block_is_low);
+  if (veq_non_zero(illseq)) {
+    uint8x16_t lb_illseq, block_illseq;
+    char16_t lbc;
+    int ill;
+
+    /* compute the cause of the illegal sequencing */
+    lb_illseq = vbicq_u8(lb_is_high, block_is_low);
+    block_illseq = vorrq_u8(vbicq_u8(block_is_low, lb_is_high),
+                            vextq_u8(lb_illseq, vdupq_n_u8(0), 1));
+
+    /* fix illegal sequencing in the lookback */
+    ill = vgetq_lane_u8(lb_illseq, 0);
+    lbc = out[-1];
+    out[-1] = ill ? replacement : lbc;
+
+    /* fix illegal sequencing in the main block */
+    if simdutf_constexpr (!match_system(big_endian)) {
+      block.val[1] = vbslq_u8(block_illseq, vdupq_n_u8(0xfd), block.val[1]);
+      block.val[0] = vorrq_u8(block_illseq, block.val[0]);
+    } else {
+      block.val[0] = vbslq_u8(block_illseq, vdupq_n_u8(0xfd), block.val[0]);
+      block.val[1] = vorrq_u8(block_illseq, block.val[1]);
+    }
+
+    vst2q_u8((uint8_t *)out, block);
+  } else if (!inplace) {
+    vst2q_u8((uint8_t *)out, block);
+  }
+}
+
+template <endianness big_endian, bool inplace>
+uint8x16_t get_mismatch_copy(const char16_t *in, char16_t *out) {
+  constexpr int idx = !match_system(big_endian) ? 0 : 1;
+  uint8x16x2_t lb = vld2q_u8((const uint8_t *)(in - 1));
+  uint8x16x2_t block = vld2q_u8((const uint8_t *)in);
+  uint8x16_t lb_masked = vandq_u8(lb.val[idx], vdupq_n_u8(0xfc));
+  uint8x16_t block_masked = vandq_u8(block.val[idx], vdupq_n_u8(0xfc));
+  uint8x16_t lb_is_high = vceqq_u8(lb_masked, vdupq_n_u8(0xd8));
+  uint8x16_t block_is_low = vceqq_u8(block_masked, vdupq_n_u8(0xdc));
+  uint8x16_t illseq = veorq_u8(lb_is_high, block_is_low);
+  if (!inplace) {
+    vst2q_u8((uint8_t *)out, block);
+  }
+  return illseq;
+}
+
+simdutf_really_inline uint64_t get_mask(uint8x16_t illse0, uint8x16_t illse1,
+                                        uint8x16_t illse2, uint8x16_t illse3) {
+#ifdef SIMDUTF_REGULAR_VISUAL_STUDIO
+  uint8x16_t bit_mask =
+      simdutf_make_uint8x16_t(0x01, 0x02, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80,
+                              0x01, 0x02, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80);
+#else
+  uint8x16_t bit_mask = {0x01, 0x02, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80,
+                         0x01, 0x02, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80};
+#endif
+  uint8x16_t sum0 =
+      vpaddq_u8(vandq_u8(illse0, bit_mask), vandq_u8(illse1, bit_mask));
+  uint8x16_t sum1 =
+      vpaddq_u8(vandq_u8(illse2, bit_mask), vandq_u8(illse3, bit_mask));
+  sum0 = vpaddq_u8(sum0, sum1);
+  sum0 = vpaddq_u8(sum0, sum0);
+  return vgetq_lane_u64(vreinterpretq_u64_u8(sum0), 0);
+}
+
+// The idea is to process 64 characters at a time, and if there is a mismatch
+// we can fix it with a bit of scalar code. When the input is correct, this
+// function might be faster than alternative implementations working on small
+// blocks of input.
+template <endianness big_endian, bool inplace>
+bool utf16fix_block64(char16_t *out, const char16_t *in) {
+  const char16_t replacement = scalar::utf16::replacement<big_endian>();
+
+  uint8x16_t illse0 = inplace ? get_mismatch_copy<big_endian, true>(in, out)
+                              : get_mismatch_copy<big_endian, false>(in, out);
+  uint8x16_t illse1 =
+      inplace ? get_mismatch_copy<big_endian, true>(in + 16, out + 16)
+              : get_mismatch_copy<big_endian, false>(in + 16, out + 16);
+  uint8x16_t illse2 =
+      inplace ? get_mismatch_copy<big_endian, true>(in + 32, out + 32)
+              : get_mismatch_copy<big_endian, false>(in + 32, out + 32);
+  uint8x16_t illse3 =
+      inplace ? get_mismatch_copy<big_endian, true>(in + 48, out + 48)
+              : get_mismatch_copy<big_endian, false>(in + 48, out + 48);
+  // this branch could be marked as unlikely:
+  if (veq_non_zero(
+          vorrq_u8(vorrq_u8(illse0, illse1), vorrq_u8(illse2, illse3)))) {
+    uint64_t matches = get_mask(illse0, illse1, illse2, illse3);
+    // Given that ARM has a fast bitreverse instruction, we can
+    // reverse once and then use clz to find the first bit set.
+    // It is how it is done in simdjson and *might* be beneficial.
+    //
+    // We might also proceed in reverse to reduce the RAW hazard,
+    // but it might require more instructions.
+
+    while (matches != 0) {
+      int r = trailing_zeroes(matches); // generates rbit + clz
+      // Either we have a high surrogate followed by a non-low surrogate
+      // or we have a low surrogate not preceded by a high surrogate.
+      bool is_high = scalar::utf16::is_high_surrogate<big_endian>(in[r - 1]);
+      out[r - is_high] = replacement;
+      matches = clear_least_significant_bit(matches);
+    }
+    return false;
+  }
+  return true;
+}
+
+template <endianness big_endian>
+void utf16fix_neon_64bits(const char16_t *in, size_t n, char16_t *out) {
+  size_t i;
+  const char16_t replacement = scalar::utf16::replacement<big_endian>();
+  if (n < 17) {
+    return scalar::utf16::to_well_formed_utf16<big_endian>(in, n, out);
+  }
+  out[0] =
+      scalar::utf16::is_low_surrogate<big_endian>(in[0]) ? replacement : in[0];
+  i = 1;
+
+  /* duplicate code to have the compiler specialise utf16fix_block() */
+  if (in == out) {
+    for (i = 1; i + 64 < n; i += 64) {
+      utf16fix_block64<big_endian, true>(out + i, in + i);
+    }
+
+    for (; i + 16 < n; i += 16) {
+      utf16fix_block<big_endian, true>(out + i, in + i);
+    }
+
+    /* tbd: find carry */
+    utf16fix_block<big_endian, true>(out + n - 16, in + n - 16);
+  } else {
+    for (i = 1; i + 64 < n; i += 64) {
+      utf16fix_block64<big_endian, false>(out + i, in + i);
+    }
+    for (; i + 16 < n; i += 16) {
+      utf16fix_block<big_endian, false>(out + i, in + i);
+    }
+
+    utf16fix_block<big_endian, false>(out + n - 16, in + n - 16);
+  }
+  out[n - 1] = scalar::utf16::is_high_surrogate<big_endian>(out[n - 1])
+                   ? replacement
+                   : out[n - 1];
+}

package/deps/simdutf/src/arm64/arm_validate_utf16.cpp

@@ -0,0 +1,165 @@
+template <endianness big_endian>
+const char16_t *arm_validate_utf16(const char16_t *input, size_t size) {
+  const char16_t *end = input + size;
+  const auto v_d8 = simd8<uint8_t>::splat(0xd8);
+  const auto v_f8 = simd8<uint8_t>::splat(0xf8);
+  const auto v_fc = simd8<uint8_t>::splat(0xfc);
+  const auto v_dc = simd8<uint8_t>::splat(0xdc);
+  while (end - input >= 16) {
+    // 0. Load data: since the validation takes into account only higher
+    //    byte of each word, we compress the two vectors into one which
+    //    consists only the higher bytes.
+    auto in0 = simd16<uint16_t>(input);
+    auto in1 =
+        simd16<uint16_t>(input + simd16<uint16_t>::SIZE / sizeof(char16_t));
+    if simdutf_constexpr (!match_system(big_endian)) {
+      in0 = vreinterpretq_u16_u8(vrev16q_u8(vreinterpretq_u8_u16(in0)));
+      in1 = vreinterpretq_u16_u8(vrev16q_u8(vreinterpretq_u8_u16(in1)));
+    }
+    const auto t0 = in0.shr<8>();
+    const auto t1 = in1.shr<8>();
+    const simd8<uint8_t> in = simd16<uint16_t>::pack(t0, t1);
+    // 1. Check whether we have any 0xD800..DFFF word (0b1101'1xxx'yyyy'yyyy).
+    const uint64_t surrogates_wordmask = ((in & v_f8) == v_d8).to_bitmask64();
+    if (surrogates_wordmask == 0) {
+      input += 16;
+    } else {
+      // 2. We have some surrogates that have to be distinguished:
+      //    - low  surrogates: 0b1101'10xx'yyyy'yyyy (0xD800..0xDBFF)
+      //    - high surrogates: 0b1101'11xx'yyyy'yyyy (0xDC00..0xDFFF)
+      //
+      //    Fact: high surrogate has 11th bit set (3rd bit in the higher word)
+
+      // V - non-surrogate code units
+      //     V = not surrogates_wordmask
+      const uint64_t V = ~surrogates_wordmask;
+
+      // H - word-mask for high surrogates: the six highest bits are 0b1101'11
+      const auto vH = ((in & v_fc) == v_dc);
+      const uint64_t H = vH.to_bitmask64();
+
+      // L - word mask for low surrogates
+      //     L = not H and surrogates_wordmask
+      const uint64_t L = ~H & surrogates_wordmask;
+
+      const uint64_t a =
+          L & (H >> 4); // A low surrogate must be followed by high one.
+                        // (A low surrogate placed in the 7th register's word
+                        // is an exception we handle.)
+      const uint64_t b =
+          a << 4; // Just mark that the opposite fact is hold,
+                  // thanks to that we have only two masks for valid case.
+      const uint64_t c = V | a | b; // Combine all the masks into the final one.
+      if (c == ~0ull) {
+        // The whole input register contains valid UTF-16, i.e.,
+        // either single code units or proper surrogate pairs.
+        input += 16;
+      } else if (c == 0xfffffffffffffffull) {
+        // The 15 lower code units of the input register contains valid UTF-16.
+        // The 15th word may be either a low or high surrogate. It the next
+        // iteration we 1) check if the low surrogate is followed by a high
+        // one, 2) reject sole high surrogate.
+        input += 15;
+      } else {
+        return nullptr;
+      }
+    }
+  }
+  return input;
+}
+
+template <endianness big_endian>
+const char16_t *arm_validate_utf16_as_ascii(const char16_t *input,
+                                            size_t size) {
+  const char16_t *end = input + size;
+  while (end - input >= 16) {
+    uint16x8_t in1 = vld1q_u16(reinterpret_cast<const uint16_t *>(input));
+    uint16x8_t in2 = vld1q_u16(reinterpret_cast<const uint16_t *>(input + 8));
+    uint16x8_t inor = vorrq_u16(in1, in2);
+    if simdutf_constexpr (!match_system(big_endian)) {
+      inor = vreinterpretq_u16_u8(vrev16q_u8(vreinterpretq_u8_u16(inor)));
+    }
+    // next we compute inor > 0x7f
+    uint16x8_t cmp = vcgtq_u16(inor, vdupq_n_u16(0x7f));
+    uint64_t mask = vget_lane_u64(vreinterpret_u64_u8(vshrn_n_u16(cmp, 4)), 0);
+    if (mask) {
+      return nullptr;
+    }
+    input += 16;
+  }
+  return input;
+}
+
+template <endianness big_endian>
+const result arm_validate_utf16_with_errors(const char16_t *input,
+                                            size_t size) {
+  const char16_t *start = input;
+  const char16_t *end = input + size;
+
+  const auto v_d8 = simd8<uint8_t>::splat(0xd8);
+  const auto v_f8 = simd8<uint8_t>::splat(0xf8);
+  const auto v_fc = simd8<uint8_t>::splat(0xfc);
+  const auto v_dc = simd8<uint8_t>::splat(0xdc);
+  while (input + 16 < end) {
+    // 0. Load data: since the validation takes into account only higher
+    //    byte of each word, we compress the two vectors into one which
+    //    consists only the higher bytes.
+    auto in0 = simd16<uint16_t>(input);
+    auto in1 =
+        simd16<uint16_t>(input + simd16<uint16_t>::SIZE / sizeof(char16_t));
+
+    if simdutf_constexpr (!match_system(big_endian)) {
+      in0 = vreinterpretq_u16_u8(vrev16q_u8(vreinterpretq_u8_u16(in0)));
+      in1 = vreinterpretq_u16_u8(vrev16q_u8(vreinterpretq_u8_u16(in1)));
+    }
+    const auto t0 = in0.shr<8>();
+    const auto t1 = in1.shr<8>();
+    const simd8<uint8_t> in = simd16<uint16_t>::pack(t0, t1);
+    // 1. Check whether we have any 0xD800..DFFF word (0b1101'1xxx'yyyy'yyyy).
+    const uint64_t surrogates_wordmask = ((in & v_f8) == v_d8).to_bitmask64();
+    if (surrogates_wordmask == 0) {
+      input += 16;
+    } else {
+      // 2. We have some surrogates that have to be distinguished:
+      //    - low  surrogates: 0b1101'10xx'yyyy'yyyy (0xD800..0xDBFF)
+      //    - high surrogates: 0b1101'11xx'yyyy'yyyy (0xDC00..0xDFFF)
+      //
+      //    Fact: high surrogate has 11th bit set (3rd bit in the higher word)
+
+      // V - non-surrogate code units
+      //     V = not surrogates_wordmask
+      const uint64_t V = ~surrogates_wordmask;
+
+      // H - word-mask for high surrogates: the six highest bits are 0b1101'11
+      const auto vH = ((in & v_fc) == v_dc);
+      const uint64_t H = vH.to_bitmask64();
+
+      // L - word mask for low surrogates
+      //     L = not H and surrogates_wordmask
+      const uint64_t L = ~H & surrogates_wordmask;
+
+      const uint64_t a =
+          L & (H >> 4); // A low surrogate must be followed by high one.
+                        // (A low surrogate placed in the 7th register's word
+                        // is an exception we handle.)
+      const uint64_t b =
+          a << 4; // Just mark that the opposite fact is hold,
+                  // thanks to that we have only two masks for valid case.
+      const uint64_t c = V | a | b; // Combine all the masks into the final one.
+      if (c == ~0ull) {
+        // The whole input register contains valid UTF-16, i.e.,
+        // either single code units or proper surrogate pairs.
+        input += 16;
+      } else if (c == 0xfffffffffffffffull) {
+        // The 15 lower code units of the input register contains valid UTF-16.
+        // The 15th word may be either a low or high surrogate. It the next
+        // iteration we 1) check if the low surrogate is followed by a high
+        // one, 2) reject sole high surrogate.
+        input += 15;
+      } else {
+        return result(error_code::SURROGATE, input - start);
+      }
+    }
+  }
+  return result(error_code::SUCCESS, input - start);
+}

package/deps/simdutf/src/arm64/arm_validate_utf32le.cpp

@@ -0,0 +1,65 @@
+
+const char32_t *arm_validate_utf32le(const char32_t *input, size_t size) {
+  const char32_t *end = input + size;
+
+  const uint32x4_t standardmax = vmovq_n_u32(0x10ffff);
+  const uint32x4_t offset = vmovq_n_u32(0xffff2000);
+  const uint32x4_t standardoffsetmax = vmovq_n_u32(0xfffff7ff);
+  uint32x4_t currentmax = vmovq_n_u32(0x0);
+  uint32x4_t currentoffsetmax = vmovq_n_u32(0x0);
+
+  while (end - input >= 4) {
+    const uint32x4_t in = vld1q_u32(reinterpret_cast<const uint32_t *>(input));
+    currentmax = vmaxq_u32(in, currentmax);
+    currentoffsetmax = vmaxq_u32(vaddq_u32(in, offset), currentoffsetmax);
+    input += 4;
+  }
+
+  uint32x4_t is_zero =
+      veorq_u32(vmaxq_u32(currentmax, standardmax), standardmax);
+  if (vmaxvq_u32(is_zero) != 0) {
+    return nullptr;
+  }
+
+  is_zero = veorq_u32(vmaxq_u32(currentoffsetmax, standardoffsetmax),
+                      standardoffsetmax);
+  if (vmaxvq_u32(is_zero) != 0) {
+    return nullptr;
+  }
+
+  return input;
+}
+
+const result arm_validate_utf32le_with_errors(const char32_t *input,
+                                              size_t size) {
+  const char32_t *start = input;
+  const char32_t *end = input + size;
+
+  const uint32x4_t standardmax = vmovq_n_u32(0x10ffff);
+  const uint32x4_t offset = vmovq_n_u32(0xffff2000);
+  const uint32x4_t standardoffsetmax = vmovq_n_u32(0xfffff7ff);
+  uint32x4_t currentmax = vmovq_n_u32(0x0);
+  uint32x4_t currentoffsetmax = vmovq_n_u32(0x0);
+
+  while (end - input >= 4) {
+    const uint32x4_t in = vld1q_u32(reinterpret_cast<const uint32_t *>(input));
+    currentmax = vmaxq_u32(in, currentmax);
+    currentoffsetmax = vmaxq_u32(vaddq_u32(in, offset), currentoffsetmax);
+
+    uint32x4_t is_zero =
+        veorq_u32(vmaxq_u32(currentmax, standardmax), standardmax);
+    if (vmaxvq_u32(is_zero) != 0) {
+      return result(error_code::TOO_LARGE, input - start);
+    }
+
+    is_zero = veorq_u32(vmaxq_u32(currentoffsetmax, standardoffsetmax),
+                        standardoffsetmax);
+    if (vmaxvq_u32(is_zero) != 0) {
+      return result(error_code::SURROGATE, input - start);
+    }
+
+    input += 4;
+  }
+
+  return result(error_code::SUCCESS, input - start);
+}