react-native-quick-crypto 1.0.18 → 1.1.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (751) hide show
  1. package/QuickCrypto.podspec +12 -38
  2. package/README.md +2 -0
  3. package/android/CMakeLists.txt +3 -0
  4. package/cpp/utils/HybridUtils.cpp +39 -77
  5. package/deps/simdutf/.clang-format +4 -0
  6. package/deps/simdutf/.github/ISSUE_TEMPLATE/bug_report.md +62 -0
  7. package/deps/simdutf/.github/ISSUE_TEMPLATE/config.yml +1 -0
  8. package/deps/simdutf/.github/ISSUE_TEMPLATE/feature_request.md +35 -0
  9. package/deps/simdutf/.github/ISSUE_TEMPLATE/standard-issue-template.md +29 -0
  10. package/deps/simdutf/.github/pull_request_template.md +51 -0
  11. package/deps/simdutf/.github/workflows/aarch64.yml +39 -0
  12. package/deps/simdutf/.github/workflows/alpine.yml +27 -0
  13. package/deps/simdutf/.github/workflows/amalgamation_demos.yml +34 -0
  14. package/deps/simdutf/.github/workflows/armv7.yml +32 -0
  15. package/deps/simdutf/.github/workflows/atomic_fuzz.yml +25 -0
  16. package/deps/simdutf/.github/workflows/cifuzz.yml +37 -0
  17. package/deps/simdutf/.github/workflows/clangformat.yml +36 -0
  18. package/deps/simdutf/.github/workflows/debian-latestcxxstandards.yml +40 -0
  19. package/deps/simdutf/.github/workflows/debian.yml +33 -0
  20. package/deps/simdutf/.github/workflows/documentation.yml +36 -0
  21. package/deps/simdutf/.github/workflows/emscripten.yml +19 -0
  22. package/deps/simdutf/.github/workflows/loongarch64-gcc-14.2.yml +39 -0
  23. package/deps/simdutf/.github/workflows/macos-latest.yml +29 -0
  24. package/deps/simdutf/.github/workflows/msys2-clang.yml +48 -0
  25. package/deps/simdutf/.github/workflows/msys2.yml +50 -0
  26. package/deps/simdutf/.github/workflows/ppc64le.yml +29 -0
  27. package/deps/simdutf/.github/workflows/rvv-1024-clang-18.yml +35 -0
  28. package/deps/simdutf/.github/workflows/rvv-128-clang-17.yml +35 -0
  29. package/deps/simdutf/.github/workflows/rvv-256-gcc-14.yml +31 -0
  30. package/deps/simdutf/.github/workflows/s390x.yml +29 -0
  31. package/deps/simdutf/.github/workflows/selective-amalgamation.yml +29 -0
  32. package/deps/simdutf/.github/workflows/typos.yml +19 -0
  33. package/deps/simdutf/.github/workflows/ubuntu22-cxx20.yml +30 -0
  34. package/deps/simdutf/.github/workflows/ubuntu22.yml +32 -0
  35. package/deps/simdutf/.github/workflows/ubuntu22_gcc12.yml +27 -0
  36. package/deps/simdutf/.github/workflows/ubuntu22sani.yml +29 -0
  37. package/deps/simdutf/.github/workflows/ubuntu24-cxxstandards.yml +34 -0
  38. package/deps/simdutf/.github/workflows/ubuntu24-unsignedchar.yml +34 -0
  39. package/deps/simdutf/.github/workflows/ubuntu24.yml +32 -0
  40. package/deps/simdutf/.github/workflows/ubuntu24sani.yml +36 -0
  41. package/deps/simdutf/.github/workflows/ubuntu24sani_clang.yml +29 -0
  42. package/deps/simdutf/.github/workflows/vs17-arm-ci.yml +21 -0
  43. package/deps/simdutf/.github/workflows/vs17-ci-cxx20.yml +41 -0
  44. package/deps/simdutf/.github/workflows/vs17-ci.yml +41 -0
  45. package/deps/simdutf/.github/workflows/vs17-clang-ci.yml +41 -0
  46. package/deps/simdutf/.github/workflows/vs17-cxxstandards.yml +36 -0
  47. package/deps/simdutf/AI_USAGE_POLICY.md +56 -0
  48. package/deps/simdutf/AUTHORS +6 -0
  49. package/deps/simdutf/CMakeLists.txt +231 -0
  50. package/deps/simdutf/CONTRIBUTING.md +214 -0
  51. package/deps/simdutf/CONTRIBUTORS +1 -0
  52. package/deps/simdutf/Doxyfile +2584 -0
  53. package/deps/simdutf/LICENSE-APACHE +201 -0
  54. package/deps/simdutf/LICENSE-MIT +18 -0
  55. package/deps/simdutf/Makefile.crosscompile +54 -0
  56. package/deps/simdutf/README-RVV.md +16 -0
  57. package/deps/simdutf/README.md +2782 -0
  58. package/deps/simdutf/SECURITY.md +8 -0
  59. package/deps/simdutf/benchmarks/CMakeLists.txt +101 -0
  60. package/deps/simdutf/benchmarks/alignment.cpp +150 -0
  61. package/deps/simdutf/benchmarks/base64/CMakeLists.txt +30 -0
  62. package/deps/simdutf/benchmarks/base64/benchmark_base64.cpp +875 -0
  63. package/deps/simdutf/benchmarks/base64/libbase64_spaces.h +49 -0
  64. package/deps/simdutf/benchmarks/base64/node_base64.h +227 -0
  65. package/deps/simdutf/benchmarks/base64/openssl3_base64.h +334 -0
  66. package/deps/simdutf/benchmarks/benchmark.cpp +65 -0
  67. package/deps/simdutf/benchmarks/benchmark_to_well_formed_utf16.cpp +347 -0
  68. package/deps/simdutf/benchmarks/competition/.clang-format-ignore +5 -0
  69. package/deps/simdutf/benchmarks/competition/CppCon2018/utf_utils.cpp +1276 -0
  70. package/deps/simdutf/benchmarks/competition/CppCon2018/utf_utils.h +595 -0
  71. package/deps/simdutf/benchmarks/competition/README.md +7 -0
  72. package/deps/simdutf/benchmarks/competition/hoehrmann/hoehrmann.h +91 -0
  73. package/deps/simdutf/benchmarks/competition/inoue2008/inoue_utf8_to_utf16.h +444 -0
  74. package/deps/simdutf/benchmarks/competition/inoue2008/inoue_utf8_to_utf16_tables.h +13183 -0
  75. package/deps/simdutf/benchmarks/competition/inoue2008/script.py +73 -0
  76. package/deps/simdutf/benchmarks/competition/llvm/ConvertUTF.cpp +738 -0
  77. package/deps/simdutf/benchmarks/competition/llvm/ConvertUTF.h +293 -0
  78. package/deps/simdutf/benchmarks/competition/u8u16/COPYRIGHT +8 -0
  79. package/deps/simdutf/benchmarks/competition/u8u16/Makefile +44 -0
  80. package/deps/simdutf/benchmarks/competition/u8u16/OSL3.0.txt +169 -0
  81. package/deps/simdutf/benchmarks/competition/u8u16/Profiling/BOM_Profiler.h +148 -0
  82. package/deps/simdutf/benchmarks/competition/u8u16/Profiling/i386_timer.h +45 -0
  83. package/deps/simdutf/benchmarks/competition/u8u16/Profiling/ppc_timer.c +34 -0
  84. package/deps/simdutf/benchmarks/competition/u8u16/README +56 -0
  85. package/deps/simdutf/benchmarks/competition/u8u16/config/config_defs.h +43 -0
  86. package/deps/simdutf/benchmarks/competition/u8u16/config/g4_config.h +27 -0
  87. package/deps/simdutf/benchmarks/competition/u8u16/config/mmx_config.h +16 -0
  88. package/deps/simdutf/benchmarks/competition/u8u16/config/p4_config.h +18 -0
  89. package/deps/simdutf/benchmarks/competition/u8u16/config/p4_ideal_config.h +16 -0
  90. package/deps/simdutf/benchmarks/competition/u8u16/config/spu_config.h +28 -0
  91. package/deps/simdutf/benchmarks/competition/u8u16/config/ssse3_config.h +20 -0
  92. package/deps/simdutf/benchmarks/competition/u8u16/iconv_u8u16.c +2 -0
  93. package/deps/simdutf/benchmarks/competition/u8u16/lib/altivec_simd.h +440 -0
  94. package/deps/simdutf/benchmarks/competition/u8u16/lib/libgen/make_basic_ops.py +121 -0
  95. package/deps/simdutf/benchmarks/competition/u8u16/lib/libgen/make_half_operand_versions.py +158 -0
  96. package/deps/simdutf/benchmarks/competition/u8u16/lib/libgen/make_test.py +270 -0
  97. package/deps/simdutf/benchmarks/competition/u8u16/lib/mmx_simd.h +141 -0
  98. package/deps/simdutf/benchmarks/competition/u8u16/lib/mmx_simd_basic.h +216 -0
  99. package/deps/simdutf/benchmarks/competition/u8u16/lib/mmx_simd_built_in.h +119 -0
  100. package/deps/simdutf/benchmarks/competition/u8u16/lib/mmx_simd_modified.h +2430 -0
  101. package/deps/simdutf/benchmarks/competition/u8u16/lib/outline.txt +39 -0
  102. package/deps/simdutf/benchmarks/competition/u8u16/lib/spu_simd.h +421 -0
  103. package/deps/simdutf/benchmarks/competition/u8u16/lib/sse_simd.h +836 -0
  104. package/deps/simdutf/benchmarks/competition/u8u16/lib/stdint.h +222 -0
  105. package/deps/simdutf/benchmarks/competition/u8u16/libu8u16_BE.c +4 -0
  106. package/deps/simdutf/benchmarks/competition/u8u16/libu8u16_LE.c +5 -0
  107. package/deps/simdutf/benchmarks/competition/u8u16/proto/u8u16.py +390 -0
  108. package/deps/simdutf/benchmarks/competition/u8u16/src/Makefile +18 -0
  109. package/deps/simdutf/benchmarks/competition/u8u16/src/bytelex.h +448 -0
  110. package/deps/simdutf/benchmarks/competition/u8u16/src/charsets/ASCII_EBCDIC.h +284 -0
  111. package/deps/simdutf/benchmarks/competition/u8u16/src/libu8u16.c +1975 -0
  112. package/deps/simdutf/benchmarks/competition/u8u16/src/libu8u16.pdf +0 -0
  113. package/deps/simdutf/benchmarks/competition/u8u16/src/libu8u16.w +2263 -0
  114. package/deps/simdutf/benchmarks/competition/u8u16/src/multiliteral.h +239 -0
  115. package/deps/simdutf/benchmarks/competition/u8u16/src/u8u16.c +232 -0
  116. package/deps/simdutf/benchmarks/competition/u8u16/src/x8x16.c +194 -0
  117. package/deps/simdutf/benchmarks/competition/u8u16/src/xml_error.c +193 -0
  118. package/deps/simdutf/benchmarks/competition/u8u16/src/xml_error.h +167 -0
  119. package/deps/simdutf/benchmarks/competition/u8u16/src/xmldecl.c +288 -0
  120. package/deps/simdutf/benchmarks/competition/u8u16/src/xmldecl.h +117 -0
  121. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_g4.c +2 -0
  122. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_mmx.c +2 -0
  123. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_p4.c +3 -0
  124. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_p4_ideal.c +2 -0
  125. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_spu.c +2 -0
  126. package/deps/simdutf/benchmarks/competition/u8u16/u8u16_ssse3.c +3 -0
  127. package/deps/simdutf/benchmarks/competition/u8u16/x8x16_p4.c +2 -0
  128. package/deps/simdutf/benchmarks/competition/utf8lut/LICENSE +23 -0
  129. package/deps/simdutf/benchmarks/competition/utf8lut/data/test_minimal.txt +44 -0
  130. package/deps/simdutf/benchmarks/competition/utf8lut/readme.md +106 -0
  131. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_clang_corr_tests.cmd +11 -0
  132. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_clang_corr_tests.sh +13 -0
  133. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_gcc_corr_tests.sh +13 -0
  134. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_gcc_example.sh +13 -0
  135. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_gcc_file_conv.sh +14 -0
  136. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_gcc_iconv_lib.sh +11 -0
  137. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_gcc_iconv_sample.sh +8 -0
  138. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_mingw_corr_tests.cmd +12 -0
  139. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_mingw_example.cmd +13 -0
  140. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_mingw_file_conv.cmd +14 -0
  141. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_mingw_iconv_lib.cmd +11 -0
  142. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_mingw_iconv_sample.cmd +8 -0
  143. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_msvc_corr_tests.cmd +11 -0
  144. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_msvc_example.cmd +12 -0
  145. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_msvc_file_conv.cmd +13 -0
  146. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_msvc_iconv_lib.cmd +10 -0
  147. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/build_msvc_iconv_sample.cmd +9 -0
  148. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/html_table.py +25 -0
  149. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/measure.py +94 -0
  150. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/resize.py +20 -0
  151. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/wipe_all.cmd +2 -0
  152. package/deps/simdutf/benchmarks/competition/utf8lut/scripts/wipe_interm.cmd +1 -0
  153. package/deps/simdutf/benchmarks/competition/utf8lut/src/base/CustomMemcpy.h +75 -0
  154. package/deps/simdutf/benchmarks/competition/utf8lut/src/base/PerfDefs.h +47 -0
  155. package/deps/simdutf/benchmarks/competition/utf8lut/src/base/Timing.cpp +17 -0
  156. package/deps/simdutf/benchmarks/competition/utf8lut/src/base/Timing.h +76 -0
  157. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/AllProcessors.cpp +35 -0
  158. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/BaseBufferProcessor.cpp +117 -0
  159. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/BaseBufferProcessor.h +210 -0
  160. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/BufferDecoder.h +158 -0
  161. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/BufferEncoder.h +104 -0
  162. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/ProcessorPlugins.h +334 -0
  163. package/deps/simdutf/benchmarks/competition/utf8lut/src/buffer/ProcessorSelector.h +186 -0
  164. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/DecoderLut.cpp +140 -0
  165. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/DecoderLut.h +42 -0
  166. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/DecoderProcess.h +100 -0
  167. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/Dfa.h +57 -0
  168. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/EncoderLut.cpp +85 -0
  169. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/EncoderLut.h +27 -0
  170. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/EncoderProcess.h +126 -0
  171. package/deps/simdutf/benchmarks/competition/utf8lut/src/core/ProcessTrivial.h +108 -0
  172. package/deps/simdutf/benchmarks/competition/utf8lut/src/iconv/iconv.cpp +139 -0
  173. package/deps/simdutf/benchmarks/competition/utf8lut/src/iconv/iconv.h +74 -0
  174. package/deps/simdutf/benchmarks/competition/utf8lut/src/message/MessageConverter.cpp +65 -0
  175. package/deps/simdutf/benchmarks/competition/utf8lut/src/message/MessageConverter.h +91 -0
  176. package/deps/simdutf/benchmarks/competition/utf8lut/src/tests/CorrectnessTests.cpp +772 -0
  177. package/deps/simdutf/benchmarks/competition/utf8lut/src/tests/Example.cpp +12 -0
  178. package/deps/simdutf/benchmarks/competition/utf8lut/src/tests/FileConverter.cpp +486 -0
  179. package/deps/simdutf/benchmarks/competition/utf8lut/src/tests/iconv_sample.c +162 -0
  180. package/deps/simdutf/benchmarks/competition/utf8lut/src/utf8lut.h +15 -0
  181. package/deps/simdutf/benchmarks/competition/utf8sse4/fromutf8-sse.cpp +292 -0
  182. package/deps/simdutf/benchmarks/competition/utfcpp/LICENSE +23 -0
  183. package/deps/simdutf/benchmarks/competition/utfcpp/README.md +1503 -0
  184. package/deps/simdutf/benchmarks/competition/utfcpp/source/utf8/checked.h +335 -0
  185. package/deps/simdutf/benchmarks/competition/utfcpp/source/utf8/core.h +338 -0
  186. package/deps/simdutf/benchmarks/competition/utfcpp/source/utf8/cpp11.h +103 -0
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  188. package/deps/simdutf/benchmarks/competition/utfcpp/source/utf8/unchecked.h +274 -0
  189. package/deps/simdutf/benchmarks/competition/utfcpp/source/utf8.h +34 -0
  190. package/deps/simdutf/benchmarks/dataset/README.md +155 -0
  191. package/deps/simdutf/benchmarks/dataset/emoji.txt +204 -0
  192. package/deps/simdutf/benchmarks/dataset/scripts/utf8type.py +40 -0
  193. package/deps/simdutf/benchmarks/dataset/wikipedia_mars/Makefile +80 -0
  194. package/deps/simdutf/benchmarks/dataset/wikipedia_mars/convert_to_utf6.py +20 -0
  195. package/deps/simdutf/benchmarks/find/CMakeLists.txt +6 -0
  196. package/deps/simdutf/benchmarks/find/findbenchmark.cpp +63 -0
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  199. package/deps/simdutf/benchmarks/src/CMakeLists.txt +52 -0
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  210. package/deps/simdutf/benchmarks/threaded.cpp +123 -0
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  236. package/deps/simdutf/fuzz/atomic_base64.cpp +448 -0
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  238. package/deps/simdutf/fuzz/build.sh +83 -0
  239. package/deps/simdutf/fuzz/conversion.cpp +669 -0
  240. package/deps/simdutf/fuzz/helpers/.clang-format-ignore +1 -0
  241. package/deps/simdutf/fuzz/helpers/common.h +135 -0
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  243. package/deps/simdutf/fuzz/main.cpp +72 -0
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  245. package/deps/simdutf/fuzz/misc.cpp +216 -0
  246. package/deps/simdutf/fuzz/random_fuzz.sh +154 -0
  247. package/deps/simdutf/fuzz/roundtrip.cpp +588 -0
  248. package/deps/simdutf/fuzz/safe_conversion.cpp +104 -0
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  749. package/src/blake3.ts +2 -1
  750. package/src/diffie-hellman.ts +5 -7
  751. package/src/ecdh.ts +5 -8
@@ -0,0 +1,2430 @@
1
+ #ifndef simd_sub_2_xx
2
+ inline SIMD_type simd_sub_2_xx(SIMD_type v1, SIMD_type v2) {
3
+ return simd_sub_2(v1, v2);
4
+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_xl
8
+ inline SIMD_type simd_sub_2_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(v1, simd_andc(v2, simd_himask_2));
10
+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_xh
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+ inline SIMD_type simd_sub_2_xh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(v1, simd_srli_2(v2, 1));
16
+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_lx
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+ inline SIMD_type simd_sub_2_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_andc(v1, simd_himask_2), v2);
22
+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_ll
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+ inline SIMD_type simd_sub_2_ll(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_andc(v1, simd_himask_2), simd_andc(v2, simd_himask_2));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_lh
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+ inline SIMD_type simd_sub_2_lh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_andc(v1, simd_himask_2), simd_srli_2(v2, 1));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_hx
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+ inline SIMD_type simd_sub_2_hx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_srli_2(v1, 1), v2);
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_2_hl
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+ inline SIMD_type simd_sub_2_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_srli_2(v1, 1), simd_andc(v2, simd_himask_2));
46
+ }
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+ #endif
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+
49
+ #ifndef simd_sub_2_hh
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+ inline SIMD_type simd_sub_2_hh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_2(simd_srli_2(v1, 1), simd_srli_2(v2, 1));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_xx
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+ inline SIMD_type simd_sub_4_xx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(v1, v2);
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_xl
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+ inline SIMD_type simd_sub_4_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(v1, simd_andc(v2, simd_himask_4));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_xh
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+ inline SIMD_type simd_sub_4_xh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(v1, simd_srli_4(v2, 2));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_lx
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+ inline SIMD_type simd_sub_4_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_andc(v1, simd_himask_4), v2);
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_ll
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+ inline SIMD_type simd_sub_4_ll(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_andc(v1, simd_himask_4), simd_andc(v2, simd_himask_4));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_lh
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+ inline SIMD_type simd_sub_4_lh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_andc(v1, simd_himask_4), simd_srli_4(v2, 2));
88
+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_hx
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+ inline SIMD_type simd_sub_4_hx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_srli_4(v1, 2), v2);
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_hl
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+ inline SIMD_type simd_sub_4_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_srli_4(v1, 2), simd_andc(v2, simd_himask_4));
100
+ }
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+ #endif
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+
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+ #ifndef simd_sub_4_hh
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+ inline SIMD_type simd_sub_4_hh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_4(simd_srli_4(v1, 2), simd_srli_4(v2, 2));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_xx
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+ inline SIMD_type simd_sub_8_xx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(v1, v2);
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_xl
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+ inline SIMD_type simd_sub_8_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(v1, simd_andc(v2, simd_himask_8));
118
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_xh
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+ inline SIMD_type simd_sub_8_xh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(v1, simd_srli_8(v2, 4));
124
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_lx
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+ inline SIMD_type simd_sub_8_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_andc(v1, simd_himask_8), v2);
130
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_ll
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+ inline SIMD_type simd_sub_8_ll(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_andc(v1, simd_himask_8), simd_andc(v2, simd_himask_8));
136
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_lh
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+ inline SIMD_type simd_sub_8_lh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_andc(v1, simd_himask_8), simd_srli_8(v2, 4));
142
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_hx
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+ inline SIMD_type simd_sub_8_hx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_srli_8(v1, 4), v2);
148
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_hl
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+ inline SIMD_type simd_sub_8_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_srli_8(v1, 4), simd_andc(v2, simd_himask_8));
154
+ }
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+ #endif
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+
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+ #ifndef simd_sub_8_hh
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+ inline SIMD_type simd_sub_8_hh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_8(simd_srli_8(v1, 4), simd_srli_8(v2, 4));
160
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_xx
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+ inline SIMD_type simd_sub_16_xx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(v1, v2);
166
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_xl
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+ inline SIMD_type simd_sub_16_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(v1, simd_andc(v2, simd_himask_16));
172
+ }
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+ #endif
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+
175
+ #ifndef simd_sub_16_xh
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+ inline SIMD_type simd_sub_16_xh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(v1, simd_srli_16(v2, 8));
178
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_lx
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+ inline SIMD_type simd_sub_16_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_andc(v1, simd_himask_16), v2);
184
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_ll
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+ inline SIMD_type simd_sub_16_ll(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_andc(v1, simd_himask_16), simd_andc(v2, simd_himask_16));
190
+ }
191
+ #endif
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+
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+ #ifndef simd_sub_16_lh
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+ inline SIMD_type simd_sub_16_lh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
196
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_hx
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+ inline SIMD_type simd_sub_16_hx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_srli_16(v1, 8), v2);
202
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_hl
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+ inline SIMD_type simd_sub_16_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_srli_16(v1, 8), simd_andc(v2, simd_himask_16));
208
+ }
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+ #endif
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+
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+ #ifndef simd_sub_16_hh
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+ inline SIMD_type simd_sub_16_hh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_xx
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+ inline SIMD_type simd_sub_32_xx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(v1, v2);
220
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_xl
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+ inline SIMD_type simd_sub_32_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(v1, simd_andc(v2, simd_himask_32));
226
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_xh
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+ inline SIMD_type simd_sub_32_xh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(v1, simd_srli_32(v2, 16));
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+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_lx
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+ inline SIMD_type simd_sub_32_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_andc(v1, simd_himask_32), v2);
238
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_ll
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+ inline SIMD_type simd_sub_32_ll(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_andc(v1, simd_himask_32), simd_andc(v2, simd_himask_32));
244
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_lh
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+ inline SIMD_type simd_sub_32_lh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
250
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_hx
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+ inline SIMD_type simd_sub_32_hx(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_srli_32(v1, 16), v2);
256
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_hl
260
+ inline SIMD_type simd_sub_32_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_srli_32(v1, 16), simd_andc(v2, simd_himask_32));
262
+ }
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+ #endif
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+
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+ #ifndef simd_sub_32_hh
266
+ inline SIMD_type simd_sub_32_hh(SIMD_type v1, SIMD_type v2) {
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+ return simd_sub_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
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+ }
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+ #endif
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+
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+ #ifndef simd_add_2_xx
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+ inline SIMD_type simd_add_2_xx(SIMD_type v1, SIMD_type v2) {
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+ return simd_add_2(v1, v2);
274
+ }
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+ #endif
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+
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+ #ifndef simd_add_2_xl
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+ inline SIMD_type simd_add_2_xl(SIMD_type v1, SIMD_type v2) {
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+ return simd_add_2(v1, simd_andc(v2, simd_himask_2));
280
+ }
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+ #endif
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+
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+ #ifndef simd_add_2_xh
284
+ inline SIMD_type simd_add_2_xh(SIMD_type v1, SIMD_type v2) {
285
+ return simd_add_2(v1, simd_srli_2(v2, 1));
286
+ }
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+ #endif
288
+
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+ #ifndef simd_add_2_lx
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+ inline SIMD_type simd_add_2_lx(SIMD_type v1, SIMD_type v2) {
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+ return simd_add_2(simd_andc(v1, simd_himask_2), v2);
292
+ }
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+ #endif
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+
295
+ #ifndef simd_add_2_ll
296
+ inline SIMD_type simd_add_2_ll(SIMD_type v1, SIMD_type v2) {
297
+ return simd_add_8(simd_andc(v1, simd_himask_2), simd_andc(v2, simd_himask_2));
298
+ }
299
+ #endif
300
+
301
+ #ifndef simd_add_2_lh
302
+ inline SIMD_type simd_add_2_lh(SIMD_type v1, SIMD_type v2) {
303
+ return simd_add_8(simd_andc(v1, simd_himask_2), simd_srli_2(v2, 1));
304
+ }
305
+ #endif
306
+
307
+ #ifndef simd_add_2_hx
308
+ inline SIMD_type simd_add_2_hx(SIMD_type v1, SIMD_type v2) {
309
+ return simd_add_2(simd_srli_2(v1, 1), v2);
310
+ }
311
+ #endif
312
+
313
+ #ifndef simd_add_2_hl
314
+ inline SIMD_type simd_add_2_hl(SIMD_type v1, SIMD_type v2) {
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+ return simd_add_8(simd_srli_2(v1, 1), simd_andc(v2, simd_himask_2));
316
+ }
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+ #endif
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+
319
+ #ifndef simd_add_2_hh
320
+ inline SIMD_type simd_add_2_hh(SIMD_type v1, SIMD_type v2) {
321
+ return simd_add_8(simd_srli_2(v1, 1), simd_srli_2(v2, 1));
322
+ }
323
+ #endif
324
+
325
+ #ifndef simd_add_4_xx
326
+ inline SIMD_type simd_add_4_xx(SIMD_type v1, SIMD_type v2) {
327
+ return simd_add_4(v1, v2);
328
+ }
329
+ #endif
330
+
331
+ #ifndef simd_add_4_xl
332
+ inline SIMD_type simd_add_4_xl(SIMD_type v1, SIMD_type v2) {
333
+ return simd_add_4(v1, simd_andc(v2, simd_himask_4));
334
+ }
335
+ #endif
336
+
337
+ #ifndef simd_add_4_xh
338
+ inline SIMD_type simd_add_4_xh(SIMD_type v1, SIMD_type v2) {
339
+ return simd_add_4(v1, simd_srli_4(v2, 2));
340
+ }
341
+ #endif
342
+
343
+ #ifndef simd_add_4_lx
344
+ inline SIMD_type simd_add_4_lx(SIMD_type v1, SIMD_type v2) {
345
+ return simd_add_4(simd_andc(v1, simd_himask_4), v2);
346
+ }
347
+ #endif
348
+
349
+ #ifndef simd_add_4_ll
350
+ inline SIMD_type simd_add_4_ll(SIMD_type v1, SIMD_type v2) {
351
+ return simd_add_8(simd_andc(v1, simd_himask_4), simd_andc(v2, simd_himask_4));
352
+ }
353
+ #endif
354
+
355
+ #ifndef simd_add_4_lh
356
+ inline SIMD_type simd_add_4_lh(SIMD_type v1, SIMD_type v2) {
357
+ return simd_add_8(simd_andc(v1, simd_himask_4), simd_srli_4(v2, 2));
358
+ }
359
+ #endif
360
+
361
+ #ifndef simd_add_4_hx
362
+ inline SIMD_type simd_add_4_hx(SIMD_type v1, SIMD_type v2) {
363
+ return simd_add_4(simd_srli_4(v1, 2), v2);
364
+ }
365
+ #endif
366
+
367
+ #ifndef simd_add_4_hl
368
+ inline SIMD_type simd_add_4_hl(SIMD_type v1, SIMD_type v2) {
369
+ return simd_add_8(simd_srli_4(v1, 2), simd_andc(v2, simd_himask_4));
370
+ }
371
+ #endif
372
+
373
+ #ifndef simd_add_4_hh
374
+ inline SIMD_type simd_add_4_hh(SIMD_type v1, SIMD_type v2) {
375
+ return simd_add_8(simd_srli_4(v1, 2), simd_srli_4(v2, 2));
376
+ }
377
+ #endif
378
+
379
+ #ifndef simd_add_8_xx
380
+ inline SIMD_type simd_add_8_xx(SIMD_type v1, SIMD_type v2) {
381
+ return simd_add_8(v1, v2);
382
+ }
383
+ #endif
384
+
385
+ #ifndef simd_add_8_xl
386
+ inline SIMD_type simd_add_8_xl(SIMD_type v1, SIMD_type v2) {
387
+ return simd_add_8(v1, simd_andc(v2, simd_himask_8));
388
+ }
389
+ #endif
390
+
391
+ #ifndef simd_add_8_xh
392
+ inline SIMD_type simd_add_8_xh(SIMD_type v1, SIMD_type v2) {
393
+ return simd_add_8(v1, simd_srli_8(v2, 4));
394
+ }
395
+ #endif
396
+
397
+ #ifndef simd_add_8_lx
398
+ inline SIMD_type simd_add_8_lx(SIMD_type v1, SIMD_type v2) {
399
+ return simd_add_8(simd_andc(v1, simd_himask_8), v2);
400
+ }
401
+ #endif
402
+
403
+ #ifndef simd_add_8_ll
404
+ inline SIMD_type simd_add_8_ll(SIMD_type v1, SIMD_type v2) {
405
+ return simd_add_8(simd_andc(v1, simd_himask_8), simd_andc(v2, simd_himask_8));
406
+ }
407
+ #endif
408
+
409
+ #ifndef simd_add_8_lh
410
+ inline SIMD_type simd_add_8_lh(SIMD_type v1, SIMD_type v2) {
411
+ return simd_add_8(simd_andc(v1, simd_himask_8), simd_srli_8(v2, 4));
412
+ }
413
+ #endif
414
+
415
+ #ifndef simd_add_8_hx
416
+ inline SIMD_type simd_add_8_hx(SIMD_type v1, SIMD_type v2) {
417
+ return simd_add_8(simd_srli_8(v1, 4), v2);
418
+ }
419
+ #endif
420
+
421
+ #ifndef simd_add_8_hl
422
+ inline SIMD_type simd_add_8_hl(SIMD_type v1, SIMD_type v2) {
423
+ return simd_add_8(simd_srli_8(v1, 4), simd_andc(v2, simd_himask_8));
424
+ }
425
+ #endif
426
+
427
+ #ifndef simd_add_8_hh
428
+ inline SIMD_type simd_add_8_hh(SIMD_type v1, SIMD_type v2) {
429
+ return simd_add_8(simd_srli_8(v1, 4), simd_srli_8(v2, 4));
430
+ }
431
+ #endif
432
+
433
+ #ifndef simd_add_16_xx
434
+ inline SIMD_type simd_add_16_xx(SIMD_type v1, SIMD_type v2) {
435
+ return simd_add_16(v1, v2);
436
+ }
437
+ #endif
438
+
439
+ #ifndef simd_add_16_xl
440
+ inline SIMD_type simd_add_16_xl(SIMD_type v1, SIMD_type v2) {
441
+ return simd_add_16(v1, simd_andc(v2, simd_himask_16));
442
+ }
443
+ #endif
444
+
445
+ #ifndef simd_add_16_xh
446
+ inline SIMD_type simd_add_16_xh(SIMD_type v1, SIMD_type v2) {
447
+ return simd_add_16(v1, simd_srli_16(v2, 8));
448
+ }
449
+ #endif
450
+
451
+ #ifndef simd_add_16_lx
452
+ inline SIMD_type simd_add_16_lx(SIMD_type v1, SIMD_type v2) {
453
+ return simd_add_16(simd_andc(v1, simd_himask_16), v2);
454
+ }
455
+ #endif
456
+
457
+ #ifndef simd_add_16_ll
458
+ inline SIMD_type simd_add_16_ll(SIMD_type v1, SIMD_type v2) {
459
+ return simd_add_16(simd_andc(v1, simd_himask_16), simd_andc(v2, simd_himask_16));
460
+ }
461
+ #endif
462
+
463
+ #ifndef simd_add_16_lh
464
+ inline SIMD_type simd_add_16_lh(SIMD_type v1, SIMD_type v2) {
465
+ return simd_add_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
466
+ }
467
+ #endif
468
+
469
+ #ifndef simd_add_16_hx
470
+ inline SIMD_type simd_add_16_hx(SIMD_type v1, SIMD_type v2) {
471
+ return simd_add_16(simd_srli_16(v1, 8), v2);
472
+ }
473
+ #endif
474
+
475
+ #ifndef simd_add_16_hl
476
+ inline SIMD_type simd_add_16_hl(SIMD_type v1, SIMD_type v2) {
477
+ return simd_add_16(simd_srli_16(v1, 8), simd_andc(v2, simd_himask_16));
478
+ }
479
+ #endif
480
+
481
+ #ifndef simd_add_16_hh
482
+ inline SIMD_type simd_add_16_hh(SIMD_type v1, SIMD_type v2) {
483
+ return simd_add_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
484
+ }
485
+ #endif
486
+
487
+ #ifndef simd_add_32_xx
488
+ inline SIMD_type simd_add_32_xx(SIMD_type v1, SIMD_type v2) {
489
+ return simd_add_32(v1, v2);
490
+ }
491
+ #endif
492
+
493
+ #ifndef simd_add_32_xl
494
+ inline SIMD_type simd_add_32_xl(SIMD_type v1, SIMD_type v2) {
495
+ return simd_add_32(v1, simd_andc(v2, simd_himask_32));
496
+ }
497
+ #endif
498
+
499
+ #ifndef simd_add_32_xh
500
+ inline SIMD_type simd_add_32_xh(SIMD_type v1, SIMD_type v2) {
501
+ return simd_add_32(v1, simd_srli_32(v2, 16));
502
+ }
503
+ #endif
504
+
505
+ #ifndef simd_add_32_lx
506
+ inline SIMD_type simd_add_32_lx(SIMD_type v1, SIMD_type v2) {
507
+ return simd_add_32(simd_andc(v1, simd_himask_32), v2);
508
+ }
509
+ #endif
510
+
511
+ #ifndef simd_add_32_ll
512
+ inline SIMD_type simd_add_32_ll(SIMD_type v1, SIMD_type v2) {
513
+ return simd_add_32(simd_andc(v1, simd_himask_32), simd_andc(v2, simd_himask_32));
514
+ }
515
+ #endif
516
+
517
+ #ifndef simd_add_32_lh
518
+ inline SIMD_type simd_add_32_lh(SIMD_type v1, SIMD_type v2) {
519
+ return simd_add_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
520
+ }
521
+ #endif
522
+
523
+ #ifndef simd_add_32_hx
524
+ inline SIMD_type simd_add_32_hx(SIMD_type v1, SIMD_type v2) {
525
+ return simd_add_32(simd_srli_32(v1, 16), v2);
526
+ }
527
+ #endif
528
+
529
+ #ifndef simd_add_32_hl
530
+ inline SIMD_type simd_add_32_hl(SIMD_type v1, SIMD_type v2) {
531
+ return simd_add_32(simd_srli_32(v1, 16), simd_andc(v2, simd_himask_32));
532
+ }
533
+ #endif
534
+
535
+ #ifndef simd_add_32_hh
536
+ inline SIMD_type simd_add_32_hh(SIMD_type v1, SIMD_type v2) {
537
+ return simd_add_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
538
+ }
539
+ #endif
540
+
541
+ #ifndef simd_pack_2_xx
542
+ inline SIMD_type simd_pack_2_xx(SIMD_type v1, SIMD_type v2) {
543
+ return simd_pack_2(v1, v2);
544
+ }
545
+ #endif
546
+
547
+ #ifndef simd_pack_2_xl
548
+ inline SIMD_type simd_pack_2_xl(SIMD_type v1, SIMD_type v2) {
549
+ return simd_pack_2(v1, v2);
550
+ }
551
+ #endif
552
+
553
+ #ifndef simd_pack_2_xh
554
+ inline SIMD_type simd_pack_2_xh(SIMD_type v1, SIMD_type v2) {
555
+ return simd_pack_2(v1, simd_srli_16(v2, 1));
556
+ }
557
+ #endif
558
+
559
+ #ifndef simd_pack_2_lx
560
+ inline SIMD_type simd_pack_2_lx(SIMD_type v1, SIMD_type v2) {
561
+ return simd_pack_2(v1, v2);
562
+ }
563
+ #endif
564
+
565
+ #ifndef simd_pack_2_ll
566
+ inline SIMD_type simd_pack_2_ll(SIMD_type v1, SIMD_type v2) {
567
+ return simd_pack_2(v1, v2);
568
+ }
569
+ #endif
570
+
571
+ #ifndef simd_pack_2_lh
572
+ inline SIMD_type simd_pack_2_lh(SIMD_type v1, SIMD_type v2) {
573
+ return simd_pack_2(v1, simd_srli_16(v2, 1));
574
+ }
575
+ #endif
576
+
577
+ #ifndef simd_pack_2_hx
578
+ inline SIMD_type simd_pack_2_hx(SIMD_type v1, SIMD_type v2) {
579
+ return simd_pack_2(simd_srli_16(v1, 1), v2);
580
+ }
581
+ #endif
582
+
583
+ #ifndef simd_pack_2_hl
584
+ inline SIMD_type simd_pack_2_hl(SIMD_type v1, SIMD_type v2) {
585
+ return simd_pack_2(simd_srli_16(v1, 1), v2);
586
+ }
587
+ #endif
588
+
589
+ #ifndef simd_pack_2_hh
590
+ inline SIMD_type simd_pack_2_hh(SIMD_type v1, SIMD_type v2) {
591
+ return simd_pack_2(simd_srli_16(v1, 1), simd_srli_16(v2, 1));
592
+ }
593
+ #endif
594
+
595
+ #ifndef simd_pack_4_xx
596
+ inline SIMD_type simd_pack_4_xx(SIMD_type v1, SIMD_type v2) {
597
+ return simd_pack_4(v1, v2);
598
+ }
599
+ #endif
600
+
601
+ #ifndef simd_pack_4_xl
602
+ inline SIMD_type simd_pack_4_xl(SIMD_type v1, SIMD_type v2) {
603
+ return simd_pack_4(v1, v2);
604
+ }
605
+ #endif
606
+
607
+ #ifndef simd_pack_4_xh
608
+ inline SIMD_type simd_pack_4_xh(SIMD_type v1, SIMD_type v2) {
609
+ return simd_pack_4(v1, simd_srli_16(v2, 2));
610
+ }
611
+ #endif
612
+
613
+ #ifndef simd_pack_4_lx
614
+ inline SIMD_type simd_pack_4_lx(SIMD_type v1, SIMD_type v2) {
615
+ return simd_pack_4(v1, v2);
616
+ }
617
+ #endif
618
+
619
+ #ifndef simd_pack_4_ll
620
+ inline SIMD_type simd_pack_4_ll(SIMD_type v1, SIMD_type v2) {
621
+ return simd_pack_4(v1, v2);
622
+ }
623
+ #endif
624
+
625
+ #ifndef simd_pack_4_lh
626
+ inline SIMD_type simd_pack_4_lh(SIMD_type v1, SIMD_type v2) {
627
+ return simd_pack_4(v1, simd_srli_16(v2, 2));
628
+ }
629
+ #endif
630
+
631
+ #ifndef simd_pack_4_hx
632
+ inline SIMD_type simd_pack_4_hx(SIMD_type v1, SIMD_type v2) {
633
+ return simd_pack_4(simd_srli_16(v1, 2), v2);
634
+ }
635
+ #endif
636
+
637
+ #ifndef simd_pack_4_hl
638
+ inline SIMD_type simd_pack_4_hl(SIMD_type v1, SIMD_type v2) {
639
+ return simd_pack_4(simd_srli_16(v1, 2), v2);
640
+ }
641
+ #endif
642
+
643
+ #ifndef simd_pack_4_hh
644
+ inline SIMD_type simd_pack_4_hh(SIMD_type v1, SIMD_type v2) {
645
+ return simd_pack_4(simd_srli_16(v1, 2), simd_srli_16(v2, 2));
646
+ }
647
+ #endif
648
+
649
+ #ifndef simd_pack_8_xx
650
+ inline SIMD_type simd_pack_8_xx(SIMD_type v1, SIMD_type v2) {
651
+ return simd_pack_8(v1, v2);
652
+ }
653
+ #endif
654
+
655
+ #ifndef simd_pack_8_xl
656
+ inline SIMD_type simd_pack_8_xl(SIMD_type v1, SIMD_type v2) {
657
+ return simd_pack_8(v1, v2);
658
+ }
659
+ #endif
660
+
661
+ #ifndef simd_pack_8_xh
662
+ inline SIMD_type simd_pack_8_xh(SIMD_type v1, SIMD_type v2) {
663
+ return simd_pack_8(v1, simd_srli_16(v2, 4));
664
+ }
665
+ #endif
666
+
667
+ #ifndef simd_pack_8_lx
668
+ inline SIMD_type simd_pack_8_lx(SIMD_type v1, SIMD_type v2) {
669
+ return simd_pack_8(v1, v2);
670
+ }
671
+ #endif
672
+
673
+ #ifndef simd_pack_8_ll
674
+ inline SIMD_type simd_pack_8_ll(SIMD_type v1, SIMD_type v2) {
675
+ return simd_pack_8(v1, v2);
676
+ }
677
+ #endif
678
+
679
+ #ifndef simd_pack_8_lh
680
+ inline SIMD_type simd_pack_8_lh(SIMD_type v1, SIMD_type v2) {
681
+ return simd_pack_8(v1, simd_srli_16(v2, 4));
682
+ }
683
+ #endif
684
+
685
+ #ifndef simd_pack_8_hx
686
+ inline SIMD_type simd_pack_8_hx(SIMD_type v1, SIMD_type v2) {
687
+ return simd_pack_8(simd_srli_16(v1, 4), v2);
688
+ }
689
+ #endif
690
+
691
+ #ifndef simd_pack_8_hl
692
+ inline SIMD_type simd_pack_8_hl(SIMD_type v1, SIMD_type v2) {
693
+ return simd_pack_8(simd_srli_16(v1, 4), v2);
694
+ }
695
+ #endif
696
+
697
+ #ifndef simd_pack_8_hh
698
+ inline SIMD_type simd_pack_8_hh(SIMD_type v1, SIMD_type v2) {
699
+ return simd_pack_8(simd_srli_16(v1, 4), simd_srli_16(v2, 4));
700
+ }
701
+ #endif
702
+
703
+ #ifndef simd_pack_16_xx
704
+ inline SIMD_type simd_pack_16_xx(SIMD_type v1, SIMD_type v2) {
705
+ return simd_pack_16(v1, v2);
706
+ }
707
+ #endif
708
+
709
+ #ifndef simd_pack_16_xl
710
+ inline SIMD_type simd_pack_16_xl(SIMD_type v1, SIMD_type v2) {
711
+ return simd_pack_16(v1, v2);
712
+ }
713
+ #endif
714
+
715
+ #ifndef simd_pack_16_xh
716
+ inline SIMD_type simd_pack_16_xh(SIMD_type v1, SIMD_type v2) {
717
+ return simd_pack_16(v1, simd_srli_16(v2, 8));
718
+ }
719
+ #endif
720
+
721
+ #ifndef simd_pack_16_lx
722
+ inline SIMD_type simd_pack_16_lx(SIMD_type v1, SIMD_type v2) {
723
+ return simd_pack_16(v1, v2);
724
+ }
725
+ #endif
726
+
727
+ #ifndef simd_pack_16_ll
728
+ inline SIMD_type simd_pack_16_ll(SIMD_type v1, SIMD_type v2) {
729
+ return simd_pack_16(v1, v2);
730
+ }
731
+ #endif
732
+
733
+ #ifndef simd_pack_16_lh
734
+ inline SIMD_type simd_pack_16_lh(SIMD_type v1, SIMD_type v2) {
735
+ return simd_pack_16(v1, simd_srli_16(v2, 8));
736
+ }
737
+ #endif
738
+
739
+ #ifndef simd_pack_16_hx
740
+ inline SIMD_type simd_pack_16_hx(SIMD_type v1, SIMD_type v2) {
741
+ return simd_pack_16(simd_srli_16(v1, 8), v2);
742
+ }
743
+ #endif
744
+
745
+ #ifndef simd_pack_16_hl
746
+ inline SIMD_type simd_pack_16_hl(SIMD_type v1, SIMD_type v2) {
747
+ return simd_pack_16(simd_srli_16(v1, 8), v2);
748
+ }
749
+ #endif
750
+
751
+ #ifndef simd_pack_16_hh
752
+ inline SIMD_type simd_pack_16_hh(SIMD_type v1, SIMD_type v2) {
753
+ return simd_pack_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
754
+ }
755
+ #endif
756
+
757
+ #ifndef simd_pack_32_xx
758
+ inline SIMD_type simd_pack_32_xx(SIMD_type v1, SIMD_type v2) {
759
+ return simd_pack_32(v1, v2);
760
+ }
761
+ #endif
762
+
763
+ #ifndef simd_pack_32_xl
764
+ inline SIMD_type simd_pack_32_xl(SIMD_type v1, SIMD_type v2) {
765
+ return simd_pack_32(v1, v2);
766
+ }
767
+ #endif
768
+
769
+ #ifndef simd_pack_32_xh
770
+ inline SIMD_type simd_pack_32_xh(SIMD_type v1, SIMD_type v2) {
771
+ return simd_pack_32(v1, simd_srli_32(v2, 16));
772
+ }
773
+ #endif
774
+
775
+ #ifndef simd_pack_32_lx
776
+ inline SIMD_type simd_pack_32_lx(SIMD_type v1, SIMD_type v2) {
777
+ return simd_pack_32(v1, v2);
778
+ }
779
+ #endif
780
+
781
+ #ifndef simd_pack_32_ll
782
+ inline SIMD_type simd_pack_32_ll(SIMD_type v1, SIMD_type v2) {
783
+ return simd_pack_32(v1, v2);
784
+ }
785
+ #endif
786
+
787
+ #ifndef simd_pack_32_lh
788
+ inline SIMD_type simd_pack_32_lh(SIMD_type v1, SIMD_type v2) {
789
+ return simd_pack_32(v1, simd_srli_32(v2, 16));
790
+ }
791
+ #endif
792
+
793
+ #ifndef simd_pack_32_hx
794
+ inline SIMD_type simd_pack_32_hx(SIMD_type v1, SIMD_type v2) {
795
+ return simd_pack_32(simd_srli_32(v1, 16), v2);
796
+ }
797
+ #endif
798
+
799
+ #ifndef simd_pack_32_hl
800
+ inline SIMD_type simd_pack_32_hl(SIMD_type v1, SIMD_type v2) {
801
+ return simd_pack_32(simd_srli_32(v1, 16), v2);
802
+ }
803
+ #endif
804
+
805
+ #ifndef simd_pack_32_hh
806
+ inline SIMD_type simd_pack_32_hh(SIMD_type v1, SIMD_type v2) {
807
+ return simd_pack_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
808
+ }
809
+ #endif
810
+
811
+ #ifndef simd_mergeh_2_xx
812
+ inline SIMD_type simd_mergeh_2_xx(SIMD_type v1, SIMD_type v2) {
813
+ return simd_mergeh_2(v1, v2);
814
+ }
815
+ #endif
816
+
817
+ #ifndef simd_mergeh_2_xl
818
+ inline SIMD_type simd_mergeh_2_xl(SIMD_type v1, SIMD_type v2) {
819
+ return simd_mergeh_2(v1, simd_andc(v2, simd_himask_2));
820
+ }
821
+ #endif
822
+
823
+ #ifndef simd_mergeh_2_xh
824
+ inline SIMD_type simd_mergeh_2_xh(SIMD_type v1, SIMD_type v2) {
825
+ return simd_mergeh_2(v1, simd_srli_2(v2, 1));
826
+ }
827
+ #endif
828
+
829
+ #ifndef simd_mergeh_2_lx
830
+ inline SIMD_type simd_mergeh_2_lx(SIMD_type v1, SIMD_type v2) {
831
+ return simd_mergeh_2(simd_andc(v1, simd_himask_2), v2);
832
+ }
833
+ #endif
834
+
835
+ #ifndef simd_mergeh_2_ll
836
+ inline SIMD_type simd_mergeh_2_ll(SIMD_type v1, SIMD_type v2) {
837
+ return simd_mergeh_2(simd_andc(v1, simd_himask_2), simd_andc(v2, simd_himask_2));
838
+ }
839
+ #endif
840
+
841
+ #ifndef simd_mergeh_2_lh
842
+ inline SIMD_type simd_mergeh_2_lh(SIMD_type v1, SIMD_type v2) {
843
+ return simd_mergeh_2(simd_andc(v1, simd_himask_2), simd_srli_2(v2, 1));
844
+ }
845
+ #endif
846
+
847
+ #ifndef simd_mergeh_2_hx
848
+ inline SIMD_type simd_mergeh_2_hx(SIMD_type v1, SIMD_type v2) {
849
+ return simd_mergeh_2(simd_srli_2(v1, 1), v2);
850
+ }
851
+ #endif
852
+
853
+ #ifndef simd_mergeh_2_hl
854
+ inline SIMD_type simd_mergeh_2_hl(SIMD_type v1, SIMD_type v2) {
855
+ return simd_mergeh_2(simd_srli_2(v1, 1), simd_andc(v2, simd_himask_2));
856
+ }
857
+ #endif
858
+
859
+ #ifndef simd_mergeh_2_hh
860
+ inline SIMD_type simd_mergeh_2_hh(SIMD_type v1, SIMD_type v2) {
861
+ return simd_mergeh_2(simd_srli_2(v1, 1), simd_srli_2(v2, 1));
862
+ }
863
+ #endif
864
+
865
+ #ifndef simd_mergeh_4_xx
866
+ inline SIMD_type simd_mergeh_4_xx(SIMD_type v1, SIMD_type v2) {
867
+ return simd_mergeh_4(v1, v2);
868
+ }
869
+ #endif
870
+
871
+ #ifndef simd_mergeh_4_xl
872
+ inline SIMD_type simd_mergeh_4_xl(SIMD_type v1, SIMD_type v2) {
873
+ return simd_mergeh_4(v1, simd_andc(v2, simd_himask_4));
874
+ }
875
+ #endif
876
+
877
+ #ifndef simd_mergeh_4_xh
878
+ inline SIMD_type simd_mergeh_4_xh(SIMD_type v1, SIMD_type v2) {
879
+ return simd_mergeh_4(v1, simd_srli_4(v2, 2));
880
+ }
881
+ #endif
882
+
883
+ #ifndef simd_mergeh_4_lx
884
+ inline SIMD_type simd_mergeh_4_lx(SIMD_type v1, SIMD_type v2) {
885
+ return simd_mergeh_4(simd_andc(v1, simd_himask_4), v2);
886
+ }
887
+ #endif
888
+
889
+ #ifndef simd_mergeh_4_ll
890
+ inline SIMD_type simd_mergeh_4_ll(SIMD_type v1, SIMD_type v2) {
891
+ return simd_mergeh_4(simd_andc(v1, simd_himask_4), simd_andc(v2, simd_himask_4));
892
+ }
893
+ #endif
894
+
895
+ #ifndef simd_mergeh_4_lh
896
+ inline SIMD_type simd_mergeh_4_lh(SIMD_type v1, SIMD_type v2) {
897
+ return simd_mergeh_4(simd_andc(v1, simd_himask_4), simd_srli_4(v2, 2));
898
+ }
899
+ #endif
900
+
901
+ #ifndef simd_mergeh_4_hx
902
+ inline SIMD_type simd_mergeh_4_hx(SIMD_type v1, SIMD_type v2) {
903
+ return simd_mergeh_4(simd_srli_4(v1, 2), v2);
904
+ }
905
+ #endif
906
+
907
+ #ifndef simd_mergeh_4_hl
908
+ inline SIMD_type simd_mergeh_4_hl(SIMD_type v1, SIMD_type v2) {
909
+ return simd_mergeh_4(simd_srli_4(v1, 2), simd_andc(v2, simd_himask_4));
910
+ }
911
+ #endif
912
+
913
+ #ifndef simd_mergeh_4_hh
914
+ inline SIMD_type simd_mergeh_4_hh(SIMD_type v1, SIMD_type v2) {
915
+ return simd_mergeh_4(simd_srli_4(v1, 2), simd_srli_4(v2, 2));
916
+ }
917
+ #endif
918
+
919
+ #ifndef simd_mergeh_8_xx
920
+ inline SIMD_type simd_mergeh_8_xx(SIMD_type v1, SIMD_type v2) {
921
+ return simd_mergeh_8(v1, v2);
922
+ }
923
+ #endif
924
+
925
+ #ifndef simd_mergeh_8_xl
926
+ inline SIMD_type simd_mergeh_8_xl(SIMD_type v1, SIMD_type v2) {
927
+ return simd_mergeh_8(v1, simd_andc(v2, simd_himask_8));
928
+ }
929
+ #endif
930
+
931
+ #ifndef simd_mergeh_8_xh
932
+ inline SIMD_type simd_mergeh_8_xh(SIMD_type v1, SIMD_type v2) {
933
+ return simd_mergeh_8(v1, simd_srli_8(v2, 4));
934
+ }
935
+ #endif
936
+
937
+ #ifndef simd_mergeh_8_lx
938
+ inline SIMD_type simd_mergeh_8_lx(SIMD_type v1, SIMD_type v2) {
939
+ return simd_mergeh_8(simd_andc(v1, simd_himask_8), v2);
940
+ }
941
+ #endif
942
+
943
+ #ifndef simd_mergeh_8_ll
944
+ inline SIMD_type simd_mergeh_8_ll(SIMD_type v1, SIMD_type v2) {
945
+ return simd_mergeh_8(simd_andc(v1, simd_himask_8), simd_andc(v2, simd_himask_8));
946
+ }
947
+ #endif
948
+
949
+ #ifndef simd_mergeh_8_lh
950
+ inline SIMD_type simd_mergeh_8_lh(SIMD_type v1, SIMD_type v2) {
951
+ return simd_mergeh_8(simd_andc(v1, simd_himask_8), simd_srli_8(v2, 4));
952
+ }
953
+ #endif
954
+
955
+ #ifndef simd_mergeh_8_hx
956
+ inline SIMD_type simd_mergeh_8_hx(SIMD_type v1, SIMD_type v2) {
957
+ return simd_mergeh_8(simd_srli_8(v1, 4), v2);
958
+ }
959
+ #endif
960
+
961
+ #ifndef simd_mergeh_8_hl
962
+ inline SIMD_type simd_mergeh_8_hl(SIMD_type v1, SIMD_type v2) {
963
+ return simd_mergeh_8(simd_srli_8(v1, 4), simd_andc(v2, simd_himask_8));
964
+ }
965
+ #endif
966
+
967
+ #ifndef simd_mergeh_8_hh
968
+ inline SIMD_type simd_mergeh_8_hh(SIMD_type v1, SIMD_type v2) {
969
+ return simd_mergeh_8(simd_srli_8(v1, 4), simd_srli_8(v2, 4));
970
+ }
971
+ #endif
972
+
973
+ #ifndef simd_mergeh_16_xx
974
+ inline SIMD_type simd_mergeh_16_xx(SIMD_type v1, SIMD_type v2) {
975
+ return simd_mergeh_16(v1, v2);
976
+ }
977
+ #endif
978
+
979
+ #ifndef simd_mergeh_16_xl
980
+ inline SIMD_type simd_mergeh_16_xl(SIMD_type v1, SIMD_type v2) {
981
+ return simd_mergeh_16(v1, simd_andc(v2, simd_himask_16));
982
+ }
983
+ #endif
984
+
985
+ #ifndef simd_mergeh_16_xh
986
+ inline SIMD_type simd_mergeh_16_xh(SIMD_type v1, SIMD_type v2) {
987
+ return simd_mergeh_16(v1, simd_srli_16(v2, 8));
988
+ }
989
+ #endif
990
+
991
+ #ifndef simd_mergeh_16_lx
992
+ inline SIMD_type simd_mergeh_16_lx(SIMD_type v1, SIMD_type v2) {
993
+ return simd_mergeh_16(simd_andc(v1, simd_himask_16), v2);
994
+ }
995
+ #endif
996
+
997
+ #ifndef simd_mergeh_16_ll
998
+ inline SIMD_type simd_mergeh_16_ll(SIMD_type v1, SIMD_type v2) {
999
+ return simd_mergeh_16(simd_andc(v1, simd_himask_16), simd_andc(v2, simd_himask_16));
1000
+ }
1001
+ #endif
1002
+
1003
+ #ifndef simd_mergeh_16_lh
1004
+ inline SIMD_type simd_mergeh_16_lh(SIMD_type v1, SIMD_type v2) {
1005
+ return simd_mergeh_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
1006
+ }
1007
+ #endif
1008
+
1009
+ #ifndef simd_mergeh_16_hx
1010
+ inline SIMD_type simd_mergeh_16_hx(SIMD_type v1, SIMD_type v2) {
1011
+ return simd_mergeh_16(simd_srli_16(v1, 8), v2);
1012
+ }
1013
+ #endif
1014
+
1015
+ #ifndef simd_mergeh_16_hl
1016
+ inline SIMD_type simd_mergeh_16_hl(SIMD_type v1, SIMD_type v2) {
1017
+ return simd_mergeh_16(simd_srli_16(v1, 8), simd_andc(v2, simd_himask_16));
1018
+ }
1019
+ #endif
1020
+
1021
+ #ifndef simd_mergeh_16_hh
1022
+ inline SIMD_type simd_mergeh_16_hh(SIMD_type v1, SIMD_type v2) {
1023
+ return simd_mergeh_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
1024
+ }
1025
+ #endif
1026
+
1027
+ #ifndef simd_mergeh_32_xx
1028
+ inline SIMD_type simd_mergeh_32_xx(SIMD_type v1, SIMD_type v2) {
1029
+ return simd_mergeh_32(v1, v2);
1030
+ }
1031
+ #endif
1032
+
1033
+ #ifndef simd_mergeh_32_xl
1034
+ inline SIMD_type simd_mergeh_32_xl(SIMD_type v1, SIMD_type v2) {
1035
+ return simd_mergeh_32(v1, simd_andc(v2, simd_himask_32));
1036
+ }
1037
+ #endif
1038
+
1039
+ #ifndef simd_mergeh_32_xh
1040
+ inline SIMD_type simd_mergeh_32_xh(SIMD_type v1, SIMD_type v2) {
1041
+ return simd_mergeh_32(v1, simd_srli_32(v2, 16));
1042
+ }
1043
+ #endif
1044
+
1045
+ #ifndef simd_mergeh_32_lx
1046
+ inline SIMD_type simd_mergeh_32_lx(SIMD_type v1, SIMD_type v2) {
1047
+ return simd_mergeh_32(simd_andc(v1, simd_himask_32), v2);
1048
+ }
1049
+ #endif
1050
+
1051
+ #ifndef simd_mergeh_32_ll
1052
+ inline SIMD_type simd_mergeh_32_ll(SIMD_type v1, SIMD_type v2) {
1053
+ return simd_mergeh_32(simd_andc(v1, simd_himask_32), simd_andc(v2, simd_himask_32));
1054
+ }
1055
+ #endif
1056
+
1057
+ #ifndef simd_mergeh_32_lh
1058
+ inline SIMD_type simd_mergeh_32_lh(SIMD_type v1, SIMD_type v2) {
1059
+ return simd_mergeh_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
1060
+ }
1061
+ #endif
1062
+
1063
+ #ifndef simd_mergeh_32_hx
1064
+ inline SIMD_type simd_mergeh_32_hx(SIMD_type v1, SIMD_type v2) {
1065
+ return simd_mergeh_32(simd_srli_32(v1, 16), v2);
1066
+ }
1067
+ #endif
1068
+
1069
+ #ifndef simd_mergeh_32_hl
1070
+ inline SIMD_type simd_mergeh_32_hl(SIMD_type v1, SIMD_type v2) {
1071
+ return simd_mergeh_32(simd_srli_32(v1, 16), simd_andc(v2, simd_himask_32));
1072
+ }
1073
+ #endif
1074
+
1075
+ #ifndef simd_mergeh_32_hh
1076
+ inline SIMD_type simd_mergeh_32_hh(SIMD_type v1, SIMD_type v2) {
1077
+ return simd_mergeh_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
1078
+ }
1079
+ #endif
1080
+
1081
+ #ifndef simd_mergel_2_xx
1082
+ inline SIMD_type simd_mergel_2_xx(SIMD_type v1, SIMD_type v2) {
1083
+ return simd_mergel_2(v1, v2);
1084
+ }
1085
+ #endif
1086
+
1087
+ #ifndef simd_mergel_2_xl
1088
+ inline SIMD_type simd_mergel_2_xl(SIMD_type v1, SIMD_type v2) {
1089
+ return simd_mergel_2(v1, simd_andc(v2, simd_himask_2));
1090
+ }
1091
+ #endif
1092
+
1093
+ #ifndef simd_mergel_2_xh
1094
+ inline SIMD_type simd_mergel_2_xh(SIMD_type v1, SIMD_type v2) {
1095
+ return simd_mergel_2(v1, simd_srli_2(v2, 1));
1096
+ }
1097
+ #endif
1098
+
1099
+ #ifndef simd_mergel_2_lx
1100
+ inline SIMD_type simd_mergel_2_lx(SIMD_type v1, SIMD_type v2) {
1101
+ return simd_mergel_2(simd_andc(v1, simd_himask_2), v2);
1102
+ }
1103
+ #endif
1104
+
1105
+ #ifndef simd_mergel_2_ll
1106
+ inline SIMD_type simd_mergel_2_ll(SIMD_type v1, SIMD_type v2) {
1107
+ return simd_mergel_2(simd_andc(v1, simd_himask_2), simd_andc(v2, simd_himask_2));
1108
+ }
1109
+ #endif
1110
+
1111
+ #ifndef simd_mergel_2_lh
1112
+ inline SIMD_type simd_mergel_2_lh(SIMD_type v1, SIMD_type v2) {
1113
+ return simd_mergel_2(simd_andc(v1, simd_himask_2), simd_srli_2(v2, 1));
1114
+ }
1115
+ #endif
1116
+
1117
+ #ifndef simd_mergel_2_hx
1118
+ inline SIMD_type simd_mergel_2_hx(SIMD_type v1, SIMD_type v2) {
1119
+ return simd_mergel_2(simd_srli_2(v1, 1), v2);
1120
+ }
1121
+ #endif
1122
+
1123
+ #ifndef simd_mergel_2_hl
1124
+ inline SIMD_type simd_mergel_2_hl(SIMD_type v1, SIMD_type v2) {
1125
+ return simd_mergel_2(simd_srli_2(v1, 1), simd_andc(v2, simd_himask_2));
1126
+ }
1127
+ #endif
1128
+
1129
+ #ifndef simd_mergel_2_hh
1130
+ inline SIMD_type simd_mergel_2_hh(SIMD_type v1, SIMD_type v2) {
1131
+ return simd_mergel_2(simd_srli_2(v1, 1), simd_srli_2(v2, 1));
1132
+ }
1133
+ #endif
1134
+
1135
+ #ifndef simd_mergel_4_xx
1136
+ inline SIMD_type simd_mergel_4_xx(SIMD_type v1, SIMD_type v2) {
1137
+ return simd_mergel_4(v1, v2);
1138
+ }
1139
+ #endif
1140
+
1141
+ #ifndef simd_mergel_4_xl
1142
+ inline SIMD_type simd_mergel_4_xl(SIMD_type v1, SIMD_type v2) {
1143
+ return simd_mergel_4(v1, simd_andc(v2, simd_himask_4));
1144
+ }
1145
+ #endif
1146
+
1147
+ #ifndef simd_mergel_4_xh
1148
+ inline SIMD_type simd_mergel_4_xh(SIMD_type v1, SIMD_type v2) {
1149
+ return simd_mergel_4(v1, simd_srli_4(v2, 2));
1150
+ }
1151
+ #endif
1152
+
1153
+ #ifndef simd_mergel_4_lx
1154
+ inline SIMD_type simd_mergel_4_lx(SIMD_type v1, SIMD_type v2) {
1155
+ return simd_mergel_4(simd_andc(v1, simd_himask_4), v2);
1156
+ }
1157
+ #endif
1158
+
1159
+ #ifndef simd_mergel_4_ll
1160
+ inline SIMD_type simd_mergel_4_ll(SIMD_type v1, SIMD_type v2) {
1161
+ return simd_mergel_4(simd_andc(v1, simd_himask_4), simd_andc(v2, simd_himask_4));
1162
+ }
1163
+ #endif
1164
+
1165
+ #ifndef simd_mergel_4_lh
1166
+ inline SIMD_type simd_mergel_4_lh(SIMD_type v1, SIMD_type v2) {
1167
+ return simd_mergel_4(simd_andc(v1, simd_himask_4), simd_srli_4(v2, 2));
1168
+ }
1169
+ #endif
1170
+
1171
+ #ifndef simd_mergel_4_hx
1172
+ inline SIMD_type simd_mergel_4_hx(SIMD_type v1, SIMD_type v2) {
1173
+ return simd_mergel_4(simd_srli_4(v1, 2), v2);
1174
+ }
1175
+ #endif
1176
+
1177
+ #ifndef simd_mergel_4_hl
1178
+ inline SIMD_type simd_mergel_4_hl(SIMD_type v1, SIMD_type v2) {
1179
+ return simd_mergel_4(simd_srli_4(v1, 2), simd_andc(v2, simd_himask_4));
1180
+ }
1181
+ #endif
1182
+
1183
+ #ifndef simd_mergel_4_hh
1184
+ inline SIMD_type simd_mergel_4_hh(SIMD_type v1, SIMD_type v2) {
1185
+ return simd_mergel_4(simd_srli_4(v1, 2), simd_srli_4(v2, 2));
1186
+ }
1187
+ #endif
1188
+
1189
+ #ifndef simd_mergel_8_xx
1190
+ inline SIMD_type simd_mergel_8_xx(SIMD_type v1, SIMD_type v2) {
1191
+ return simd_mergel_8(v1, v2);
1192
+ }
1193
+ #endif
1194
+
1195
+ #ifndef simd_mergel_8_xl
1196
+ inline SIMD_type simd_mergel_8_xl(SIMD_type v1, SIMD_type v2) {
1197
+ return simd_mergel_8(v1, simd_andc(v2, simd_himask_8));
1198
+ }
1199
+ #endif
1200
+
1201
+ #ifndef simd_mergel_8_xh
1202
+ inline SIMD_type simd_mergel_8_xh(SIMD_type v1, SIMD_type v2) {
1203
+ return simd_mergel_8(v1, simd_srli_8(v2, 4));
1204
+ }
1205
+ #endif
1206
+
1207
+ #ifndef simd_mergel_8_lx
1208
+ inline SIMD_type simd_mergel_8_lx(SIMD_type v1, SIMD_type v2) {
1209
+ return simd_mergel_8(simd_andc(v1, simd_himask_8), v2);
1210
+ }
1211
+ #endif
1212
+
1213
+ #ifndef simd_mergel_8_ll
1214
+ inline SIMD_type simd_mergel_8_ll(SIMD_type v1, SIMD_type v2) {
1215
+ return simd_mergel_8(simd_andc(v1, simd_himask_8), simd_andc(v2, simd_himask_8));
1216
+ }
1217
+ #endif
1218
+
1219
+ #ifndef simd_mergel_8_lh
1220
+ inline SIMD_type simd_mergel_8_lh(SIMD_type v1, SIMD_type v2) {
1221
+ return simd_mergel_8(simd_andc(v1, simd_himask_8), simd_srli_8(v2, 4));
1222
+ }
1223
+ #endif
1224
+
1225
+ #ifndef simd_mergel_8_hx
1226
+ inline SIMD_type simd_mergel_8_hx(SIMD_type v1, SIMD_type v2) {
1227
+ return simd_mergel_8(simd_srli_8(v1, 4), v2);
1228
+ }
1229
+ #endif
1230
+
1231
+ #ifndef simd_mergel_8_hl
1232
+ inline SIMD_type simd_mergel_8_hl(SIMD_type v1, SIMD_type v2) {
1233
+ return simd_mergel_8(simd_srli_8(v1, 4), simd_andc(v2, simd_himask_8));
1234
+ }
1235
+ #endif
1236
+
1237
+ #ifndef simd_mergel_8_hh
1238
+ inline SIMD_type simd_mergel_8_hh(SIMD_type v1, SIMD_type v2) {
1239
+ return simd_mergel_8(simd_srli_8(v1, 4), simd_srli_8(v2, 4));
1240
+ }
1241
+ #endif
1242
+
1243
+ #ifndef simd_mergel_16_xx
1244
+ inline SIMD_type simd_mergel_16_xx(SIMD_type v1, SIMD_type v2) {
1245
+ return simd_mergel_16(v1, v2);
1246
+ }
1247
+ #endif
1248
+
1249
+ #ifndef simd_mergel_16_xl
1250
+ inline SIMD_type simd_mergel_16_xl(SIMD_type v1, SIMD_type v2) {
1251
+ return simd_mergel_16(v1, simd_andc(v2, simd_himask_16));
1252
+ }
1253
+ #endif
1254
+
1255
+ #ifndef simd_mergel_16_xh
1256
+ inline SIMD_type simd_mergel_16_xh(SIMD_type v1, SIMD_type v2) {
1257
+ return simd_mergel_16(v1, simd_srli_16(v2, 8));
1258
+ }
1259
+ #endif
1260
+
1261
+ #ifndef simd_mergel_16_lx
1262
+ inline SIMD_type simd_mergel_16_lx(SIMD_type v1, SIMD_type v2) {
1263
+ return simd_mergel_16(simd_andc(v1, simd_himask_16), v2);
1264
+ }
1265
+ #endif
1266
+
1267
+ #ifndef simd_mergel_16_ll
1268
+ inline SIMD_type simd_mergel_16_ll(SIMD_type v1, SIMD_type v2) {
1269
+ return simd_mergel_16(simd_andc(v1, simd_himask_16), simd_andc(v2, simd_himask_16));
1270
+ }
1271
+ #endif
1272
+
1273
+ #ifndef simd_mergel_16_lh
1274
+ inline SIMD_type simd_mergel_16_lh(SIMD_type v1, SIMD_type v2) {
1275
+ return simd_mergel_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
1276
+ }
1277
+ #endif
1278
+
1279
+ #ifndef simd_mergel_16_hx
1280
+ inline SIMD_type simd_mergel_16_hx(SIMD_type v1, SIMD_type v2) {
1281
+ return simd_mergel_16(simd_srli_16(v1, 8), v2);
1282
+ }
1283
+ #endif
1284
+
1285
+ #ifndef simd_mergel_16_hl
1286
+ inline SIMD_type simd_mergel_16_hl(SIMD_type v1, SIMD_type v2) {
1287
+ return simd_mergel_16(simd_srli_16(v1, 8), simd_andc(v2, simd_himask_16));
1288
+ }
1289
+ #endif
1290
+
1291
+ #ifndef simd_mergel_16_hh
1292
+ inline SIMD_type simd_mergel_16_hh(SIMD_type v1, SIMD_type v2) {
1293
+ return simd_mergel_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
1294
+ }
1295
+ #endif
1296
+
1297
+ #ifndef simd_mergel_32_xx
1298
+ inline SIMD_type simd_mergel_32_xx(SIMD_type v1, SIMD_type v2) {
1299
+ return simd_mergel_32(v1, v2);
1300
+ }
1301
+ #endif
1302
+
1303
+ #ifndef simd_mergel_32_xl
1304
+ inline SIMD_type simd_mergel_32_xl(SIMD_type v1, SIMD_type v2) {
1305
+ return simd_mergel_32(v1, simd_andc(v2, simd_himask_32));
1306
+ }
1307
+ #endif
1308
+
1309
+ #ifndef simd_mergel_32_xh
1310
+ inline SIMD_type simd_mergel_32_xh(SIMD_type v1, SIMD_type v2) {
1311
+ return simd_mergel_32(v1, simd_srli_32(v2, 16));
1312
+ }
1313
+ #endif
1314
+
1315
+ #ifndef simd_mergel_32_lx
1316
+ inline SIMD_type simd_mergel_32_lx(SIMD_type v1, SIMD_type v2) {
1317
+ return simd_mergel_32(simd_andc(v1, simd_himask_32), v2);
1318
+ }
1319
+ #endif
1320
+
1321
+ #ifndef simd_mergel_32_ll
1322
+ inline SIMD_type simd_mergel_32_ll(SIMD_type v1, SIMD_type v2) {
1323
+ return simd_mergel_32(simd_andc(v1, simd_himask_32), simd_andc(v2, simd_himask_32));
1324
+ }
1325
+ #endif
1326
+
1327
+ #ifndef simd_mergel_32_lh
1328
+ inline SIMD_type simd_mergel_32_lh(SIMD_type v1, SIMD_type v2) {
1329
+ return simd_mergel_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
1330
+ }
1331
+ #endif
1332
+
1333
+ #ifndef simd_mergel_32_hx
1334
+ inline SIMD_type simd_mergel_32_hx(SIMD_type v1, SIMD_type v2) {
1335
+ return simd_mergel_32(simd_srli_32(v1, 16), v2);
1336
+ }
1337
+ #endif
1338
+
1339
+ #ifndef simd_mergel_32_hl
1340
+ inline SIMD_type simd_mergel_32_hl(SIMD_type v1, SIMD_type v2) {
1341
+ return simd_mergel_32(simd_srli_32(v1, 16), simd_andc(v2, simd_himask_32));
1342
+ }
1343
+ #endif
1344
+
1345
+ #ifndef simd_mergel_32_hh
1346
+ inline SIMD_type simd_mergel_32_hh(SIMD_type v1, SIMD_type v2) {
1347
+ return simd_mergel_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
1348
+ }
1349
+ #endif
1350
+
1351
+ #ifndef simd_sll_2_xx
1352
+ inline SIMD_type simd_sll_2_xx(SIMD_type v1, SIMD_type v2) {
1353
+ return simd_sll_2(v1, v2);
1354
+ }
1355
+ #endif
1356
+
1357
+ #ifndef simd_sll_2_xl
1358
+ inline SIMD_type simd_sll_2_xl(SIMD_type v1, SIMD_type v2) {
1359
+ return simd_sll_2(v1, v2);
1360
+ }
1361
+ #endif
1362
+
1363
+ #ifndef simd_sll_2_xh
1364
+ inline SIMD_type simd_sll_2_xh(SIMD_type v1, SIMD_type v2) {
1365
+ return simd_sll_2(v1, simd_srli_16(v2, 1));
1366
+ }
1367
+ #endif
1368
+
1369
+ #ifndef simd_sll_2_lx
1370
+ inline SIMD_type simd_sll_2_lx(SIMD_type v1, SIMD_type v2) {
1371
+ return simd_sll_2(simd_andc(v1, simd_himask_2), v2);
1372
+ }
1373
+ #endif
1374
+
1375
+ #ifndef simd_sll_2_ll
1376
+ inline SIMD_type simd_sll_2_ll(SIMD_type v1, SIMD_type v2) {
1377
+ return simd_sll_2(simd_andc(v1, simd_himask_2), v2);
1378
+ }
1379
+ #endif
1380
+
1381
+ #ifndef simd_sll_2_lh
1382
+ inline SIMD_type simd_sll_2_lh(SIMD_type v1, SIMD_type v2) {
1383
+ return simd_sll_2(simd_andc(v1, simd_himask_2), simd_srli_16(v2, 1));
1384
+ }
1385
+ #endif
1386
+
1387
+ #ifndef simd_sll_2_hx
1388
+ inline SIMD_type simd_sll_2_hx(SIMD_type v1, SIMD_type v2) {
1389
+ return simd_sll_2(simd_srli_2(v1, 1), v2);
1390
+ }
1391
+ #endif
1392
+
1393
+ #ifndef simd_sll_2_hl
1394
+ inline SIMD_type simd_sll_2_hl(SIMD_type v1, SIMD_type v2) {
1395
+ return simd_sll_2(simd_srli_2(v1, 1), v2);
1396
+ }
1397
+ #endif
1398
+
1399
+ #ifndef simd_sll_2_hh
1400
+ inline SIMD_type simd_sll_2_hh(SIMD_type v1, SIMD_type v2) {
1401
+ return simd_sll_2(simd_srli_2(v1, 1), simd_srli_16(v2, 1));
1402
+ }
1403
+ #endif
1404
+
1405
+ #ifndef simd_sll_4_xx
1406
+ inline SIMD_type simd_sll_4_xx(SIMD_type v1, SIMD_type v2) {
1407
+ return simd_sll_4(v1, v2);
1408
+ }
1409
+ #endif
1410
+
1411
+ #ifndef simd_sll_4_xl
1412
+ inline SIMD_type simd_sll_4_xl(SIMD_type v1, SIMD_type v2) {
1413
+ return simd_sll_4(v1, v2);
1414
+ }
1415
+ #endif
1416
+
1417
+ #ifndef simd_sll_4_xh
1418
+ inline SIMD_type simd_sll_4_xh(SIMD_type v1, SIMD_type v2) {
1419
+ return simd_sll_4(v1, simd_srli_16(v2, 2));
1420
+ }
1421
+ #endif
1422
+
1423
+ #ifndef simd_sll_4_lx
1424
+ inline SIMD_type simd_sll_4_lx(SIMD_type v1, SIMD_type v2) {
1425
+ return simd_sll_4(simd_andc(v1, simd_himask_4), v2);
1426
+ }
1427
+ #endif
1428
+
1429
+ #ifndef simd_sll_4_ll
1430
+ inline SIMD_type simd_sll_4_ll(SIMD_type v1, SIMD_type v2) {
1431
+ return simd_sll_4(simd_andc(v1, simd_himask_4), v2);
1432
+ }
1433
+ #endif
1434
+
1435
+ #ifndef simd_sll_4_lh
1436
+ inline SIMD_type simd_sll_4_lh(SIMD_type v1, SIMD_type v2) {
1437
+ return simd_sll_4(simd_andc(v1, simd_himask_4), simd_srli_16(v2, 2));
1438
+ }
1439
+ #endif
1440
+
1441
+ #ifndef simd_sll_4_hx
1442
+ inline SIMD_type simd_sll_4_hx(SIMD_type v1, SIMD_type v2) {
1443
+ return simd_sll_4(simd_srli_4(v1, 2), v2);
1444
+ }
1445
+ #endif
1446
+
1447
+ #ifndef simd_sll_4_hl
1448
+ inline SIMD_type simd_sll_4_hl(SIMD_type v1, SIMD_type v2) {
1449
+ return simd_sll_4(simd_srli_4(v1, 2), v2);
1450
+ }
1451
+ #endif
1452
+
1453
+ #ifndef simd_sll_4_hh
1454
+ inline SIMD_type simd_sll_4_hh(SIMD_type v1, SIMD_type v2) {
1455
+ return simd_sll_4(simd_srli_4(v1, 2), simd_srli_16(v2, 2));
1456
+ }
1457
+ #endif
1458
+
1459
+ #ifndef simd_sll_8_xx
1460
+ inline SIMD_type simd_sll_8_xx(SIMD_type v1, SIMD_type v2) {
1461
+ return simd_sll_8(v1, v2);
1462
+ }
1463
+ #endif
1464
+
1465
+ #ifndef simd_sll_8_xl
1466
+ inline SIMD_type simd_sll_8_xl(SIMD_type v1, SIMD_type v2) {
1467
+ return simd_sll_8(v1, v2);
1468
+ }
1469
+ #endif
1470
+
1471
+ #ifndef simd_sll_8_xh
1472
+ inline SIMD_type simd_sll_8_xh(SIMD_type v1, SIMD_type v2) {
1473
+ return simd_sll_8(v1, simd_srli_16(v2, 4));
1474
+ }
1475
+ #endif
1476
+
1477
+ #ifndef simd_sll_8_lx
1478
+ inline SIMD_type simd_sll_8_lx(SIMD_type v1, SIMD_type v2) {
1479
+ return simd_sll_8(simd_andc(v1, simd_himask_8), v2);
1480
+ }
1481
+ #endif
1482
+
1483
+ #ifndef simd_sll_8_ll
1484
+ inline SIMD_type simd_sll_8_ll(SIMD_type v1, SIMD_type v2) {
1485
+ return simd_sll_8(simd_andc(v1, simd_himask_8), v2);
1486
+ }
1487
+ #endif
1488
+
1489
+ #ifndef simd_sll_8_lh
1490
+ inline SIMD_type simd_sll_8_lh(SIMD_type v1, SIMD_type v2) {
1491
+ return simd_sll_8(simd_andc(v1, simd_himask_8), simd_srli_16(v2, 4));
1492
+ }
1493
+ #endif
1494
+
1495
+ #ifndef simd_sll_8_hx
1496
+ inline SIMD_type simd_sll_8_hx(SIMD_type v1, SIMD_type v2) {
1497
+ return simd_sll_8(simd_srli_8(v1, 4), v2);
1498
+ }
1499
+ #endif
1500
+
1501
+ #ifndef simd_sll_8_hl
1502
+ inline SIMD_type simd_sll_8_hl(SIMD_type v1, SIMD_type v2) {
1503
+ return simd_sll_8(simd_srli_8(v1, 4), v2);
1504
+ }
1505
+ #endif
1506
+
1507
+ #ifndef simd_sll_8_hh
1508
+ inline SIMD_type simd_sll_8_hh(SIMD_type v1, SIMD_type v2) {
1509
+ return simd_sll_8(simd_srli_8(v1, 4), simd_srli_16(v2, 4));
1510
+ }
1511
+ #endif
1512
+
1513
+ #ifndef simd_sll_16_xx
1514
+ inline SIMD_type simd_sll_16_xx(SIMD_type v1, SIMD_type v2) {
1515
+ return simd_sll_16(v1, v2);
1516
+ }
1517
+ #endif
1518
+
1519
+ #ifndef simd_sll_16_xl
1520
+ inline SIMD_type simd_sll_16_xl(SIMD_type v1, SIMD_type v2) {
1521
+ return simd_sll_16(v1, v2);
1522
+ }
1523
+ #endif
1524
+
1525
+ #ifndef simd_sll_16_xh
1526
+ inline SIMD_type simd_sll_16_xh(SIMD_type v1, SIMD_type v2) {
1527
+ return simd_sll_16(v1, simd_srli_16(v2, 8));
1528
+ }
1529
+ #endif
1530
+
1531
+ #ifndef simd_sll_16_lx
1532
+ inline SIMD_type simd_sll_16_lx(SIMD_type v1, SIMD_type v2) {
1533
+ return simd_sll_16(simd_andc(v1, simd_himask_16), v2);
1534
+ }
1535
+ #endif
1536
+
1537
+ #ifndef simd_sll_16_ll
1538
+ inline SIMD_type simd_sll_16_ll(SIMD_type v1, SIMD_type v2) {
1539
+ return simd_sll_16(simd_andc(v1, simd_himask_16), v2);
1540
+ }
1541
+ #endif
1542
+
1543
+ #ifndef simd_sll_16_lh
1544
+ inline SIMD_type simd_sll_16_lh(SIMD_type v1, SIMD_type v2) {
1545
+ return simd_sll_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
1546
+ }
1547
+ #endif
1548
+
1549
+ #ifndef simd_sll_16_hx
1550
+ inline SIMD_type simd_sll_16_hx(SIMD_type v1, SIMD_type v2) {
1551
+ return simd_sll_16(simd_srli_16(v1, 8), v2);
1552
+ }
1553
+ #endif
1554
+
1555
+ #ifndef simd_sll_16_hl
1556
+ inline SIMD_type simd_sll_16_hl(SIMD_type v1, SIMD_type v2) {
1557
+ return simd_sll_16(simd_srli_16(v1, 8), v2);
1558
+ }
1559
+ #endif
1560
+
1561
+ #ifndef simd_sll_16_hh
1562
+ inline SIMD_type simd_sll_16_hh(SIMD_type v1, SIMD_type v2) {
1563
+ return simd_sll_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
1564
+ }
1565
+ #endif
1566
+
1567
+ #ifndef simd_sll_32_xx
1568
+ inline SIMD_type simd_sll_32_xx(SIMD_type v1, SIMD_type v2) {
1569
+ return simd_sll_32(v1, v2);
1570
+ }
1571
+ #endif
1572
+
1573
+ #ifndef simd_sll_32_xl
1574
+ inline SIMD_type simd_sll_32_xl(SIMD_type v1, SIMD_type v2) {
1575
+ return simd_sll_32(v1, v2);
1576
+ }
1577
+ #endif
1578
+
1579
+ #ifndef simd_sll_32_xh
1580
+ inline SIMD_type simd_sll_32_xh(SIMD_type v1, SIMD_type v2) {
1581
+ return simd_sll_32(v1, simd_srli_32(v2, 16));
1582
+ }
1583
+ #endif
1584
+
1585
+ #ifndef simd_sll_32_lx
1586
+ inline SIMD_type simd_sll_32_lx(SIMD_type v1, SIMD_type v2) {
1587
+ return simd_sll_32(simd_andc(v1, simd_himask_32), v2);
1588
+ }
1589
+ #endif
1590
+
1591
+ #ifndef simd_sll_32_ll
1592
+ inline SIMD_type simd_sll_32_ll(SIMD_type v1, SIMD_type v2) {
1593
+ return simd_sll_32(simd_andc(v1, simd_himask_32), v2);
1594
+ }
1595
+ #endif
1596
+
1597
+ #ifndef simd_sll_32_lh
1598
+ inline SIMD_type simd_sll_32_lh(SIMD_type v1, SIMD_type v2) {
1599
+ return simd_sll_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
1600
+ }
1601
+ #endif
1602
+
1603
+ #ifndef simd_sll_32_hx
1604
+ inline SIMD_type simd_sll_32_hx(SIMD_type v1, SIMD_type v2) {
1605
+ return simd_sll_32(simd_srli_32(v1, 16), v2);
1606
+ }
1607
+ #endif
1608
+
1609
+ #ifndef simd_sll_32_hl
1610
+ inline SIMD_type simd_sll_32_hl(SIMD_type v1, SIMD_type v2) {
1611
+ return simd_sll_32(simd_srli_32(v1, 16), v2);
1612
+ }
1613
+ #endif
1614
+
1615
+ #ifndef simd_sll_32_hh
1616
+ inline SIMD_type simd_sll_32_hh(SIMD_type v1, SIMD_type v2) {
1617
+ return simd_sll_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
1618
+ }
1619
+ #endif
1620
+
1621
+ #ifndef simd_srl_2_xx
1622
+ inline SIMD_type simd_srl_2_xx(SIMD_type v1, SIMD_type v2) {
1623
+ return simd_srl_2(v1, v2);
1624
+ }
1625
+ #endif
1626
+
1627
+ #ifndef simd_srl_2_xl
1628
+ inline SIMD_type simd_srl_2_xl(SIMD_type v1, SIMD_type v2) {
1629
+ return simd_srl_2(v1, v2);
1630
+ }
1631
+ #endif
1632
+
1633
+ #ifndef simd_srl_2_xh
1634
+ inline SIMD_type simd_srl_2_xh(SIMD_type v1, SIMD_type v2) {
1635
+ return simd_srl_2(v1, simd_srli_16(v2, 1));
1636
+ }
1637
+ #endif
1638
+
1639
+ #ifndef simd_srl_2_lx
1640
+ inline SIMD_type simd_srl_2_lx(SIMD_type v1, SIMD_type v2) {
1641
+ return simd_srl_2(simd_andc(v1, simd_himask_2), v2);
1642
+ }
1643
+ #endif
1644
+
1645
+ #ifndef simd_srl_2_ll
1646
+ inline SIMD_type simd_srl_2_ll(SIMD_type v1, SIMD_type v2) {
1647
+ return simd_srl_2(simd_andc(v1, simd_himask_2), v2);
1648
+ }
1649
+ #endif
1650
+
1651
+ #ifndef simd_srl_2_lh
1652
+ inline SIMD_type simd_srl_2_lh(SIMD_type v1, SIMD_type v2) {
1653
+ return simd_srl_2(simd_andc(v1, simd_himask_2), simd_srli_16(v2, 1));
1654
+ }
1655
+ #endif
1656
+
1657
+ #ifndef simd_srl_2_hx
1658
+ inline SIMD_type simd_srl_2_hx(SIMD_type v1, SIMD_type v2) {
1659
+ return simd_srl_2(simd_srli_2(v1, 1), v2);
1660
+ }
1661
+ #endif
1662
+
1663
+ #ifndef simd_srl_2_hl
1664
+ inline SIMD_type simd_srl_2_hl(SIMD_type v1, SIMD_type v2) {
1665
+ return simd_srl_2(simd_srli_2(v1, 1), v2);
1666
+ }
1667
+ #endif
1668
+
1669
+ #ifndef simd_srl_2_hh
1670
+ inline SIMD_type simd_srl_2_hh(SIMD_type v1, SIMD_type v2) {
1671
+ return simd_srl_2(simd_srli_2(v1, 1), simd_srli_16(v2, 1));
1672
+ }
1673
+ #endif
1674
+
1675
+ #ifndef simd_srl_4_xx
1676
+ inline SIMD_type simd_srl_4_xx(SIMD_type v1, SIMD_type v2) {
1677
+ return simd_srl_4(v1, v2);
1678
+ }
1679
+ #endif
1680
+
1681
+ #ifndef simd_srl_4_xl
1682
+ inline SIMD_type simd_srl_4_xl(SIMD_type v1, SIMD_type v2) {
1683
+ return simd_srl_4(v1, v2);
1684
+ }
1685
+ #endif
1686
+
1687
+ #ifndef simd_srl_4_xh
1688
+ inline SIMD_type simd_srl_4_xh(SIMD_type v1, SIMD_type v2) {
1689
+ return simd_srl_4(v1, simd_srli_16(v2, 2));
1690
+ }
1691
+ #endif
1692
+
1693
+ #ifndef simd_srl_4_lx
1694
+ inline SIMD_type simd_srl_4_lx(SIMD_type v1, SIMD_type v2) {
1695
+ return simd_srl_4(simd_andc(v1, simd_himask_4), v2);
1696
+ }
1697
+ #endif
1698
+
1699
+ #ifndef simd_srl_4_ll
1700
+ inline SIMD_type simd_srl_4_ll(SIMD_type v1, SIMD_type v2) {
1701
+ return simd_srl_4(simd_andc(v1, simd_himask_4), v2);
1702
+ }
1703
+ #endif
1704
+
1705
+ #ifndef simd_srl_4_lh
1706
+ inline SIMD_type simd_srl_4_lh(SIMD_type v1, SIMD_type v2) {
1707
+ return simd_srl_4(simd_andc(v1, simd_himask_4), simd_srli_16(v2, 2));
1708
+ }
1709
+ #endif
1710
+
1711
+ #ifndef simd_srl_4_hx
1712
+ inline SIMD_type simd_srl_4_hx(SIMD_type v1, SIMD_type v2) {
1713
+ return simd_srl_4(simd_srli_4(v1, 2), v2);
1714
+ }
1715
+ #endif
1716
+
1717
+ #ifndef simd_srl_4_hl
1718
+ inline SIMD_type simd_srl_4_hl(SIMD_type v1, SIMD_type v2) {
1719
+ return simd_srl_4(simd_srli_4(v1, 2), v2);
1720
+ }
1721
+ #endif
1722
+
1723
+ #ifndef simd_srl_4_hh
1724
+ inline SIMD_type simd_srl_4_hh(SIMD_type v1, SIMD_type v2) {
1725
+ return simd_srl_4(simd_srli_4(v1, 2), simd_srli_16(v2, 2));
1726
+ }
1727
+ #endif
1728
+
1729
+ #ifndef simd_srl_8_xx
1730
+ inline SIMD_type simd_srl_8_xx(SIMD_type v1, SIMD_type v2) {
1731
+ return simd_srl_8(v1, v2);
1732
+ }
1733
+ #endif
1734
+
1735
+ #ifndef simd_srl_8_xl
1736
+ inline SIMD_type simd_srl_8_xl(SIMD_type v1, SIMD_type v2) {
1737
+ return simd_srl_8(v1, v2);
1738
+ }
1739
+ #endif
1740
+
1741
+ #ifndef simd_srl_8_xh
1742
+ inline SIMD_type simd_srl_8_xh(SIMD_type v1, SIMD_type v2) {
1743
+ return simd_srl_8(v1, simd_srli_16(v2, 4));
1744
+ }
1745
+ #endif
1746
+
1747
+ #ifndef simd_srl_8_lx
1748
+ inline SIMD_type simd_srl_8_lx(SIMD_type v1, SIMD_type v2) {
1749
+ return simd_srl_8(simd_andc(v1, simd_himask_8), v2);
1750
+ }
1751
+ #endif
1752
+
1753
+ #ifndef simd_srl_8_ll
1754
+ inline SIMD_type simd_srl_8_ll(SIMD_type v1, SIMD_type v2) {
1755
+ return simd_srl_8(simd_andc(v1, simd_himask_8), v2);
1756
+ }
1757
+ #endif
1758
+
1759
+ #ifndef simd_srl_8_lh
1760
+ inline SIMD_type simd_srl_8_lh(SIMD_type v1, SIMD_type v2) {
1761
+ return simd_srl_8(simd_andc(v1, simd_himask_8), simd_srli_16(v2, 4));
1762
+ }
1763
+ #endif
1764
+
1765
+ #ifndef simd_srl_8_hx
1766
+ inline SIMD_type simd_srl_8_hx(SIMD_type v1, SIMD_type v2) {
1767
+ return simd_srl_8(simd_srli_8(v1, 4), v2);
1768
+ }
1769
+ #endif
1770
+
1771
+ #ifndef simd_srl_8_hl
1772
+ inline SIMD_type simd_srl_8_hl(SIMD_type v1, SIMD_type v2) {
1773
+ return simd_srl_8(simd_srli_8(v1, 4), v2);
1774
+ }
1775
+ #endif
1776
+
1777
+ #ifndef simd_srl_8_hh
1778
+ inline SIMD_type simd_srl_8_hh(SIMD_type v1, SIMD_type v2) {
1779
+ return simd_srl_8(simd_srli_8(v1, 4), simd_srli_16(v2, 4));
1780
+ }
1781
+ #endif
1782
+
1783
+ #ifndef simd_srl_16_xx
1784
+ inline SIMD_type simd_srl_16_xx(SIMD_type v1, SIMD_type v2) {
1785
+ return simd_srl_16(v1, v2);
1786
+ }
1787
+ #endif
1788
+
1789
+ #ifndef simd_srl_16_xl
1790
+ inline SIMD_type simd_srl_16_xl(SIMD_type v1, SIMD_type v2) {
1791
+ return simd_srl_16(v1, v2);
1792
+ }
1793
+ #endif
1794
+
1795
+ #ifndef simd_srl_16_xh
1796
+ inline SIMD_type simd_srl_16_xh(SIMD_type v1, SIMD_type v2) {
1797
+ return simd_srl_16(v1, simd_srli_16(v2, 8));
1798
+ }
1799
+ #endif
1800
+
1801
+ #ifndef simd_srl_16_lx
1802
+ inline SIMD_type simd_srl_16_lx(SIMD_type v1, SIMD_type v2) {
1803
+ return simd_srl_16(simd_andc(v1, simd_himask_16), v2);
1804
+ }
1805
+ #endif
1806
+
1807
+ #ifndef simd_srl_16_ll
1808
+ inline SIMD_type simd_srl_16_ll(SIMD_type v1, SIMD_type v2) {
1809
+ return simd_srl_16(simd_andc(v1, simd_himask_16), v2);
1810
+ }
1811
+ #endif
1812
+
1813
+ #ifndef simd_srl_16_lh
1814
+ inline SIMD_type simd_srl_16_lh(SIMD_type v1, SIMD_type v2) {
1815
+ return simd_srl_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
1816
+ }
1817
+ #endif
1818
+
1819
+ #ifndef simd_srl_16_hx
1820
+ inline SIMD_type simd_srl_16_hx(SIMD_type v1, SIMD_type v2) {
1821
+ return simd_srl_16(simd_srli_16(v1, 8), v2);
1822
+ }
1823
+ #endif
1824
+
1825
+ #ifndef simd_srl_16_hl
1826
+ inline SIMD_type simd_srl_16_hl(SIMD_type v1, SIMD_type v2) {
1827
+ return simd_srl_16(simd_srli_16(v1, 8), v2);
1828
+ }
1829
+ #endif
1830
+
1831
+ #ifndef simd_srl_16_hh
1832
+ inline SIMD_type simd_srl_16_hh(SIMD_type v1, SIMD_type v2) {
1833
+ return simd_srl_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
1834
+ }
1835
+ #endif
1836
+
1837
+ #ifndef simd_srl_32_xx
1838
+ inline SIMD_type simd_srl_32_xx(SIMD_type v1, SIMD_type v2) {
1839
+ return simd_srl_32(v1, v2);
1840
+ }
1841
+ #endif
1842
+
1843
+ #ifndef simd_srl_32_xl
1844
+ inline SIMD_type simd_srl_32_xl(SIMD_type v1, SIMD_type v2) {
1845
+ return simd_srl_32(v1, v2);
1846
+ }
1847
+ #endif
1848
+
1849
+ #ifndef simd_srl_32_xh
1850
+ inline SIMD_type simd_srl_32_xh(SIMD_type v1, SIMD_type v2) {
1851
+ return simd_srl_32(v1, simd_srli_32(v2, 16));
1852
+ }
1853
+ #endif
1854
+
1855
+ #ifndef simd_srl_32_lx
1856
+ inline SIMD_type simd_srl_32_lx(SIMD_type v1, SIMD_type v2) {
1857
+ return simd_srl_32(simd_andc(v1, simd_himask_32), v2);
1858
+ }
1859
+ #endif
1860
+
1861
+ #ifndef simd_srl_32_ll
1862
+ inline SIMD_type simd_srl_32_ll(SIMD_type v1, SIMD_type v2) {
1863
+ return simd_srl_32(simd_andc(v1, simd_himask_32), v2);
1864
+ }
1865
+ #endif
1866
+
1867
+ #ifndef simd_srl_32_lh
1868
+ inline SIMD_type simd_srl_32_lh(SIMD_type v1, SIMD_type v2) {
1869
+ return simd_srl_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
1870
+ }
1871
+ #endif
1872
+
1873
+ #ifndef simd_srl_32_hx
1874
+ inline SIMD_type simd_srl_32_hx(SIMD_type v1, SIMD_type v2) {
1875
+ return simd_srl_32(simd_srli_32(v1, 16), v2);
1876
+ }
1877
+ #endif
1878
+
1879
+ #ifndef simd_srl_32_hl
1880
+ inline SIMD_type simd_srl_32_hl(SIMD_type v1, SIMD_type v2) {
1881
+ return simd_srl_32(simd_srli_32(v1, 16), v2);
1882
+ }
1883
+ #endif
1884
+
1885
+ #ifndef simd_srl_32_hh
1886
+ inline SIMD_type simd_srl_32_hh(SIMD_type v1, SIMD_type v2) {
1887
+ return simd_srl_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
1888
+ }
1889
+ #endif
1890
+
1891
+ #ifndef simd_sra_2_xx
1892
+ inline SIMD_type simd_sra_2_xx(SIMD_type v1, SIMD_type v2) {
1893
+ return simd_sra_2(v1, v2);
1894
+ }
1895
+ #endif
1896
+
1897
+ #ifndef simd_sra_2_xl
1898
+ inline SIMD_type simd_sra_2_xl(SIMD_type v1, SIMD_type v2) {
1899
+ return simd_sra_2(v1, v2);
1900
+ }
1901
+ #endif
1902
+
1903
+ #ifndef simd_sra_2_xh
1904
+ inline SIMD_type simd_sra_2_xh(SIMD_type v1, SIMD_type v2) {
1905
+ return simd_sra_2(v1, simd_srli_16(v2, 1));
1906
+ }
1907
+ #endif
1908
+
1909
+ #ifndef simd_sra_2_lx
1910
+ inline SIMD_type simd_sra_2_lx(SIMD_type v1, SIMD_type v2) {
1911
+ return simd_sra_2(simd_andc(v1, simd_himask_2), v2);
1912
+ }
1913
+ #endif
1914
+
1915
+ #ifndef simd_sra_2_ll
1916
+ inline SIMD_type simd_sra_2_ll(SIMD_type v1, SIMD_type v2) {
1917
+ return simd_sra_2(simd_andc(v1, simd_himask_2), v2);
1918
+ }
1919
+ #endif
1920
+
1921
+ #ifndef simd_sra_2_lh
1922
+ inline SIMD_type simd_sra_2_lh(SIMD_type v1, SIMD_type v2) {
1923
+ return simd_sra_2(simd_andc(v1, simd_himask_2), simd_srli_16(v2, 1));
1924
+ }
1925
+ #endif
1926
+
1927
+ #ifndef simd_sra_2_hx
1928
+ inline SIMD_type simd_sra_2_hx(SIMD_type v1, SIMD_type v2) {
1929
+ return simd_sra_2(simd_srli_2(v1, 1), v2);
1930
+ }
1931
+ #endif
1932
+
1933
+ #ifndef simd_sra_2_hl
1934
+ inline SIMD_type simd_sra_2_hl(SIMD_type v1, SIMD_type v2) {
1935
+ return simd_sra_2(simd_srli_2(v1, 1), v2);
1936
+ }
1937
+ #endif
1938
+
1939
+ #ifndef simd_sra_2_hh
1940
+ inline SIMD_type simd_sra_2_hh(SIMD_type v1, SIMD_type v2) {
1941
+ return simd_sra_2(simd_srli_2(v1, 1), simd_srli_16(v2, 1));
1942
+ }
1943
+ #endif
1944
+
1945
+ #ifndef simd_sra_4_xx
1946
+ inline SIMD_type simd_sra_4_xx(SIMD_type v1, SIMD_type v2) {
1947
+ return simd_sra_4(v1, v2);
1948
+ }
1949
+ #endif
1950
+
1951
+ #ifndef simd_sra_4_xl
1952
+ inline SIMD_type simd_sra_4_xl(SIMD_type v1, SIMD_type v2) {
1953
+ return simd_sra_4(v1, v2);
1954
+ }
1955
+ #endif
1956
+
1957
+ #ifndef simd_sra_4_xh
1958
+ inline SIMD_type simd_sra_4_xh(SIMD_type v1, SIMD_type v2) {
1959
+ return simd_sra_4(v1, simd_srli_16(v2, 2));
1960
+ }
1961
+ #endif
1962
+
1963
+ #ifndef simd_sra_4_lx
1964
+ inline SIMD_type simd_sra_4_lx(SIMD_type v1, SIMD_type v2) {
1965
+ return simd_sra_4(simd_andc(v1, simd_himask_4), v2);
1966
+ }
1967
+ #endif
1968
+
1969
+ #ifndef simd_sra_4_ll
1970
+ inline SIMD_type simd_sra_4_ll(SIMD_type v1, SIMD_type v2) {
1971
+ return simd_sra_4(simd_andc(v1, simd_himask_4), v2);
1972
+ }
1973
+ #endif
1974
+
1975
+ #ifndef simd_sra_4_lh
1976
+ inline SIMD_type simd_sra_4_lh(SIMD_type v1, SIMD_type v2) {
1977
+ return simd_sra_4(simd_andc(v1, simd_himask_4), simd_srli_16(v2, 2));
1978
+ }
1979
+ #endif
1980
+
1981
+ #ifndef simd_sra_4_hx
1982
+ inline SIMD_type simd_sra_4_hx(SIMD_type v1, SIMD_type v2) {
1983
+ return simd_sra_4(simd_srli_4(v1, 2), v2);
1984
+ }
1985
+ #endif
1986
+
1987
+ #ifndef simd_sra_4_hl
1988
+ inline SIMD_type simd_sra_4_hl(SIMD_type v1, SIMD_type v2) {
1989
+ return simd_sra_4(simd_srli_4(v1, 2), v2);
1990
+ }
1991
+ #endif
1992
+
1993
+ #ifndef simd_sra_4_hh
1994
+ inline SIMD_type simd_sra_4_hh(SIMD_type v1, SIMD_type v2) {
1995
+ return simd_sra_4(simd_srli_4(v1, 2), simd_srli_16(v2, 2));
1996
+ }
1997
+ #endif
1998
+
1999
+ #ifndef simd_sra_8_xx
2000
+ inline SIMD_type simd_sra_8_xx(SIMD_type v1, SIMD_type v2) {
2001
+ return simd_sra_8(v1, v2);
2002
+ }
2003
+ #endif
2004
+
2005
+ #ifndef simd_sra_8_xl
2006
+ inline SIMD_type simd_sra_8_xl(SIMD_type v1, SIMD_type v2) {
2007
+ return simd_sra_8(v1, v2);
2008
+ }
2009
+ #endif
2010
+
2011
+ #ifndef simd_sra_8_xh
2012
+ inline SIMD_type simd_sra_8_xh(SIMD_type v1, SIMD_type v2) {
2013
+ return simd_sra_8(v1, simd_srli_16(v2, 4));
2014
+ }
2015
+ #endif
2016
+
2017
+ #ifndef simd_sra_8_lx
2018
+ inline SIMD_type simd_sra_8_lx(SIMD_type v1, SIMD_type v2) {
2019
+ return simd_sra_8(simd_andc(v1, simd_himask_8), v2);
2020
+ }
2021
+ #endif
2022
+
2023
+ #ifndef simd_sra_8_ll
2024
+ inline SIMD_type simd_sra_8_ll(SIMD_type v1, SIMD_type v2) {
2025
+ return simd_sra_8(simd_andc(v1, simd_himask_8), v2);
2026
+ }
2027
+ #endif
2028
+
2029
+ #ifndef simd_sra_8_lh
2030
+ inline SIMD_type simd_sra_8_lh(SIMD_type v1, SIMD_type v2) {
2031
+ return simd_sra_8(simd_andc(v1, simd_himask_8), simd_srli_16(v2, 4));
2032
+ }
2033
+ #endif
2034
+
2035
+ #ifndef simd_sra_8_hx
2036
+ inline SIMD_type simd_sra_8_hx(SIMD_type v1, SIMD_type v2) {
2037
+ return simd_sra_8(simd_srli_8(v1, 4), v2);
2038
+ }
2039
+ #endif
2040
+
2041
+ #ifndef simd_sra_8_hl
2042
+ inline SIMD_type simd_sra_8_hl(SIMD_type v1, SIMD_type v2) {
2043
+ return simd_sra_8(simd_srli_8(v1, 4), v2);
2044
+ }
2045
+ #endif
2046
+
2047
+ #ifndef simd_sra_8_hh
2048
+ inline SIMD_type simd_sra_8_hh(SIMD_type v1, SIMD_type v2) {
2049
+ return simd_sra_8(simd_srli_8(v1, 4), simd_srli_16(v2, 4));
2050
+ }
2051
+ #endif
2052
+
2053
+ #ifndef simd_sra_16_xx
2054
+ inline SIMD_type simd_sra_16_xx(SIMD_type v1, SIMD_type v2) {
2055
+ return simd_sra_16(v1, v2);
2056
+ }
2057
+ #endif
2058
+
2059
+ #ifndef simd_sra_16_xl
2060
+ inline SIMD_type simd_sra_16_xl(SIMD_type v1, SIMD_type v2) {
2061
+ return simd_sra_16(v1, v2);
2062
+ }
2063
+ #endif
2064
+
2065
+ #ifndef simd_sra_16_xh
2066
+ inline SIMD_type simd_sra_16_xh(SIMD_type v1, SIMD_type v2) {
2067
+ return simd_sra_16(v1, simd_srli_16(v2, 8));
2068
+ }
2069
+ #endif
2070
+
2071
+ #ifndef simd_sra_16_lx
2072
+ inline SIMD_type simd_sra_16_lx(SIMD_type v1, SIMD_type v2) {
2073
+ return simd_sra_16(simd_andc(v1, simd_himask_16), v2);
2074
+ }
2075
+ #endif
2076
+
2077
+ #ifndef simd_sra_16_ll
2078
+ inline SIMD_type simd_sra_16_ll(SIMD_type v1, SIMD_type v2) {
2079
+ return simd_sra_16(simd_andc(v1, simd_himask_16), v2);
2080
+ }
2081
+ #endif
2082
+
2083
+ #ifndef simd_sra_16_lh
2084
+ inline SIMD_type simd_sra_16_lh(SIMD_type v1, SIMD_type v2) {
2085
+ return simd_sra_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
2086
+ }
2087
+ #endif
2088
+
2089
+ #ifndef simd_sra_16_hx
2090
+ inline SIMD_type simd_sra_16_hx(SIMD_type v1, SIMD_type v2) {
2091
+ return simd_sra_16(simd_srli_16(v1, 8), v2);
2092
+ }
2093
+ #endif
2094
+
2095
+ #ifndef simd_sra_16_hl
2096
+ inline SIMD_type simd_sra_16_hl(SIMD_type v1, SIMD_type v2) {
2097
+ return simd_sra_16(simd_srli_16(v1, 8), v2);
2098
+ }
2099
+ #endif
2100
+
2101
+ #ifndef simd_sra_16_hh
2102
+ inline SIMD_type simd_sra_16_hh(SIMD_type v1, SIMD_type v2) {
2103
+ return simd_sra_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
2104
+ }
2105
+ #endif
2106
+
2107
+ #ifndef simd_sra_32_xx
2108
+ inline SIMD_type simd_sra_32_xx(SIMD_type v1, SIMD_type v2) {
2109
+ return simd_sra_32(v1, v2);
2110
+ }
2111
+ #endif
2112
+
2113
+ #ifndef simd_sra_32_xl
2114
+ inline SIMD_type simd_sra_32_xl(SIMD_type v1, SIMD_type v2) {
2115
+ return simd_sra_32(v1, v2);
2116
+ }
2117
+ #endif
2118
+
2119
+ #ifndef simd_sra_32_xh
2120
+ inline SIMD_type simd_sra_32_xh(SIMD_type v1, SIMD_type v2) {
2121
+ return simd_sra_32(v1, simd_srli_32(v2, 16));
2122
+ }
2123
+ #endif
2124
+
2125
+ #ifndef simd_sra_32_lx
2126
+ inline SIMD_type simd_sra_32_lx(SIMD_type v1, SIMD_type v2) {
2127
+ return simd_sra_32(simd_andc(v1, simd_himask_32), v2);
2128
+ }
2129
+ #endif
2130
+
2131
+ #ifndef simd_sra_32_ll
2132
+ inline SIMD_type simd_sra_32_ll(SIMD_type v1, SIMD_type v2) {
2133
+ return simd_sra_32(simd_andc(v1, simd_himask_32), v2);
2134
+ }
2135
+ #endif
2136
+
2137
+ #ifndef simd_sra_32_lh
2138
+ inline SIMD_type simd_sra_32_lh(SIMD_type v1, SIMD_type v2) {
2139
+ return simd_sra_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
2140
+ }
2141
+ #endif
2142
+
2143
+ #ifndef simd_sra_32_hx
2144
+ inline SIMD_type simd_sra_32_hx(SIMD_type v1, SIMD_type v2) {
2145
+ return simd_sra_32(simd_srli_32(v1, 16), v2);
2146
+ }
2147
+ #endif
2148
+
2149
+ #ifndef simd_sra_32_hl
2150
+ inline SIMD_type simd_sra_32_hl(SIMD_type v1, SIMD_type v2) {
2151
+ return simd_sra_32(simd_srli_32(v1, 16), v2);
2152
+ }
2153
+ #endif
2154
+
2155
+ #ifndef simd_sra_32_hh
2156
+ inline SIMD_type simd_sra_32_hh(SIMD_type v1, SIMD_type v2) {
2157
+ return simd_sra_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
2158
+ }
2159
+ #endif
2160
+
2161
+ #ifndef simd_rotl_2_xx
2162
+ inline SIMD_type simd_rotl_2_xx(SIMD_type v1, SIMD_type v2) {
2163
+ return simd_rotl_2(v1, v2);
2164
+ }
2165
+ #endif
2166
+
2167
+ #ifndef simd_rotl_2_xl
2168
+ inline SIMD_type simd_rotl_2_xl(SIMD_type v1, SIMD_type v2) {
2169
+ return simd_rotl_2(v1, v2);
2170
+ }
2171
+ #endif
2172
+
2173
+ #ifndef simd_rotl_2_xh
2174
+ inline SIMD_type simd_rotl_2_xh(SIMD_type v1, SIMD_type v2) {
2175
+ return simd_rotl_2(v1, simd_srli_16(v2, 1));
2176
+ }
2177
+ #endif
2178
+
2179
+ #ifndef simd_rotl_2_lx
2180
+ inline SIMD_type simd_rotl_2_lx(SIMD_type v1, SIMD_type v2) {
2181
+ return simd_rotl_2(simd_andc(v1, simd_himask_2), v2);
2182
+ }
2183
+ #endif
2184
+
2185
+ #ifndef simd_rotl_2_ll
2186
+ inline SIMD_type simd_rotl_2_ll(SIMD_type v1, SIMD_type v2) {
2187
+ return simd_rotl_2(simd_andc(v1, simd_himask_2), v2);
2188
+ }
2189
+ #endif
2190
+
2191
+ #ifndef simd_rotl_2_lh
2192
+ inline SIMD_type simd_rotl_2_lh(SIMD_type v1, SIMD_type v2) {
2193
+ return simd_rotl_2(simd_andc(v1, simd_himask_2), simd_srli_16(v2, 1));
2194
+ }
2195
+ #endif
2196
+
2197
+ #ifndef simd_rotl_2_hx
2198
+ inline SIMD_type simd_rotl_2_hx(SIMD_type v1, SIMD_type v2) {
2199
+ return simd_rotl_2(simd_srli_2(v1, 1), v2);
2200
+ }
2201
+ #endif
2202
+
2203
+ #ifndef simd_rotl_2_hl
2204
+ inline SIMD_type simd_rotl_2_hl(SIMD_type v1, SIMD_type v2) {
2205
+ return simd_rotl_2(simd_srli_2(v1, 1), v2);
2206
+ }
2207
+ #endif
2208
+
2209
+ #ifndef simd_rotl_2_hh
2210
+ inline SIMD_type simd_rotl_2_hh(SIMD_type v1, SIMD_type v2) {
2211
+ return simd_rotl_2(simd_srli_2(v1, 1), simd_srli_16(v2, 1));
2212
+ }
2213
+ #endif
2214
+
2215
+ #ifndef simd_rotl_4_xx
2216
+ inline SIMD_type simd_rotl_4_xx(SIMD_type v1, SIMD_type v2) {
2217
+ return simd_rotl_4(v1, v2);
2218
+ }
2219
+ #endif
2220
+
2221
+ #ifndef simd_rotl_4_xl
2222
+ inline SIMD_type simd_rotl_4_xl(SIMD_type v1, SIMD_type v2) {
2223
+ return simd_rotl_4(v1, v2);
2224
+ }
2225
+ #endif
2226
+
2227
+ #ifndef simd_rotl_4_xh
2228
+ inline SIMD_type simd_rotl_4_xh(SIMD_type v1, SIMD_type v2) {
2229
+ return simd_rotl_4(v1, simd_srli_16(v2, 2));
2230
+ }
2231
+ #endif
2232
+
2233
+ #ifndef simd_rotl_4_lx
2234
+ inline SIMD_type simd_rotl_4_lx(SIMD_type v1, SIMD_type v2) {
2235
+ return simd_rotl_4(simd_andc(v1, simd_himask_4), v2);
2236
+ }
2237
+ #endif
2238
+
2239
+ #ifndef simd_rotl_4_ll
2240
+ inline SIMD_type simd_rotl_4_ll(SIMD_type v1, SIMD_type v2) {
2241
+ return simd_rotl_4(simd_andc(v1, simd_himask_4), v2);
2242
+ }
2243
+ #endif
2244
+
2245
+ #ifndef simd_rotl_4_lh
2246
+ inline SIMD_type simd_rotl_4_lh(SIMD_type v1, SIMD_type v2) {
2247
+ return simd_rotl_4(simd_andc(v1, simd_himask_4), simd_srli_16(v2, 2));
2248
+ }
2249
+ #endif
2250
+
2251
+ #ifndef simd_rotl_4_hx
2252
+ inline SIMD_type simd_rotl_4_hx(SIMD_type v1, SIMD_type v2) {
2253
+ return simd_rotl_4(simd_srli_4(v1, 2), v2);
2254
+ }
2255
+ #endif
2256
+
2257
+ #ifndef simd_rotl_4_hl
2258
+ inline SIMD_type simd_rotl_4_hl(SIMD_type v1, SIMD_type v2) {
2259
+ return simd_rotl_4(simd_srli_4(v1, 2), v2);
2260
+ }
2261
+ #endif
2262
+
2263
+ #ifndef simd_rotl_4_hh
2264
+ inline SIMD_type simd_rotl_4_hh(SIMD_type v1, SIMD_type v2) {
2265
+ return simd_rotl_4(simd_srli_4(v1, 2), simd_srli_16(v2, 2));
2266
+ }
2267
+ #endif
2268
+
2269
+ #ifndef simd_rotl_8_xx
2270
+ inline SIMD_type simd_rotl_8_xx(SIMD_type v1, SIMD_type v2) {
2271
+ return simd_rotl_8(v1, v2);
2272
+ }
2273
+ #endif
2274
+
2275
+ #ifndef simd_rotl_8_xl
2276
+ inline SIMD_type simd_rotl_8_xl(SIMD_type v1, SIMD_type v2) {
2277
+ return simd_rotl_8(v1, v2);
2278
+ }
2279
+ #endif
2280
+
2281
+ #ifndef simd_rotl_8_xh
2282
+ inline SIMD_type simd_rotl_8_xh(SIMD_type v1, SIMD_type v2) {
2283
+ return simd_rotl_8(v1, simd_srli_16(v2, 4));
2284
+ }
2285
+ #endif
2286
+
2287
+ #ifndef simd_rotl_8_lx
2288
+ inline SIMD_type simd_rotl_8_lx(SIMD_type v1, SIMD_type v2) {
2289
+ return simd_rotl_8(simd_andc(v1, simd_himask_8), v2);
2290
+ }
2291
+ #endif
2292
+
2293
+ #ifndef simd_rotl_8_ll
2294
+ inline SIMD_type simd_rotl_8_ll(SIMD_type v1, SIMD_type v2) {
2295
+ return simd_rotl_8(simd_andc(v1, simd_himask_8), v2);
2296
+ }
2297
+ #endif
2298
+
2299
+ #ifndef simd_rotl_8_lh
2300
+ inline SIMD_type simd_rotl_8_lh(SIMD_type v1, SIMD_type v2) {
2301
+ return simd_rotl_8(simd_andc(v1, simd_himask_8), simd_srli_16(v2, 4));
2302
+ }
2303
+ #endif
2304
+
2305
+ #ifndef simd_rotl_8_hx
2306
+ inline SIMD_type simd_rotl_8_hx(SIMD_type v1, SIMD_type v2) {
2307
+ return simd_rotl_8(simd_srli_8(v1, 4), v2);
2308
+ }
2309
+ #endif
2310
+
2311
+ #ifndef simd_rotl_8_hl
2312
+ inline SIMD_type simd_rotl_8_hl(SIMD_type v1, SIMD_type v2) {
2313
+ return simd_rotl_8(simd_srli_8(v1, 4), v2);
2314
+ }
2315
+ #endif
2316
+
2317
+ #ifndef simd_rotl_8_hh
2318
+ inline SIMD_type simd_rotl_8_hh(SIMD_type v1, SIMD_type v2) {
2319
+ return simd_rotl_8(simd_srli_8(v1, 4), simd_srli_16(v2, 4));
2320
+ }
2321
+ #endif
2322
+
2323
+ #ifndef simd_rotl_16_xx
2324
+ inline SIMD_type simd_rotl_16_xx(SIMD_type v1, SIMD_type v2) {
2325
+ return simd_rotl_16(v1, v2);
2326
+ }
2327
+ #endif
2328
+
2329
+ #ifndef simd_rotl_16_xl
2330
+ inline SIMD_type simd_rotl_16_xl(SIMD_type v1, SIMD_type v2) {
2331
+ return simd_rotl_16(v1, v2);
2332
+ }
2333
+ #endif
2334
+
2335
+ #ifndef simd_rotl_16_xh
2336
+ inline SIMD_type simd_rotl_16_xh(SIMD_type v1, SIMD_type v2) {
2337
+ return simd_rotl_16(v1, simd_srli_16(v2, 8));
2338
+ }
2339
+ #endif
2340
+
2341
+ #ifndef simd_rotl_16_lx
2342
+ inline SIMD_type simd_rotl_16_lx(SIMD_type v1, SIMD_type v2) {
2343
+ return simd_rotl_16(simd_andc(v1, simd_himask_16), v2);
2344
+ }
2345
+ #endif
2346
+
2347
+ #ifndef simd_rotl_16_ll
2348
+ inline SIMD_type simd_rotl_16_ll(SIMD_type v1, SIMD_type v2) {
2349
+ return simd_rotl_16(simd_andc(v1, simd_himask_16), v2);
2350
+ }
2351
+ #endif
2352
+
2353
+ #ifndef simd_rotl_16_lh
2354
+ inline SIMD_type simd_rotl_16_lh(SIMD_type v1, SIMD_type v2) {
2355
+ return simd_rotl_16(simd_andc(v1, simd_himask_16), simd_srli_16(v2, 8));
2356
+ }
2357
+ #endif
2358
+
2359
+ #ifndef simd_rotl_16_hx
2360
+ inline SIMD_type simd_rotl_16_hx(SIMD_type v1, SIMD_type v2) {
2361
+ return simd_rotl_16(simd_srli_16(v1, 8), v2);
2362
+ }
2363
+ #endif
2364
+
2365
+ #ifndef simd_rotl_16_hl
2366
+ inline SIMD_type simd_rotl_16_hl(SIMD_type v1, SIMD_type v2) {
2367
+ return simd_rotl_16(simd_srli_16(v1, 8), v2);
2368
+ }
2369
+ #endif
2370
+
2371
+ #ifndef simd_rotl_16_hh
2372
+ inline SIMD_type simd_rotl_16_hh(SIMD_type v1, SIMD_type v2) {
2373
+ return simd_rotl_16(simd_srli_16(v1, 8), simd_srli_16(v2, 8));
2374
+ }
2375
+ #endif
2376
+
2377
+ #ifndef simd_rotl_32_xx
2378
+ inline SIMD_type simd_rotl_32_xx(SIMD_type v1, SIMD_type v2) {
2379
+ return simd_rotl_32(v1, v2);
2380
+ }
2381
+ #endif
2382
+
2383
+ #ifndef simd_rotl_32_xl
2384
+ inline SIMD_type simd_rotl_32_xl(SIMD_type v1, SIMD_type v2) {
2385
+ return simd_rotl_32(v1, v2);
2386
+ }
2387
+ #endif
2388
+
2389
+ #ifndef simd_rotl_32_xh
2390
+ inline SIMD_type simd_rotl_32_xh(SIMD_type v1, SIMD_type v2) {
2391
+ return simd_rotl_32(v1, simd_srli_32(v2, 16));
2392
+ }
2393
+ #endif
2394
+
2395
+ #ifndef simd_rotl_32_lx
2396
+ inline SIMD_type simd_rotl_32_lx(SIMD_type v1, SIMD_type v2) {
2397
+ return simd_rotl_32(simd_andc(v1, simd_himask_32), v2);
2398
+ }
2399
+ #endif
2400
+
2401
+ #ifndef simd_rotl_32_ll
2402
+ inline SIMD_type simd_rotl_32_ll(SIMD_type v1, SIMD_type v2) {
2403
+ return simd_rotl_32(simd_andc(v1, simd_himask_32), v2);
2404
+ }
2405
+ #endif
2406
+
2407
+ #ifndef simd_rotl_32_lh
2408
+ inline SIMD_type simd_rotl_32_lh(SIMD_type v1, SIMD_type v2) {
2409
+ return simd_rotl_32(simd_andc(v1, simd_himask_32), simd_srli_32(v2, 16));
2410
+ }
2411
+ #endif
2412
+
2413
+ #ifndef simd_rotl_32_hx
2414
+ inline SIMD_type simd_rotl_32_hx(SIMD_type v1, SIMD_type v2) {
2415
+ return simd_rotl_32(simd_srli_32(v1, 16), v2);
2416
+ }
2417
+ #endif
2418
+
2419
+ #ifndef simd_rotl_32_hl
2420
+ inline SIMD_type simd_rotl_32_hl(SIMD_type v1, SIMD_type v2) {
2421
+ return simd_rotl_32(simd_srli_32(v1, 16), v2);
2422
+ }
2423
+ #endif
2424
+
2425
+ #ifndef simd_rotl_32_hh
2426
+ inline SIMD_type simd_rotl_32_hh(SIMD_type v1, SIMD_type v2) {
2427
+ return simd_rotl_32(simd_srli_32(v1, 16), simd_srli_32(v2, 16));
2428
+ }
2429
+ #endif
2430
+