code-languages 1.17.0 → 1.19.0

package/dist/languages/verilog.cjs

@@ -0,0 +1,34 @@
+'use strict';
+
+// src/languages/verilog.ts
+var verilog = {
+  slug: "verilog",
+  publishedDate: "1984-01-01",
+  extensions: [".v", ".vh", ".sv", ".svh"],
+  author: "Phil Moorby / Gateway Design Automation",
+  website: "https://standards.ieee.org/standard/1800-2023.html",
+  paradigms: ["hardware-description", "concurrent", "event-driven", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1800-2023",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  i18n: {
+    en: {
+      name: "Verilog/SystemVerilog",
+      description: "A hardware description and verification language for digital circuits and systems.",
+      longDescription: "Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\n\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows."
+    },
+    es: {
+      name: "Verilog/SystemVerilog",
+      description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
+      longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+exports.verilog = verilog;
+//# sourceMappingURL=verilog.cjs.map
+//# sourceMappingURL=verilog.cjs.map

package/dist/languages/verilog.cjs.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";;;AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/verilog.d.cts

@@ -0,0 +1,29 @@
+declare const verilog: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { verilog };

package/dist/languages/verilog.d.ts

@@ -0,0 +1,29 @@
+declare const verilog: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { verilog };

package/dist/languages/verilog.js

@@ -0,0 +1,32 @@
+// src/languages/verilog.ts
+var verilog = {
+  slug: "verilog",
+  publishedDate: "1984-01-01",
+  extensions: [".v", ".vh", ".sv", ".svh"],
+  author: "Phil Moorby / Gateway Design Automation",
+  website: "https://standards.ieee.org/standard/1800-2023.html",
+  paradigms: ["hardware-description", "concurrent", "event-driven", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1800-2023",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg",
+  i18n: {
+    en: {
+      name: "Verilog/SystemVerilog",
+      description: "A hardware description and verification language for digital circuits and systems.",
+      longDescription: "Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\n\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows."
+    },
+    es: {
+      name: "Verilog/SystemVerilog",
+      description: "Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.",
+      longDescription: "Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\n\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+export { verilog };
+//# sourceMappingURL=verilog.js.map
+//# sourceMappingURL=verilog.js.map

package/dist/languages/verilog.js.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/verilog.ts"],"names":[],"mappings":";AAEO,IAAM,OAAA,GAAU;AAAA,EACrB,IAAA,EAAM,SAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,IAAA,EAAM,KAAA,EAAO,OAAO,MAAM,CAAA;AAAA,EACvC,MAAA,EAAQ,yCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,gBAAgB,cAAc,CAAA;AAAA,EAChF,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,SAAS,CAAA;AAAA,IAC3B,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,0FAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,oFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,uBAAA;AAAA,MACN,WAAA,EACE,4FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"verilog.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const verilog = {\n  slug: \"verilog\",\n  publishedDate: \"1984-01-01\",\n  extensions: [\".v\", \".vh\", \".sv\", \".svh\"],\n  author: \"Phil Moorby / Gateway Design Automation\",\n  website: \"https://standards.ieee.org/standard/1800-2023.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"event-driven\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1800-2023\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_verilog.svg\",\n  i18n: {\n    en: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"A hardware description and verification language for digital circuits and systems.\",\n      longDescription:\n        \"Verilog and SystemVerilog describe digital hardware at behavioral, register-transfer, and gate levels. The language supports modules, signals, continuous assignments, procedural blocks, timing, testbenches, assertions, interfaces, classes, and constrained random verification.\\n\\nIt is used for FPGA designs, ASIC development, hardware simulation, synthesis, verification environments, reusable IP blocks, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"Verilog/SystemVerilog\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para circuitos y sistemas digitales.\",\n      longDescription:\n        \"Verilog y SystemVerilog describen hardware digital en niveles conductual, register-transfer y de compuertas. El lenguaje soporta modulos, senales, asignaciones continuas, bloques procedurales, timing, testbenches, assertions, interfaces, clases y verificacion aleatoria restringida.\\n\\nSe usa en disenos FPGA, desarrollo ASIC, simulacion de hardware, sintesis, entornos de verificacion, bloques IP reutilizables y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vhdl.cjs

@@ -0,0 +1,34 @@
+'use strict';
+
+// src/languages/vhdl.ts
+var vhdl = {
+  slug: "vhdl",
+  publishedDate: "1987-01-01",
+  extensions: [".vhd", ".vhdl"],
+  author: "U.S. Department of Defense / IEEE",
+  website: "https://standards.ieee.org/standard/1076-2019.html",
+  paradigms: ["hardware-description", "concurrent", "dataflow", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["VUnit", "FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1076-2019",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg",
+  i18n: {
+    en: {
+      name: "VHDL",
+      description: "A hardware description and verification language for digital electronic systems.",
+      longDescription: "VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\n\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows."
+    },
+    es: {
+      name: "VHDL",
+      description: "Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.",
+      longDescription: "VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\n\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+exports.vhdl = vhdl;
+//# sourceMappingURL=vhdl.cjs.map
+//# sourceMappingURL=vhdl.cjs.map

package/dist/languages/vhdl.cjs.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";;;AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/vhdl.d.cts

@@ -0,0 +1,29 @@
+declare const vhdl: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { vhdl };

package/dist/languages/vhdl.d.ts

@@ -0,0 +1,29 @@
+declare const vhdl: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { vhdl };

package/dist/languages/vhdl.js

@@ -0,0 +1,32 @@
+// src/languages/vhdl.ts
+var vhdl = {
+  slug: "vhdl",
+  publishedDate: "1987-01-01",
+  extensions: [".vhd", ".vhdl"],
+  author: "U.S. Department of Defense / IEEE",
+  website: "https://standards.ieee.org/standard/1076-2019.html",
+  paradigms: ["hardware-description", "concurrent", "dataflow", "verification"],
+  tooling: {
+    runtimes: ["FPGA Toolchains", "ASIC EDA Tools", "Simulators"],
+    packageManagers: ["VUnit", "FuseSoC"],
+    ecosystems: ["Hardware Design", "FPGA", "ASIC", "Verification"]
+  },
+  version: "IEEE 1076-2019",
+  logo: "https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg",
+  i18n: {
+    en: {
+      name: "VHDL",
+      description: "A hardware description and verification language for digital electronic systems.",
+      longDescription: "VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\n\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows."
+    },
+    es: {
+      name: "VHDL",
+      description: "Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.",
+      longDescription: "VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\n\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico."
+    }
+  }
+};
+
+export { vhdl };
+//# sourceMappingURL=vhdl.js.map
+//# sourceMappingURL=vhdl.js.map

package/dist/languages/vhdl.js.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/vhdl.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,MAAA,EAAQ,OAAO,CAAA;AAAA,EAC5B,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,oDAAA;AAAA,EACT,SAAA,EAAW,CAAC,sBAAA,EAAwB,YAAA,EAAc,YAAY,cAAc,CAAA;AAAA,EAC5E,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,iBAAA,EAAmB,gBAAA,EAAkB,YAAY,CAAA;AAAA,IAC5D,eAAA,EAAiB,CAAC,OAAA,EAAS,SAAS,CAAA;AAAA,IACpC,UAAA,EAAY,CAAC,iBAAA,EAAmB,MAAA,EAAQ,QAAQ,cAAc;AAAA,GAChE;AAAA,EACA,OAAA,EAAS,gBAAA;AAAA,EACT,IAAA,EAAM,uFAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,kFAAA;AAAA,MACF,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,6FAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"vhdl.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const vhdl = {\n  slug: \"vhdl\",\n  publishedDate: \"1987-01-01\",\n  extensions: [\".vhd\", \".vhdl\"],\n  author: \"U.S. Department of Defense / IEEE\",\n  website: \"https://standards.ieee.org/standard/1076-2019.html\",\n  paradigms: [\"hardware-description\", \"concurrent\", \"dataflow\", \"verification\"],\n  tooling: {\n    runtimes: [\"FPGA Toolchains\", \"ASIC EDA Tools\", \"Simulators\"],\n    packageManagers: [\"VUnit\", \"FuseSoC\"],\n    ecosystems: [\"Hardware Design\", \"FPGA\", \"ASIC\", \"Verification\"],\n  },\n  version: \"IEEE 1076-2019\",\n  logo: \"https://cdn.jsdelivr.net/gh/vscode-icons/vscode-icons@master/icons/file_type_vhdl.svg\",\n  i18n: {\n    en: {\n      name: \"VHDL\",\n      description:\n        \"A hardware description and verification language for digital electronic systems.\",\n      longDescription:\n        \"VHDL describes digital systems using entities, architectures, signals, processes, concurrent statements, packages, generics, configurations, testbenches, and strongly typed design units. It supports simulation, synthesis, and verification across multiple abstraction levels.\\n\\nIt is used for FPGA development, ASIC design, hardware verification, reusable IP blocks, digital signal processing, safety-critical hardware, and electronic design automation workflows.\",\n    },\n    es: {\n      name: \"VHDL\",\n      description:\n        \"Un lenguaje de descripcion y verificacion de hardware para sistemas electronicos digitales.\",\n      longDescription:\n        \"VHDL describe sistemas digitales usando entidades, arquitecturas, senales, procesos, sentencias concurrentes, paquetes, generics, configuraciones, testbenches y unidades de diseno fuertemente tipadas. Soporta simulacion, sintesis y verificacion en varios niveles de abstraccion.\\n\\nSe usa en desarrollo FPGA, diseno ASIC, verificacion de hardware, bloques IP reutilizables, procesamiento digital de senales, hardware critico para seguridad y flujos de automatizacion de diseno electronico.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/wgsl.cjs

@@ -0,0 +1,34 @@
+'use strict';
+
+// src/languages/wgsl.ts
+var wgsl = {
+  slug: "wgsl",
+  publishedDate: "2021-05-18",
+  extensions: [".wgsl"],
+  author: "W3C GPU for the Web Working Group",
+  website: "https://www.w3.org/TR/WGSL/",
+  paradigms: ["shader", "data-parallel", "graphics", "gpu-compute"],
+  tooling: {
+    runtimes: ["WebGPU", "Browsers", "wgpu"],
+    packageManagers: ["npm", "Cargo"],
+    ecosystems: ["WebGPU", "Graphics", "GPU Programming", "Web"]
+  },
+  version: "Candidate Recommendation Draft 2026-05-07",
+  logo: "https://cdn.simpleicons.org/webgpu/005A9C",
+  i18n: {
+    en: {
+      name: "WGSL",
+      description: "The WebGPU Shading Language for portable browser and native GPU programs.",
+      longDescription: "WGSL is the shader language for WebGPU, designed for predictable validation, portability, and safety across graphics backends. It includes explicit types, address spaces, entry points, bindings, uniforms, storage buffers, textures, workgroups, and built-in functions for graphics and compute shaders.\n\nIt is used in WebGPU applications, browser rendering, native wgpu projects, visualization tools, compute workloads, creative coding, and graphics engines that target portable GPU execution."
+    },
+    es: {
+      name: "WGSL",
+      description: "El lenguaje de shading de WebGPU para programas GPU portables en navegador y nativo.",
+      longDescription: "WGSL es el lenguaje de shaders de WebGPU, disenado para validacion predecible, portabilidad y seguridad entre backends graficos. Incluye tipos explicitos, address spaces, entry points, bindings, uniforms, storage buffers, texturas, workgroups y funciones integradas para shaders graficos y compute.\n\nSe usa en aplicaciones WebGPU, rendering en navegador, proyectos nativos con wgpu, herramientas de visualizacion, cargas compute, creative coding y motores graficos que apuntan a ejecucion GPU portable."
+    }
+  }
+};
+
+exports.wgsl = wgsl;
+//# sourceMappingURL=wgsl.cjs.map
+//# sourceMappingURL=wgsl.cjs.map

package/dist/languages/wgsl.cjs.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/wgsl.ts"],"names":[],"mappings":";;;AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,OAAO,CAAA;AAAA,EACpB,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,6BAAA;AAAA,EACT,SAAA,EAAW,CAAC,QAAA,EAAU,eAAA,EAAiB,YAAY,aAAa,CAAA;AAAA,EAChE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,QAAA,EAAU,UAAA,EAAY,MAAM,CAAA;AAAA,IACvC,eAAA,EAAiB,CAAC,KAAA,EAAO,OAAO,CAAA;AAAA,IAChC,UAAA,EAAY,CAAC,QAAA,EAAU,UAAA,EAAY,mBAAmB,KAAK;AAAA,GAC7D;AAAA,EACA,OAAA,EAAS,2CAAA;AAAA,EACT,IAAA,EAAM,2CAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,2EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,sFAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"wgsl.cjs","sourcesContent":["import type { Language } from \"../types\";\n\nexport const wgsl = {\n  slug: \"wgsl\",\n  publishedDate: \"2021-05-18\",\n  extensions: [\".wgsl\"],\n  author: \"W3C GPU for the Web Working Group\",\n  website: \"https://www.w3.org/TR/WGSL/\",\n  paradigms: [\"shader\", \"data-parallel\", \"graphics\", \"gpu-compute\"],\n  tooling: {\n    runtimes: [\"WebGPU\", \"Browsers\", \"wgpu\"],\n    packageManagers: [\"npm\", \"Cargo\"],\n    ecosystems: [\"WebGPU\", \"Graphics\", \"GPU Programming\", \"Web\"],\n  },\n  version: \"Candidate Recommendation Draft 2026-05-07\",\n  logo: \"https://cdn.simpleicons.org/webgpu/005A9C\",\n  i18n: {\n    en: {\n      name: \"WGSL\",\n      description: \"The WebGPU Shading Language for portable browser and native GPU programs.\",\n      longDescription:\n        \"WGSL is the shader language for WebGPU, designed for predictable validation, portability, and safety across graphics backends. It includes explicit types, address spaces, entry points, bindings, uniforms, storage buffers, textures, workgroups, and built-in functions for graphics and compute shaders.\\n\\nIt is used in WebGPU applications, browser rendering, native wgpu projects, visualization tools, compute workloads, creative coding, and graphics engines that target portable GPU execution.\",\n    },\n    es: {\n      name: \"WGSL\",\n      description:\n        \"El lenguaje de shading de WebGPU para programas GPU portables en navegador y nativo.\",\n      longDescription:\n        \"WGSL es el lenguaje de shaders de WebGPU, disenado para validacion predecible, portabilidad y seguridad entre backends graficos. Incluye tipos explicitos, address spaces, entry points, bindings, uniforms, storage buffers, texturas, workgroups y funciones integradas para shaders graficos y compute.\\n\\nSe usa en aplicaciones WebGPU, rendering en navegador, proyectos nativos con wgpu, herramientas de visualizacion, cargas compute, creative coding y motores graficos que apuntan a ejecucion GPU portable.\",\n    },\n  },\n} satisfies Language;\n"]}

package/dist/languages/wgsl.d.cts

@@ -0,0 +1,29 @@
+declare const wgsl: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { wgsl };

package/dist/languages/wgsl.d.ts

@@ -0,0 +1,29 @@
+declare const wgsl: {
+    slug: string;
+    publishedDate: string;
+    extensions: string[];
+    author: string;
+    website: string;
+    paradigms: string[];
+    tooling: {
+        runtimes: string[];
+        packageManagers: string[];
+        ecosystems: string[];
+    };
+    version: string;
+    logo: string;
+    i18n: {
+        en: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+        es: {
+            name: string;
+            description: string;
+            longDescription: string;
+        };
+    };
+};
+
+export { wgsl };

package/dist/languages/wgsl.js

@@ -0,0 +1,32 @@
+// src/languages/wgsl.ts
+var wgsl = {
+  slug: "wgsl",
+  publishedDate: "2021-05-18",
+  extensions: [".wgsl"],
+  author: "W3C GPU for the Web Working Group",
+  website: "https://www.w3.org/TR/WGSL/",
+  paradigms: ["shader", "data-parallel", "graphics", "gpu-compute"],
+  tooling: {
+    runtimes: ["WebGPU", "Browsers", "wgpu"],
+    packageManagers: ["npm", "Cargo"],
+    ecosystems: ["WebGPU", "Graphics", "GPU Programming", "Web"]
+  },
+  version: "Candidate Recommendation Draft 2026-05-07",
+  logo: "https://cdn.simpleicons.org/webgpu/005A9C",
+  i18n: {
+    en: {
+      name: "WGSL",
+      description: "The WebGPU Shading Language for portable browser and native GPU programs.",
+      longDescription: "WGSL is the shader language for WebGPU, designed for predictable validation, portability, and safety across graphics backends. It includes explicit types, address spaces, entry points, bindings, uniforms, storage buffers, textures, workgroups, and built-in functions for graphics and compute shaders.\n\nIt is used in WebGPU applications, browser rendering, native wgpu projects, visualization tools, compute workloads, creative coding, and graphics engines that target portable GPU execution."
+    },
+    es: {
+      name: "WGSL",
+      description: "El lenguaje de shading de WebGPU para programas GPU portables en navegador y nativo.",
+      longDescription: "WGSL es el lenguaje de shaders de WebGPU, disenado para validacion predecible, portabilidad y seguridad entre backends graficos. Incluye tipos explicitos, address spaces, entry points, bindings, uniforms, storage buffers, texturas, workgroups y funciones integradas para shaders graficos y compute.\n\nSe usa en aplicaciones WebGPU, rendering en navegador, proyectos nativos con wgpu, herramientas de visualizacion, cargas compute, creative coding y motores graficos que apuntan a ejecucion GPU portable."
+    }
+  }
+};
+
+export { wgsl };
+//# sourceMappingURL=wgsl.js.map
+//# sourceMappingURL=wgsl.js.map

package/dist/languages/wgsl.js.map

@@ -0,0 +1 @@
+{"version":3,"sources":["../../src/languages/wgsl.ts"],"names":[],"mappings":";AAEO,IAAM,IAAA,GAAO;AAAA,EAClB,IAAA,EAAM,MAAA;AAAA,EACN,aAAA,EAAe,YAAA;AAAA,EACf,UAAA,EAAY,CAAC,OAAO,CAAA;AAAA,EACpB,MAAA,EAAQ,mCAAA;AAAA,EACR,OAAA,EAAS,6BAAA;AAAA,EACT,SAAA,EAAW,CAAC,QAAA,EAAU,eAAA,EAAiB,YAAY,aAAa,CAAA;AAAA,EAChE,OAAA,EAAS;AAAA,IACP,QAAA,EAAU,CAAC,QAAA,EAAU,UAAA,EAAY,MAAM,CAAA;AAAA,IACvC,eAAA,EAAiB,CAAC,KAAA,EAAO,OAAO,CAAA;AAAA,IAChC,UAAA,EAAY,CAAC,QAAA,EAAU,UAAA,EAAY,mBAAmB,KAAK;AAAA,GAC7D;AAAA,EACA,OAAA,EAAS,2CAAA;AAAA,EACT,IAAA,EAAM,2CAAA;AAAA,EACN,IAAA,EAAM;AAAA,IACJ,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EAAa,2EAAA;AAAA,MACb,eAAA,EACE;AAAA,KACJ;AAAA,IACA,EAAA,EAAI;AAAA,MACF,IAAA,EAAM,MAAA;AAAA,MACN,WAAA,EACE,sFAAA;AAAA,MACF,eAAA,EACE;AAAA;AACJ;AAEJ","file":"wgsl.js","sourcesContent":["import type { Language } from \"../types\";\n\nexport const wgsl = {\n  slug: \"wgsl\",\n  publishedDate: \"2021-05-18\",\n  extensions: [\".wgsl\"],\n  author: \"W3C GPU for the Web Working Group\",\n  website: \"https://www.w3.org/TR/WGSL/\",\n  paradigms: [\"shader\", \"data-parallel\", \"graphics\", \"gpu-compute\"],\n  tooling: {\n    runtimes: [\"WebGPU\", \"Browsers\", \"wgpu\"],\n    packageManagers: [\"npm\", \"Cargo\"],\n    ecosystems: [\"WebGPU\", \"Graphics\", \"GPU Programming\", \"Web\"],\n  },\n  version: \"Candidate Recommendation Draft 2026-05-07\",\n  logo: \"https://cdn.simpleicons.org/webgpu/005A9C\",\n  i18n: {\n    en: {\n      name: \"WGSL\",\n      description: \"The WebGPU Shading Language for portable browser and native GPU programs.\",\n      longDescription:\n        \"WGSL is the shader language for WebGPU, designed for predictable validation, portability, and safety across graphics backends. It includes explicit types, address spaces, entry points, bindings, uniforms, storage buffers, textures, workgroups, and built-in functions for graphics and compute shaders.\\n\\nIt is used in WebGPU applications, browser rendering, native wgpu projects, visualization tools, compute workloads, creative coding, and graphics engines that target portable GPU execution.\",\n    },\n    es: {\n      name: \"WGSL\",\n      description:\n        \"El lenguaje de shading de WebGPU para programas GPU portables en navegador y nativo.\",\n      longDescription:\n        \"WGSL es el lenguaje de shaders de WebGPU, disenado para validacion predecible, portabilidad y seguridad entre backends graficos. Incluye tipos explicitos, address spaces, entry points, bindings, uniforms, storage buffers, texturas, workgroups y funciones integradas para shaders graficos y compute.\\n\\nSe usa en aplicaciones WebGPU, rendering en navegador, proyectos nativos con wgpu, herramientas de visualizacion, cargas compute, creative coding y motores graficos que apuntan a ejecucion GPU portable.\",\n    },\n  },\n} satisfies Language;\n"]}

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "code-languages",
-  "version": "1.17.0",
+  "version": "1.19.0",
   "description": "Structured metadata for programming languages.",
   "homepage": "https://github.com/ElJijuna/code-languages#readme",
   "bugs": {
@@ -61,6 +61,11 @@
       "import": "./dist/languages/actionscript.js",
       "require": "./dist/languages/actionscript.cjs"
     },
+    "./asciidoc": {
+      "types": "./dist/languages/asciidoc.d.ts",
+      "import": "./dist/languages/asciidoc.js",
+      "require": "./dist/languages/asciidoc.cjs"
+    },
     "./asp": {
       "types": "./dist/languages/asp.d.ts",
       "import": "./dist/languages/asp.js",
@@ -86,6 +91,21 @@
       "import": "./dist/languages/batch.js",
       "require": "./dist/languages/batch.cjs"
     },
+    "./bazel": {
+      "types": "./dist/languages/bazel.d.ts",
+      "import": "./dist/languages/bazel.js",
+      "require": "./dist/languages/bazel.cjs"
+    },
+    "./bicep": {
+      "types": "./dist/languages/bicep.d.ts",
+      "import": "./dist/languages/bicep.js",
+      "require": "./dist/languages/bicep.cjs"
+    },
+    "./blade": {
+      "types": "./dist/languages/blade.d.ts",
+      "import": "./dist/languages/blade.js",
+      "require": "./dist/languages/blade.cjs"
+    },
     "./c": {
       "types": "./dist/languages/c.d.ts",
       "import": "./dist/languages/c.js",
@@ -111,6 +131,11 @@
       "import": "./dist/languages/crystal.js",
       "require": "./dist/languages/crystal.cjs"
     },
+    "./cue": {
+      "types": "./dist/languages/cue.d.ts",
+      "import": "./dist/languages/cue.js",
+      "require": "./dist/languages/cue.cjs"
+    },
     "./cuda": {
       "types": "./dist/languages/cuda.d.ts",
       "import": "./dist/languages/cuda.js",
@@ -151,6 +176,21 @@
       "import": "./dist/languages/typescript.js",
       "require": "./dist/languages/typescript.cjs"
     },
+    "./typst": {
+      "types": "./dist/languages/typst.d.ts",
+      "import": "./dist/languages/typst.js",
+      "require": "./dist/languages/typst.cjs"
+    },
+    "./verilog": {
+      "types": "./dist/languages/verilog.d.ts",
+      "import": "./dist/languages/verilog.js",
+      "require": "./dist/languages/verilog.cjs"
+    },
+    "./vhdl": {
+      "types": "./dist/languages/vhdl.d.ts",
+      "import": "./dist/languages/vhdl.js",
+      "require": "./dist/languages/vhdl.cjs"
+    },
     "./visual-basic": {
       "types": "./dist/languages/visual-basic.d.ts",
       "import": "./dist/languages/visual-basic.js",
@@ -226,6 +266,11 @@
       "import": "./dist/languages/sql.js",
       "require": "./dist/languages/sql.cjs"
     },
+    "./starlark": {
+      "types": "./dist/languages/starlark.d.ts",
+      "import": "./dist/languages/starlark.js",
+      "require": "./dist/languages/starlark.cjs"
+    },
     "./svg": {
       "types": "./dist/languages/svg.d.ts",
       "import": "./dist/languages/svg.js",
@@ -256,16 +301,46 @@
       "import": "./dist/languages/java.js",
       "require": "./dist/languages/java.cjs"
     },
+    "./jinja": {
+      "types": "./dist/languages/jinja.d.ts",
+      "import": "./dist/languages/jinja.js",
+      "require": "./dist/languages/jinja.cjs"
+    },
+    "./liquid": {
+      "types": "./dist/languages/liquid.d.ts",
+      "import": "./dist/languages/liquid.js",
+      "require": "./dist/languages/liquid.cjs"
+    },
+    "./mdx": {
+      "types": "./dist/languages/mdx.d.ts",
+      "import": "./dist/languages/mdx.js",
+      "require": "./dist/languages/mdx.cjs"
+    },
+    "./mermaid": {
+      "types": "./dist/languages/mermaid.d.ts",
+      "import": "./dist/languages/mermaid.js",
+      "require": "./dist/languages/mermaid.cjs"
+    },
     "./php": {
       "types": "./dist/languages/php.d.ts",
       "import": "./dist/languages/php.js",
       "require": "./dist/languages/php.cjs"
     },
+    "./plantuml": {
+      "types": "./dist/languages/plantuml.d.ts",
+      "import": "./dist/languages/plantuml.js",
+      "require": "./dist/languages/plantuml.cjs"
+    },
     "./powershell": {
       "types": "./dist/languages/powershell.d.ts",
       "import": "./dist/languages/powershell.js",
       "require": "./dist/languages/powershell.cjs"
     },
+    "./prolog": {
+      "types": "./dist/languages/prolog.d.ts",
+      "import": "./dist/languages/prolog.js",
+      "require": "./dist/languages/prolog.cjs"
+    },
     "./protobuf": {
       "types": "./dist/languages/protobuf.d.ts",
       "import": "./dist/languages/protobuf.js",
@@ -276,6 +351,11 @@
       "import": "./dist/languages/pug.js",
       "require": "./dist/languages/pug.cjs"
     },
+    "./qml": {
+      "types": "./dist/languages/qml.d.ts",
+      "import": "./dist/languages/qml.js",
+      "require": "./dist/languages/qml.cjs"
+    },
     "./python": {
       "types": "./dist/languages/python.d.ts",
       "import": "./dist/languages/python.js",
@@ -326,6 +406,11 @@
       "import": "./dist/languages/webassembly.js",
       "require": "./dist/languages/webassembly.cjs"
     },
+    "./wgsl": {
+      "types": "./dist/languages/wgsl.d.ts",
+      "import": "./dist/languages/wgsl.js",
+      "require": "./dist/languages/wgsl.cjs"
+    },
     "./xaml": {
       "types": "./dist/languages/xaml.d.ts",
       "import": "./dist/languages/xaml.js",
@@ -371,6 +456,11 @@
       "import": "./dist/languages/hcl.js",
       "require": "./dist/languages/hcl.cjs"
     },
+    "./hlsl": {
+      "types": "./dist/languages/hlsl.d.ts",
+      "import": "./dist/languages/hlsl.js",
+      "require": "./dist/languages/hlsl.cjs"
+    },
     "./css": {
       "types": "./dist/languages/css.d.ts",
       "import": "./dist/languages/css.js",
@@ -391,6 +481,16 @@
       "import": "./dist/languages/fsharp.js",
       "require": "./dist/languages/fsharp.cjs"
     },
+    "./gdscript": {
+      "types": "./dist/languages/gdscript.d.ts",
+      "import": "./dist/languages/gdscript.js",
+      "require": "./dist/languages/gdscript.cjs"
+    },
+    "./handlebars": {
+      "types": "./dist/languages/handlebars.d.ts",
+      "import": "./dist/languages/handlebars.js",
+      "require": "./dist/languages/handlebars.cjs"
+    },
     "./html": {
       "types": "./dist/languages/html.d.ts",
       "import": "./dist/languages/html.js",