ac6502 1.10.0 → 1.11.0

package/src/components/IO/ACIA.ts

@@ -3,6 +3,9 @@ import { IO } from '../IO'
 /**
  * ACIA - Emulates a R6551 ACIA (Asynchronous Communications Interface Adapter)
  * 
+ * Simplified to match real R6551 hardware: single-byte TX/RX registers,
+ * no buffers, no baud rate timing (USB serial operates at USB speeds).
+ * 
  * Register Map:
  * $00: Data Register (read/write)
  * $01: Status Register (read) / Programmed Reset (write)
@@ -11,31 +14,24 @@ import { IO } from '../IO'
  */
 export class ACIA implements IO {
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
   transmit?: (data: number) => void
 
   // Registers
-  private dataRegister: number = 0
-  private statusRegister: number = 0x10  // Transmit Data Register Empty
+  private txRegister: number = 0
+  private rxRegister: number = 0
   private commandRegister: number = 0
   private controlRegister: number = 0
 
-  // Buffers
-  private transmitBuffer: number[] = []
-  private receiveBuffer: number[] = []
-
   // Status flags
+  private txRegEmpty: boolean = true
+  private rxRegFull: boolean = false
+  private txPending: boolean = false
+  private overrun: boolean = false
   private parityError: boolean = false
   private framingError: boolean = false
-  private overrun: boolean = false
   private irqFlag: boolean = false
   private echoMode: boolean = false
 
-  // Timing
-  private cycleCounter: number = 0
-  private baudRate: number = 115200
-
   /**
    * Read from ACIA register
    */
@@ -80,51 +76,32 @@ export class ACIA implements IO {
         break
       
       case 0x03: // Control Register
-        this.writeControl(data)
+        this.controlRegister = data & 0xFF
         break
     }
   }
 
   /**
-   * Read data from receive buffer
+   * Read data from receive register
    */
   private readData(): number {
-    if (this.receiveBuffer.length > 0) {
-      const data = this.receiveBuffer.shift()!
-      this.dataRegister = data
-      
-      // Update status: clear Receive Data Register Full
-      this.statusRegister &= ~0x08
-      
-      // Check for overrun if more data arrives
-      if (this.receiveBuffer.length === 0) {
-        this.overrun = false
-        this.statusRegister &= ~0x04
-      }
+    // Clear Receive Data Register Full
+    this.rxRegFull = false
+    this.overrun = false
 
-      // If more bytes remain in the buffer, re-assert IRQ so the BIOS services them
-      if (this.receiveBuffer.length > 0 && !(this.commandRegister & 0x02)) {
-        this.irqFlag = true
-        this.statusRegister |= 0x80
-      } else {
-        this.irqFlag = false
-        this.statusRegister &= ~0x80
-      }
+    // Clear IRQ if it was from RX
+    this.irqFlag = false
 
-      return data
-    }
-    
-    return this.dataRegister
+    return this.rxRegister
   }
 
   /**
-   * Write data to transmit buffer
+   * Write data to transmit register
    */
   private writeData(data: number): void {
-    this.transmitBuffer.push(data & 0xFF)
-    
-    // Clear Transmit Data Register Empty flag
-    this.statusRegister &= ~0x10
+    this.txRegister = data & 0xFF
+    this.txRegEmpty = false
+    this.txPending = true
   }
 
   /**
@@ -148,27 +125,26 @@ export class ACIA implements IO {
     if (this.overrun) status |= 0x04
     
     // Bit 3: Receive Data Register Full
-    if (this.receiveBuffer.length > 0) status |= 0x08
+    if (this.rxRegFull) status |= 0x08
     
     // Bit 4: Transmit Data Register Empty
-    if (this.transmitBuffer.length === 0) status |= 0x10
+    if (this.txRegEmpty) status |= 0x10
     
-    // Bit 5: Data Carrier Detect (DCD)
+    // Bit 5: Data Carrier Detect (DCD) - always connected
     status &= ~0x20
     
-    // Bit 6: Data Set Ready (DSR)
+    // Bit 6: Data Set Ready (DSR) - always ready
     status |= 0x40
     
     // Bit 7: Interrupt (IRQ)
     if (this.irqFlag) status |= 0x80
 
-    // Clear IRQ and error flags after building the status byte (R6551 spec)
+    // Clear IRQ and error flags after reading (R6551 spec)
     this.irqFlag = false
     this.parityError = false
     this.framingError = false
     this.overrun = false
 
-    this.statusRegister = status
     return status
   }
 
@@ -178,82 +154,16 @@ export class ACIA implements IO {
   private writeCommand(data: number): void {
     this.commandRegister = data & 0xFF
 
-    // Bits 0-1: DTR control
-    // const dtrControl = data & 0x03
-    
-    // Bit 1: Receiver Interrupt Request Disable (RIIE) — 0 = IRQ enabled, 1 = disabled (active low)
-    const receiveIRQEnabled = (data & 0x02) === 0
-    
-    // Bits 3-2: Transmitter Interrupt Control (TIC)
-    // const transmitControl = (data >> 2) & 0x03
-    
     // Bit 4: Echo Mode Enable (EME)
     this.echoMode = (data & 0x10) !== 0
-    
-    // Bits 6-7: Parity control
-    // const parityControl = (data >> 6) & 0x03
-
-    // Handle receive IRQ
-    if (receiveIRQEnabled && this.receiveBuffer.length > 0) {
-      this.irqFlag = true
-      this.statusRegister |= 0x80
-      this.raiseIRQ()
-    } else if (!receiveIRQEnabled) {
-      this.irqFlag = false
-      this.statusRegister &= ~0x80
-    }
-  }
-
-  /**
-   * Write to control register
-   */
-  private writeControl(data: number): void {
-    this.controlRegister = data & 0xFF
-
-    // Bits 0-3: Baud rate
-    const baudRateCode = data & 0x0F
-    this.baudRate = this.getBaudRate(baudRateCode)
-    
-    // Bit 4: Receiver clock source (internal/external)
-    const receiverClockSource = (data & 0x10) !== 0
-    
-    // Bits 5-6: Word length (5, 6, 7, or 8 bits)
-    const wordLength = ((data >> 5) & 0x03) + 5
-    
-    // Bit 7: Stop bits (1 or 2)
-    const stopBits = (data & 0x80) ? 2 : 1
-  }
-
-  /**
-   * Get baud rate from control register code
-   */
-  private getBaudRate(code: number): number {
-    const baudRates = [
-      115200,    // 0000 (actually 16x external clock, using 115200 as default)
-      50,      // 0001
-      75,      // 0010
-      110,     // 0011
-      135,     // 0100
-      150,     // 0101
-      300,     // 0110
-      600,     // 0111
-      1200,    // 1000
-      1800,    // 1001
-      2400,    // 1010
-      3600,    // 1011
-      4800,    // 1100
-      7200,    // 1101
-      9600,    // 1110
-      19200    // 1111
-    ]
-    return baudRates[code] || 115200
   }
 
   /**
    * Programmed reset
    */
   private programmedReset(): void {
-    this.statusRegister = 0x10  // Transmit Data Register Empty
+    this.txRegEmpty = true
+    this.txPending = false
     this.parityError = false
     this.framingError = false
     this.overrun = false
@@ -261,100 +171,71 @@ export class ACIA implements IO {
   }
 
   /**
-   * Tick - emulate ACIA timing
+   * Tick - process TX/RX each cycle, return interrupt status
    */
-  tick(frequency: number): void {
-    // Re-evaluate receive interrupt condition.
-    // After readStatus() clears irqFlag, the IRQ must be re-asserted if
-    // the underlying condition (RDRF + receive IRQ enabled) is still active.
-    if (!(this.commandRegister & 0x02) && this.receiveBuffer.length > 0) {
-      this.irqFlag = true
-    }
-
-    if (this.irqFlag) {
-      this.raiseIRQ()
-    }
-
-    this.cycleCounter++
+  tick(frequency: number): number {
+    // Handle pending transmit - send immediately (no baud timing)
+    if (this.txPending) {
+      this.txPending = false
 
-    // Calculate cycles per byte: (CPU_CLOCK / baud_rate) * bits_per_frame
-    // Assuming 10 bits per frame (1 start + 8 data + 1 stop)
-    const cyclesPerByte = Math.floor((frequency / this.baudRate) * 10)
-
-    // Simulate transmission based on actual baud rate
-    if (this.cycleCounter >= cyclesPerByte && this.transmitBuffer.length > 0) {
-      this.cycleCounter = 0
-      
-      // Transmit one byte
-      const byte = this.transmitBuffer.shift()
-      
-      if (byte !== undefined && this.transmit) {
-        this.transmit(byte)
+      if (this.transmit) {
+        this.transmit(this.txRegister)
       }
 
-      // Set Transmit Data Register Empty if buffer is empty
-      if (this.transmitBuffer.length === 0) {
-        this.statusRegister |= 0x10
+      this.txRegEmpty = true
 
-        // Trigger transmit complete IRQ if enabled (bits 3-2 = 01 means TxIRQ on TDRE)
-        if ((this.commandRegister & 0x0C) === 0x04) {
-          this.irqFlag = true
-          this.statusRegister |= 0x80
-          this.raiseIRQ()
-        }
+      // Trigger transmit complete IRQ if enabled (TIC bits 3-2 = 01)
+      if ((this.commandRegister & 0x0C) === 0x04) {
+        this.irqFlag = true
       }
+
+      // Echo mode: received data echoed back
+      // (echo of transmitted data is handled in onData)
     }
+
+    // Return IRQ status
+    return this.irqFlag ? 0x80 : 0
   }
 
   /**
    * Reset the ACIA
    */
   reset(coldStart: boolean): void {
-    this.dataRegister = 0
-    this.statusRegister = 0x10  // Transmit Data Register Empty
+    this.txRegister = 0
+    this.rxRegister = 0
     this.commandRegister = 0
     this.controlRegister = 0
-    
-    this.transmitBuffer = []
-    this.receiveBuffer = []
-    
+
+    this.txRegEmpty = true
+    this.rxRegFull = false
+    this.txPending = false
+    this.overrun = false
     this.parityError = false
     this.framingError = false
-    this.overrun = false
     this.irqFlag = false
     this.echoMode = false
-    
-    this.cycleCounter = 0
-    this.baudRate = 115200
   }
 
   /**
    * Receive data from external source
    */
   onData(data: number): void {
-    if (this.receiveBuffer.length > 0) {
+    if (this.rxRegFull) {
       // Overrun: new data arrived before the previous byte was read
       this.overrun = true
-      this.statusRegister |= 0x04
     }
 
-    this.receiveBuffer.push(data & 0xFF)
-    
-    // Set Receive Data Register Full flag
-    this.statusRegister |= 0x08
+    this.rxRegister = data & 0xFF
+    this.rxRegFull = true
     
     // Trigger receive IRQ if enabled (bit 1 = 0 means enabled, active low)
     if (!(this.commandRegister & 0x02)) {
       this.irqFlag = true
-      this.statusRegister |= 0x80
-      this.raiseIRQ()
     }
 
     // Echo mode: automatically transmit received data
-    if (this.echoMode) {
-      this.transmitBuffer.push(data & 0xFF)
-      // Clear Transmit Data Register Empty flag
-      this.statusRegister &= ~0x10
+    if (this.echoMode && this.transmit) {
+      this.transmit(data & 0xFF)
     }
   }
 }

package/src/components/IO/Attachments/KeyboardEncoderAttachment.ts

@@ -86,7 +86,7 @@ export class KeyboardEncoderAttachment extends AttachmentBase {
   // 'A' = PS/2 encoder on Port A (CA1 IRQ only)
   // 'B' = Matrix encoder on Port B (CB1 IRQ only)
   // 'both' = both ports active (default)
-  activePort: 'A' | 'B' | 'both' = 'both'
+  activePort: 'A' | 'B' | 'both' = 'B'
 
   // Port A state
   private asciiDataA: number = 0x00

package/src/components/IO/Empty.ts

@@ -2,15 +2,12 @@ import { IO } from '../IO'
 
 export class Empty implements IO {
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
-
   read(address: number): number {
     return 0
   }
 
   write(address: number, data: number): void {}
-  tick(frequency: number): void {}
+  tick(frequency: number): number { return 0 }
   reset(coldStart: boolean): void {}
 
 }

package/src/components/IO/RAMBank.ts

@@ -20,40 +20,29 @@ export class RAMBank implements IO {
   data: number[] = [...Array(RAMBank.TOTAL_SIZE)].fill(0x00)
   currentBank: number = 0
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
-
   /**
-   * Read from RAM or bank control register
+   * Read from RAM - all addresses read from the data array
    */
   read(address: number): number {
-    // Reading from bank control register returns current bank number
-    if (address === RAMBank.BANK_CONTROL_REGISTER) {
-      return this.currentBank
-    }
-    
-    // Calculate actual address in RAM: bank * bank_size + offset and return data
     return this.data[this.currentBank * RAMBank.BANK_SIZE + address]
   }
 
   /**
    * Write to RAM or bank control register
+   * Writing to $3FF sets the bank AND writes through to the new bank's data
    */
   write(address: number, data: number): void {
-    // Writing to bank control register switches banks
     if (address === RAMBank.BANK_CONTROL_REGISTER) {
-      this.currentBank = data & 0xFF // Ensure 0-255 range
-      return
+      this.currentBank = data & 0xFF
     }
     
-    // Calculate actual address in RAM: bank * bank_size + offset and store data
     this.data[this.currentBank * RAMBank.BANK_SIZE + address] = data & 0xFF
   }
   
   /**
    * Tick - no timing behavior for RAM
    */
-  tick(frequency: number): void {}
+  tick(frequency: number): number { return 0 }
   
   /**
    * Reset the RAM card

package/src/components/IO/RTC.ts

@@ -26,8 +26,6 @@ import { IO } from '../IO'
  * 0x13: RAM Data (Extended RAM Data at address pointed to by 0x10)
  */
 export class RTC implements IO {
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
 
   // RTC Registers (user-visible)
   private userSeconds: number = 0        // 0x00
@@ -61,6 +59,7 @@ export class RTC implements IO {
   private watchdog2: number = 0      // 0x0D (0.1 Second and Second)
   private watchdogCounterCentis: number = 0
   private watchdogCycleCounter: number = 0
+  private nmiPending: boolean = false
 
   // Control registers
   private controlA: number = 0       // 0x0E
@@ -261,7 +260,6 @@ export class RTC implements IO {
     if ((this.controlA & flagMask) === 0) return
     if ((this.controlB & enableMask) === 0) return
     this.controlA |= 0x01 // Set IRQF flag (bit 0)
-    this.raiseIRQ()
   }
 
   private setKickstartFlag(): void {
@@ -304,7 +302,7 @@ export class RTC implements IO {
     } else {
       // WDS=1 steers watchdog to reset; emulate by clearing WDE
       this.controlB &= ~0x02
-      this.raiseNMI()
+      this.nmiPending = true
     }
   }
 
@@ -449,7 +447,7 @@ export class RTC implements IO {
 
 
 
-  tick(frequency: number, cycles: number = 1): void {
+  tick(frequency: number): number {
     this.cpuFrequency = frequency > 0 ? frequency : 1000000
 
     const teEnabled = (this.controlB & 0x80) !== 0
@@ -457,12 +455,17 @@ export class RTC implements IO {
     if ((this.monthControl & 0x80) !== 0) {
       // EOSC=1: oscillator disabled (DS1511Y+ active-low enable)
       this.stepWatchdog()
-      return
+      let status = (this.controlA & 0x01) ? 0x80 : 0
+      if (this.nmiPending) {
+        status |= 0x40
+        this.nmiPending = false
+      }
+      return status
     }
 
     // Advance the clock by counting CPU cycles.
     // One emulated second = cpuFrequency cycles.
-    this.cycleAccumulator += cycles
+    this.cycleAccumulator++
     while (this.cycleAccumulator >= this.cpuFrequency) {
       this.cycleAccumulator -= this.cpuFrequency
       this.incrementTime()
@@ -482,6 +485,14 @@ export class RTC implements IO {
     }
 
     this.stepWatchdog()
+
+    // Return interrupt status: bit 7 = IRQ, bit 6 = NMI
+    let status = (this.controlA & 0x01) ? 0x80 : 0
+    if (this.nmiPending) {
+      status |= 0x40
+      this.nmiPending = false
+    }
+    return status
   }
 
   reset(coldStart: boolean): void {

package/src/components/IO/Sound.ts

@@ -40,9 +40,6 @@ export const SID_CLOCK_PAL = 985248
 /** Number of SID registers */
 const NUM_REGISTERS = 29
 
-/** Cycles per tick from Machine.ts ioTickInterval */
-const CYCLES_PER_TICK = 128
-
 // Register offsets within each voice (relative to voice base)
 const REG_FREQ_LO = 0
 const REG_FREQ_HI = 1
@@ -162,9 +159,6 @@ export class SIDVoice {
 
 export class Sound implements IO {
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
-
   /** Callback to push audio samples to the host emulator */
   pushSamples?: (samples: Float32Array) => void
 
@@ -202,7 +196,7 @@ export class Sound implements IO {
   sidClock: number = SID_CLOCK_NTSC
 
   /** Internal sample buffer for pushing to host */
-  private sampleBuffer: Float32Array = new Float32Array(4096)
+  private sampleBuffer: Float32Array = new Float32Array(128)
   private sampleBufferIndex: number = 0
 
   // ================================================================
@@ -247,35 +241,28 @@ export class Sound implements IO {
     }
   }
 
-  tick(frequency: number): void {
+  tick(frequency: number): number {
     // SID clock runs at the CPU clock rate
     this.sidClock = frequency
 
-    // Each tick represents CYCLES_PER_TICK SID clock cycles
-    const cycles = CYCLES_PER_TICK
-
-    for (let c = 0; c < cycles; c++) {
-      this.clockOneCycle()
+    // Each tick represents 1 SID clock cycle
+    this.clockOneCycle()
 
-      // Sample rate conversion: accumulate and downsample
-      this.cycleAccumulator += this.sampleRate
-      if (this.cycleAccumulator >= this.sidClock) {
-        this.cycleAccumulator -= this.sidClock
+    // Sample rate conversion: accumulate and downsample
+    this.cycleAccumulator += this.sampleRate
+    if (this.cycleAccumulator >= this.sidClock) {
+      this.cycleAccumulator -= this.sidClock
 
-        const sample = this.generateSample()
-        this.sampleBuffer[this.sampleBufferIndex++] = sample
+      const sample = this.generateSample()
+      this.sampleBuffer[this.sampleBufferIndex++] = sample
 
-        // Buffer full - push to host
-        if (this.sampleBufferIndex >= this.sampleBuffer.length) {
-          this.flushSampleBuffer()
-        }
+      // Buffer full - push to host
+      if (this.sampleBufferIndex >= this.sampleBuffer.length) {
+        this.flushSampleBuffer()
       }
     }
 
-    // Flush remaining samples
-    if (this.sampleBufferIndex > 0) {
-      this.flushSampleBuffer()
-    }
+    return 0
   }
 
   reset(coldStart: boolean): void {

package/src/components/IO/Storage.ts

@@ -65,9 +65,6 @@ export class Storage implements IO {
   private isIdentifying: boolean = false
   private isTransferring: boolean = false
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
-
   constructor() {
     // Initialize storage and identity buffers
     this.storage = new Uint8Array(Storage.STORAGE_SIZE)
@@ -129,8 +126,8 @@ export class Storage implements IO {
     }
   }
 
-  tick(frequency: number): void {
-    // No timing behavior needed for this implementation
+  tick(frequency: number): number {
+    return 0
   }
 
   reset(coldStart: boolean): void {

package/src/components/IO/VIA.ts

@@ -78,9 +78,6 @@ export class VIA implements IO {
   private portA_attachmentCount: number = 0
   private portB_attachmentCount: number = 0
 
-  raiseIRQ = () => {}
-  raiseNMI = () => {}
-
   constructor() {
     this.reset(true)
   }
@@ -333,12 +330,12 @@ export class VIA implements IO {
     }
   }
 
-  tick(frequency: number, cycles: number = 1): void {
+  tick(frequency: number): number {
     this.tickCounter++
 
     // Update Timer 1
     if (this.T1_running && this.regT1C > 0) {
-      this.regT1C -= cycles
+      this.regT1C--
       if (this.regT1C <= 0) {
         this.setIRQFlag(VIA.IRQ_T1)
 
@@ -359,7 +356,7 @@ export class VIA implements IO {
 
     // Update Timer 2
     if (this.T2_running && this.regT2C > 0) {
-      this.regT2C -= cycles
+      this.regT2C--
       if (this.regT2C <= 0) {
         this.setIRQFlag(VIA.IRQ_T2)
         this.regT2C = 0
@@ -401,10 +398,11 @@ export class VIA implements IO {
       }
     }
 
-    // Raise IRQ if any enabled interrupt is active
+    // Return IRQ status if any enabled interrupt is active
     if (this.regIFR & this.regIER & 0x7F) {
-      this.raiseIRQ()
+      return 0x80
     }
+    return 0
   }
 
   private updateIRQ(): void {