ac6502 1.10.0 → 1.11.0

package/dist/components/IO/ACIA.d.ts

@@ -2,6 +2,9 @@ import { IO } from '../IO';
 /**
  * ACIA - Emulates a R6551 ACIA (Asynchronous Communications Interface Adapter)
  *
+ * Simplified to match real R6551 hardware: single-byte TX/RX registers,
+ * no buffers, no baud rate timing (USB serial operates at USB speeds).
+ *
  * Register Map:
  * $00: Data Register (read/write)
  * $01: Status Register (read) / Programmed Reset (write)
@@ -9,22 +12,19 @@ import { IO } from '../IO';
  * $03: Control Register (write)
  */
 export declare class ACIA implements IO {
-    raiseIRQ: () => void;
-    raiseNMI: () => void;
     transmit?: (data: number) => void;
-    private dataRegister;
-    private statusRegister;
+    private txRegister;
+    private rxRegister;
     private commandRegister;
     private controlRegister;
-    private transmitBuffer;
-    private receiveBuffer;
+    private txRegEmpty;
+    private rxRegFull;
+    private txPending;
+    private overrun;
     private parityError;
     private framingError;
-    private overrun;
     private irqFlag;
     private echoMode;
-    private cycleCounter;
-    private baudRate;
     /**
      * Read from ACIA register
      */
@@ -34,11 +34,11 @@ export declare class ACIA implements IO {
      */
     write(address: number, data: number): void;
     /**
-     * Read data from receive buffer
+     * Read data from receive register
      */
     private readData;
     /**
-     * Write data to transmit buffer
+     * Write data to transmit register
      */
     private writeData;
     /**
@@ -54,22 +54,14 @@ export declare class ACIA implements IO {
      * Write to command register
      */
     private writeCommand;
-    /**
-     * Write to control register
-     */
-    private writeControl;
-    /**
-     * Get baud rate from control register code
-     */
-    private getBaudRate;
     /**
      * Programmed reset
      */
     private programmedReset;
     /**
-     * Tick - emulate ACIA timing
+     * Tick - process TX/RX each cycle, return interrupt status
      */
-    tick(frequency: number): void;
+    tick(frequency: number): number;
     /**
      * Reset the ACIA
      */

package/dist/components/IO/ACIA.js

@@ -4,6 +4,9 @@ exports.ACIA = void 0;
 /**
  * ACIA - Emulates a R6551 ACIA (Asynchronous Communications Interface Adapter)
  *
+ * Simplified to match real R6551 hardware: single-byte TX/RX registers,
+ * no buffers, no baud rate timing (USB serial operates at USB speeds).
+ *
  * Register Map:
  * $00: Data Register (read/write)
  * $01: Status Register (read) / Programmed Reset (write)
@@ -12,25 +15,20 @@ exports.ACIA = void 0;
  */
 class ACIA {
     constructor() {
-        this.raiseIRQ = () => { };
-        this.raiseNMI = () => { };
         // Registers
-        this.dataRegister = 0;
-        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.txRegister = 0;
+        this.rxRegister = 0;
         this.commandRegister = 0;
         this.controlRegister = 0;
-        // Buffers
-        this.transmitBuffer = [];
-        this.receiveBuffer = [];
         // Status flags
+        this.txRegEmpty = true;
+        this.rxRegFull = false;
+        this.txPending = false;
+        this.overrun = false;
         this.parityError = false;
         this.framingError = false;
-        this.overrun = false;
         this.irqFlag = false;
         this.echoMode = false;
-        // Timing
-        this.cycleCounter = 0;
-        this.baudRate = 115200;
     }
     /**
      * Read from ACIA register
@@ -66,44 +64,28 @@ class ACIA {
                 this.writeCommand(data);
                 break;
             case 0x03: // Control Register
-                this.writeControl(data);
+                this.controlRegister = data & 0xFF;
                 break;
         }
     }
     /**
-     * Read data from receive buffer
+     * Read data from receive register
      */
     readData() {
-        if (this.receiveBuffer.length > 0) {
-            const data = this.receiveBuffer.shift();
-            this.dataRegister = data;
-            // Update status: clear Receive Data Register Full
-            this.statusRegister &= ~0x08;
-            // Check for overrun if more data arrives
-            if (this.receiveBuffer.length === 0) {
-                this.overrun = false;
-                this.statusRegister &= ~0x04;
-            }
-            // If more bytes remain in the buffer, re-assert IRQ so the BIOS services them
-            if (this.receiveBuffer.length > 0 && !(this.commandRegister & 0x02)) {
-                this.irqFlag = true;
-                this.statusRegister |= 0x80;
-            }
-            else {
-                this.irqFlag = false;
-                this.statusRegister &= ~0x80;
-            }
-            return data;
-        }
-        return this.dataRegister;
+        // Clear Receive Data Register Full
+        this.rxRegFull = false;
+        this.overrun = false;
+        // Clear IRQ if it was from RX
+        this.irqFlag = false;
+        return this.rxRegister;
     }
     /**
-     * Write data to transmit buffer
+     * Write data to transmit register
      */
     writeData(data) {
-        this.transmitBuffer.push(data & 0xFF);
-        // Clear Transmit Data Register Empty flag
-        this.statusRegister &= ~0x10;
+        this.txRegister = data & 0xFF;
+        this.txRegEmpty = false;
+        this.txPending = true;
     }
     /**
      * Read status register
@@ -125,24 +107,23 @@ class ACIA {
         if (this.overrun)
             status |= 0x04;
         // Bit 3: Receive Data Register Full
-        if (this.receiveBuffer.length > 0)
+        if (this.rxRegFull)
             status |= 0x08;
         // Bit 4: Transmit Data Register Empty
-        if (this.transmitBuffer.length === 0)
+        if (this.txRegEmpty)
             status |= 0x10;
-        // Bit 5: Data Carrier Detect (DCD)
+        // Bit 5: Data Carrier Detect (DCD) - always connected
         status &= ~0x20;
-        // Bit 6: Data Set Ready (DSR)
+        // Bit 6: Data Set Ready (DSR) - always ready
         status |= 0x40;
         // Bit 7: Interrupt (IRQ)
         if (this.irqFlag)
             status |= 0x80;
-        // Clear IRQ and error flags after building the status byte (R6551 spec)
+        // Clear IRQ and error flags after reading (R6551 spec)
         this.irqFlag = false;
         this.parityError = false;
         this.framingError = false;
         this.overrun = false;
-        this.statusRegister = status;
         return status;
     }
     /**
@@ -150,154 +131,75 @@ class ACIA {
      */
     writeCommand(data) {
         this.commandRegister = data & 0xFF;
-        // Bits 0-1: DTR control
-        // const dtrControl = data & 0x03
-        // Bit 1: Receiver Interrupt Request Disable (RIIE) — 0 = IRQ enabled, 1 = disabled (active low)
-        const receiveIRQEnabled = (data & 0x02) === 0;
-        // Bits 3-2: Transmitter Interrupt Control (TIC)
-        // const transmitControl = (data >> 2) & 0x03
         // Bit 4: Echo Mode Enable (EME)
         this.echoMode = (data & 0x10) !== 0;
-        // Bits 6-7: Parity control
-        // const parityControl = (data >> 6) & 0x03
-        // Handle receive IRQ
-        if (receiveIRQEnabled && this.receiveBuffer.length > 0) {
-            this.irqFlag = true;
-            this.statusRegister |= 0x80;
-            this.raiseIRQ();
-        }
-        else if (!receiveIRQEnabled) {
-            this.irqFlag = false;
-            this.statusRegister &= ~0x80;
-        }
-    }
-    /**
-     * Write to control register
-     */
-    writeControl(data) {
-        this.controlRegister = data & 0xFF;
-        // Bits 0-3: Baud rate
-        const baudRateCode = data & 0x0F;
-        this.baudRate = this.getBaudRate(baudRateCode);
-        // Bit 4: Receiver clock source (internal/external)
-        const receiverClockSource = (data & 0x10) !== 0;
-        // Bits 5-6: Word length (5, 6, 7, or 8 bits)
-        const wordLength = ((data >> 5) & 0x03) + 5;
-        // Bit 7: Stop bits (1 or 2)
-        const stopBits = (data & 0x80) ? 2 : 1;
-    }
-    /**
-     * Get baud rate from control register code
-     */
-    getBaudRate(code) {
-        const baudRates = [
-            115200, // 0000 (actually 16x external clock, using 115200 as default)
-            50, // 0001
-            75, // 0010
-            110, // 0011
-            135, // 0100
-            150, // 0101
-            300, // 0110
-            600, // 0111
-            1200, // 1000
-            1800, // 1001
-            2400, // 1010
-            3600, // 1011
-            4800, // 1100
-            7200, // 1101
-            9600, // 1110
-            19200 // 1111
-        ];
-        return baudRates[code] || 115200;
     }
     /**
      * Programmed reset
      */
     programmedReset() {
-        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.txRegEmpty = true;
+        this.txPending = false;
         this.parityError = false;
         this.framingError = false;
         this.overrun = false;
         this.irqFlag = false;
     }
     /**
-     * Tick - emulate ACIA timing
+     * Tick - process TX/RX each cycle, return interrupt status
      */
     tick(frequency) {
-        // Re-evaluate receive interrupt condition.
-        // After readStatus() clears irqFlag, the IRQ must be re-asserted if
-        // the underlying condition (RDRF + receive IRQ enabled) is still active.
-        if (!(this.commandRegister & 0x02) && this.receiveBuffer.length > 0) {
-            this.irqFlag = true;
-        }
-        if (this.irqFlag) {
-            this.raiseIRQ();
-        }
-        this.cycleCounter++;
-        // Calculate cycles per byte: (CPU_CLOCK / baud_rate) * bits_per_frame
-        // Assuming 10 bits per frame (1 start + 8 data + 1 stop)
-        const cyclesPerByte = Math.floor((frequency / this.baudRate) * 10);
-        // Simulate transmission based on actual baud rate
-        if (this.cycleCounter >= cyclesPerByte && this.transmitBuffer.length > 0) {
-            this.cycleCounter = 0;
-            // Transmit one byte
-            const byte = this.transmitBuffer.shift();
-            if (byte !== undefined && this.transmit) {
-                this.transmit(byte);
+        // Handle pending transmit - send immediately (no baud timing)
+        if (this.txPending) {
+            this.txPending = false;
+            if (this.transmit) {
+                this.transmit(this.txRegister);
             }
-            // Set Transmit Data Register Empty if buffer is empty
-            if (this.transmitBuffer.length === 0) {
-                this.statusRegister |= 0x10;
-                // Trigger transmit complete IRQ if enabled (bits 3-2 = 01 means TxIRQ on TDRE)
-                if ((this.commandRegister & 0x0C) === 0x04) {
-                    this.irqFlag = true;
-                    this.statusRegister |= 0x80;
-                    this.raiseIRQ();
-                }
+            this.txRegEmpty = true;
+            // Trigger transmit complete IRQ if enabled (TIC bits 3-2 = 01)
+            if ((this.commandRegister & 0x0C) === 0x04) {
+                this.irqFlag = true;
             }
+            // Echo mode: received data echoed back
+            // (echo of transmitted data is handled in onData)
         }
+        // Return IRQ status
+        return this.irqFlag ? 0x80 : 0;
     }
     /**
      * Reset the ACIA
      */
     reset(coldStart) {
-        this.dataRegister = 0;
-        this.statusRegister = 0x10; // Transmit Data Register Empty
+        this.txRegister = 0;
+        this.rxRegister = 0;
         this.commandRegister = 0;
         this.controlRegister = 0;
-        this.transmitBuffer = [];
-        this.receiveBuffer = [];
+        this.txRegEmpty = true;
+        this.rxRegFull = false;
+        this.txPending = false;
+        this.overrun = false;
         this.parityError = false;
         this.framingError = false;
-        this.overrun = false;
         this.irqFlag = false;
         this.echoMode = false;
-        this.cycleCounter = 0;
-        this.baudRate = 115200;
     }
     /**
      * Receive data from external source
      */
     onData(data) {
-        if (this.receiveBuffer.length > 0) {
+        if (this.rxRegFull) {
             // Overrun: new data arrived before the previous byte was read
             this.overrun = true;
-            this.statusRegister |= 0x04;
         }
-        this.receiveBuffer.push(data & 0xFF);
-        // Set Receive Data Register Full flag
-        this.statusRegister |= 0x08;
+        this.rxRegister = data & 0xFF;
+        this.rxRegFull = true;
         // Trigger receive IRQ if enabled (bit 1 = 0 means enabled, active low)
         if (!(this.commandRegister & 0x02)) {
             this.irqFlag = true;
-            this.statusRegister |= 0x80;
-            this.raiseIRQ();
         }
         // Echo mode: automatically transmit received data
-        if (this.echoMode) {
-            this.transmitBuffer.push(data & 0xFF);
-            // Clear Transmit Data Register Empty flag
-            this.statusRegister &= ~0x10;
+        if (this.echoMode && this.transmit) {
+            this.transmit(data & 0xFF);
         }
     }
 }

package/dist/components/IO/ACIA.js.map

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+{"version":3,"file":"ACIA.js","sourceRoot":"","sources":["../../../src/components/IO/ACIA.ts"],"names":[],"mappings":";;;AAEA;;;;;;;;;;;GAWG;AACH,MAAa,IAAI;IAAjB;QAIE,YAAY;QACJ,eAAU,GAAW,CAAC,CAAA;QACtB,eAAU,GAAW,CAAC,CAAA;QACtB,oBAAe,GAAW,CAAC,CAAA;QAC3B,oBAAe,GAAW,CAAC,CAAA;QAEnC,eAAe;QACP,eAAU,GAAY,IAAI,CAAA;QAC1B,cAAS,GAAY,KAAK,CAAA;QAC1B,cAAS,GAAY,KAAK,CAAA;QAC1B,YAAO,GAAY,KAAK,CAAA;QACxB,gBAAW,GAAY,KAAK,CAAA;QAC5B,iBAAY,GAAY,KAAK,CAAA;QAC7B,YAAO,GAAY,KAAK,CAAA;QACxB,aAAQ,GAAY,KAAK,CAAA;IAgNnC,CAAC;IA9MC;;OAEG;IACH,IAAI,CAAC,OAAe;QAClB,MAAM,QAAQ,GAAG,OAAO,GAAG,IAAI,CAAA;QAE/B,QAAQ,QAAQ,EAAE,CAAC;YACjB,KAAK,IAAI,EAAE,gBAAgB;gBACzB,OAAO,IAAI,CAAC,QAAQ,EAAE,CAAA;YAExB,KAAK,IAAI,EAAE,kBAAkB;gBAC3B,OAAO,IAAI,CAAC,UAAU,EAAE,CAAA;YAE1B,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,OAAO,IAAI,CAAC,eAAe,CAAA;YAE7B,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,OAAO,IAAI,CAAC,eAAe,CAAA;YAE7B;gBACE,OAAO,CAAC,CAAA;QACZ,CAAC;IACH,CAAC;IAED;;OAEG;IACH,KAAK,CAAC,OAAe,EAAE,IAAY;QACjC,MAAM,QAAQ,GAAG,OAAO,GAAG,IAAI,CAAA;QAE/B,QAAQ,QAAQ,EAAE,CAAC;YACjB,KAAK,IAAI,EAAE,gBAAgB;gBACzB,IAAI,CAAC,SAAS,CAAC,IAAI,CAAC,CAAA;gBACpB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,eAAe,EAAE,CAAA;gBACtB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,YAAY,CAAC,IAAI,CAAC,CAAA;gBACvB,MAAK;YAEP,KAAK,IAAI,EAAE,mBAAmB;gBAC5B,IAAI,CAAC,eAAe,GAAG,IAAI,GAAG,IAAI,CAAA;gBAClC,MAAK;QACT,CAAC;IACH,CAAC;IAED;;OAEG;IACK,QAAQ;QACd,mCAAmC;QACnC,IAAI,CAAC,SAAS,GAAG,KAAK,CAAA;QACtB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QAEpB,8BAA8B;QAC9B,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QAEpB,OAAO,IAAI,CAAC,UAAU,CAAA;IACxB,CAAC;IAED;;OAEG;IACK,SAAS,CAAC,IAAY;QAC5B,IAAI,CAAC,UAAU,GAAG,IAAI,GAAG,IAAI,CAAA;QAC7B,IAAI,CAAC,UAAU,GAAG,KAAK,CAAA;QACvB,IAAI,CAAC,SAAS,GAAG,IAAI,CAAA;IACvB,CAAC;IAED;;;;;;;OAOG;IACK,UAAU;QAChB,IAAI,MAAM,GAAG,CAAC,CAAA;QAEd,sBAAsB;QACtB,IAAI,IAAI,CAAC,WAAW;YAAE,MAAM,IAAI,IAAI,CAAA;QAEpC,uBAAuB;QACvB,IAAI,IAAI,CAAC,YAAY;YAAE,MAAM,IAAI,IAAI,CAAA;QAErC,iBAAiB;QACjB,IAAI,IAAI,CAAC,OAAO;YAAE,MAAM,IAAI,IAAI,CAAA;QAEhC,oCAAoC;QACpC,IAAI,IAAI,CAAC,SAAS;YAAE,MAAM,IAAI,IAAI,CAAA;QAElC,sCAAsC;QACtC,IAAI,IAAI,CAAC,UAAU;YAAE,MAAM,IAAI,IAAI,CAAA;QAEnC,sDAAsD;QACtD,MAAM,IAAI,CAAC,IAAI,CAAA;QAEf,6CAA6C;QAC7C,MAAM,IAAI,IAAI,CAAA;QAEd,yBAAyB;QACzB,IAAI,IAAI,CAAC,OAAO;YAAE,MAAM,IAAI,IAAI,CAAA;QAEhC,uDAAuD;QACvD,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QACpB,IAAI,CAAC,WAAW,GAAG,KAAK,CAAA;QACxB,IAAI,CAAC,YAAY,GAAG,KAAK,CAAA;QACzB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QAEpB,OAAO,MAAM,CAAA;IACf,CAAC;IAED;;OAEG;IACK,YAAY,CAAC,IAAY;QAC/B,IAAI,CAAC,eAAe,GAAG,IAAI,GAAG,IAAI,CAAA;QAElC,gCAAgC;QAChC,IAAI,CAAC,QAAQ,GAAG,CAAC,IAAI,GAAG,IAAI,CAAC,KAAK,CAAC,CAAA;IACrC,CAAC;IAED;;OAEG;IACK,eAAe;QACrB,IAAI,CAAC,UAAU,GAAG,IAAI,CAAA;QACtB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAA;QACtB,IAAI,CAAC,WAAW,GAAG,KAAK,CAAA;QACxB,IAAI,CAAC,YAAY,GAAG,KAAK,CAAA;QACzB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QACpB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;IACtB,CAAC;IAED;;OAEG;IACH,IAAI,CAAC,SAAiB;QACpB,8DAA8D;QAC9D,IAAI,IAAI,CAAC,SAAS,EAAE,CAAC;YACnB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAA;YAEtB,IAAI,IAAI,CAAC,QAAQ,EAAE,CAAC;gBAClB,IAAI,CAAC,QAAQ,CAAC,IAAI,CAAC,UAAU,CAAC,CAAA;YAChC,CAAC;YAED,IAAI,CAAC,UAAU,GAAG,IAAI,CAAA;YAEtB,+DAA+D;YAC/D,IAAI,CAAC,IAAI,CAAC,eAAe,GAAG,IAAI,CAAC,KAAK,IAAI,EAAE,CAAC;gBAC3C,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;YACrB,CAAC;YAED,uCAAuC;YACvC,kDAAkD;QACpD,CAAC;QAED,oBAAoB;QACpB,OAAO,IAAI,CAAC,OAAO,CAAC,CAAC,CAAC,IAAI,CAAC,CAAC,CAAC,CAAC,CAAA;IAChC,CAAC;IAED;;OAEG;IACH,KAAK,CAAC,SAAkB;QACtB,IAAI,CAAC,UAAU,GAAG,CAAC,CAAA;QACnB,IAAI,CAAC,UAAU,GAAG,CAAC,CAAA;QACnB,IAAI,CAAC,eAAe,GAAG,CAAC,CAAA;QACxB,IAAI,CAAC,eAAe,GAAG,CAAC,CAAA;QAExB,IAAI,CAAC,UAAU,GAAG,IAAI,CAAA;QACtB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAA;QACtB,IAAI,CAAC,SAAS,GAAG,KAAK,CAAA;QACtB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QACpB,IAAI,CAAC,WAAW,GAAG,KAAK,CAAA;QACxB,IAAI,CAAC,YAAY,GAAG,KAAK,CAAA;QACzB,IAAI,CAAC,OAAO,GAAG,KAAK,CAAA;QACpB,IAAI,CAAC,QAAQ,GAAG,KAAK,CAAA;IACvB,CAAC;IAED;;OAEG;IACH,MAAM,CAAC,IAAY;QACjB,IAAI,IAAI,CAAC,SAAS,EAAE,CAAC;YACnB,8DAA8D;YAC9D,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;QACrB,CAAC;QAED,IAAI,CAAC,UAAU,GAAG,IAAI,GAAG,IAAI,CAAA;QAC7B,IAAI,CAAC,SAAS,GAAG,IAAI,CAAA;QAErB,uEAAuE;QACvE,IAAI,CAAC,CAAC,IAAI,CAAC,eAAe,GAAG,IAAI,CAAC,EAAE,CAAC;YACnC,IAAI,CAAC,OAAO,GAAG,IAAI,CAAA;QACrB,CAAC;QAED,kDAAkD;QAClD,IAAI,IAAI,CAAC,QAAQ,IAAI,IAAI,CAAC,QAAQ,EAAE,CAAC;YACnC,IAAI,CAAC,QAAQ,CAAC,IAAI,GAAG,IAAI,CAAC,CAAA;QAC5B,CAAC;IACH,CAAC;CACF;AAlOD,oBAkOC"}

package/dist/components/IO/Attachments/KeyboardEncoderAttachment.js

@@ -90,7 +90,7 @@ class KeyboardEncoderAttachment extends Attachment_1.AttachmentBase {
         // 'A' = PS/2 encoder on Port A (CA1 IRQ only)
         // 'B' = Matrix encoder on Port B (CB1 IRQ only)
         // 'both' = both ports active (default)
-        this.activePort = 'both';
+        this.activePort = 'B';
         // Port A state
         this.asciiDataA = 0x00;
         this.dataReadyA = false;

package/dist/components/IO/Attachments/KeyboardEncoderAttachment.js.map

@@ -1 +1 @@
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package/dist/components/IO/Empty.d.ts

@@ -1,9 +1,7 @@
 import { IO } from '../IO';
 export declare class Empty implements IO {
-    raiseIRQ: () => void;
-    raiseNMI: () => void;
     read(address: number): number;
     write(address: number, data: number): void;
-    tick(frequency: number): void;
+    tick(frequency: number): number;
     reset(coldStart: boolean): void;
 }

package/dist/components/IO/Empty.js

@@ -2,15 +2,11 @@
 Object.defineProperty(exports, "__esModule", { value: true });
 exports.Empty = void 0;
 class Empty {
-    constructor() {
-        this.raiseIRQ = () => { };
-        this.raiseNMI = () => { };
-    }
     read(address) {
         return 0;
     }
     write(address, data) { }
-    tick(frequency) { }
+    tick(frequency) { return 0; }
     reset(coldStart) { }
 }
 exports.Empty = Empty;

package/dist/components/IO/Empty.js.map

@@ -1 +1 @@
-{"version":3,"file":"Empty.js","sourceRoot":"","sources":["../../../src/components/IO/Empty.ts"],"names":[],"mappings":";;;AAEA,MAAa,KAAK;IAAlB;QAEE,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;QACnB,aAAQ,GAAG,GAAG,EAAE,GAAE,CAAC,CAAA;IAUrB,CAAC;IARC,IAAI,CAAC,OAAe;QAClB,OAAO,CAAC,CAAA;IACV,CAAC;IAED,KAAK,CAAC,OAAe,EAAE,IAAY,IAAS,CAAC;IAC7C,IAAI,CAAC,SAAiB,IAAS,CAAC;IAChC,KAAK,CAAC,SAAkB,IAAS,CAAC;CAEnC;AAbD,sBAaC"}
+{"version":3,"file":"Empty.js","sourceRoot":"","sources":["../../../src/components/IO/Empty.ts"],"names":[],"mappings":";;;AAEA,MAAa,KAAK;IAEhB,IAAI,CAAC,OAAe;QAClB,OAAO,CAAC,CAAA;IACV,CAAC;IAED,KAAK,CAAC,OAAe,EAAE,IAAY,IAAS,CAAC;IAC7C,IAAI,CAAC,SAAiB,IAAY,OAAO,CAAC,CAAA,CAAC,CAAC;IAC5C,KAAK,CAAC,SAAkB,IAAS,CAAC;CAEnC;AAVD,sBAUC"}

package/dist/components/IO/RAMBank.d.ts

@@ -16,20 +16,19 @@ export declare class RAMBank implements IO {
     static BANK_CONTROL_REGISTER: number;
     data: number[];
     currentBank: number;
-    raiseIRQ: () => void;
-    raiseNMI: () => void;
     /**
-     * Read from RAM or bank control register
+     * Read from RAM - all addresses read from the data array
      */
     read(address: number): number;
     /**
      * Write to RAM or bank control register
+     * Writing to $3FF sets the bank AND writes through to the new bank's data
      */
     write(address: number, data: number): void;
     /**
      * Tick - no timing behavior for RAM
      */
-    tick(frequency: number): void;
+    tick(frequency: number): number;
     /**
      * Reset the RAM card
      */

package/dist/components/IO/RAMBank.js

@@ -15,36 +15,27 @@ class RAMBank {
     constructor() {
         this.data = [...Array(RAMBank.TOTAL_SIZE)].fill(0x00);
         this.currentBank = 0;
-        this.raiseIRQ = () => { };
-        this.raiseNMI = () => { };
     }
     /**
-     * Read from RAM or bank control register
+     * Read from RAM - all addresses read from the data array
      */
     read(address) {
-        // Reading from bank control register returns current bank number
-        if (address === RAMBank.BANK_CONTROL_REGISTER) {
-            return this.currentBank;
-        }
-        // Calculate actual address in RAM: bank * bank_size + offset and return data
         return this.data[this.currentBank * RAMBank.BANK_SIZE + address];
     }
     /**
      * Write to RAM or bank control register
+     * Writing to $3FF sets the bank AND writes through to the new bank's data
      */
     write(address, data) {
-        // Writing to bank control register switches banks
         if (address === RAMBank.BANK_CONTROL_REGISTER) {
-            this.currentBank = data & 0xFF; // Ensure 0-255 range
-            return;
+            this.currentBank = data & 0xFF;
         }
-        // Calculate actual address in RAM: bank * bank_size + offset and store data
         this.data[this.currentBank * RAMBank.BANK_SIZE + address] = data & 0xFF;
     }
     /**
      * Tick - no timing behavior for RAM
      */
-    tick(frequency) { }
+    tick(frequency) { return 0; }
     /**
      * Reset the RAM card
      */

package/dist/components/IO/RAMBank.js.map

@@ -1 +1 @@
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+{"version":3,"file":"RAMBank.js","sourceRoot":"","sources":["../../../src/components/IO/RAMBank.ts"],"names":[],"mappings":";;;AAEA;;;;;;;;;GASG;AACH,MAAa,OAAO;IAApB;QAOE,SAAI,GAAa,CAAC,GAAG,KAAK,CAAC,OAAO,CAAC,UAAU,CAAC,CAAC,CAAC,IAAI,CAAC,IAAI,CAAC,CAAA;QAC1D,gBAAW,GAAW,CAAC,CAAA;IAoCzB,CAAC;IAlCC;;OAEG;IACH,IAAI,CAAC,OAAe;QAClB,OAAO,IAAI,CAAC,IAAI,CAAC,IAAI,CAAC,WAAW,GAAG,OAAO,CAAC,SAAS,GAAG,OAAO,CAAC,CAAA;IAClE,CAAC;IAED;;;OAGG;IACH,KAAK,CAAC,OAAe,EAAE,IAAY;QACjC,IAAI,OAAO,KAAK,OAAO,CAAC,qBAAqB,EAAE,CAAC;YAC9C,IAAI,CAAC,WAAW,GAAG,IAAI,GAAG,IAAI,CAAA;QAChC,CAAC;QAED,IAAI,CAAC,IAAI,CAAC,IAAI,CAAC,WAAW,GAAG,OAAO,CAAC,SAAS,GAAG,OAAO,CAAC,GAAG,IAAI,GAAG,IAAI,CAAA;IACzE,CAAC;IAED;;OAEG;IACH,IAAI,CAAC,SAAiB,IAAY,OAAO,CAAC,CAAA,CAAC,CAAC;IAE5C;;OAEG;IACH,KAAK,CAAC,SAAkB;QACtB,IAAI,SAAS,EAAE,CAAC;YACd,IAAI,CAAC,WAAW,GAAG,CAAC,CAAA;YACpB,IAAI,CAAC,IAAI,CAAC,IAAI,CAAC,IAAI,CAAC,CAAA;QACtB,CAAC;IACH,CAAC;;AA1CH,0BA4CC;AA1CQ,kBAAU,GAAW,GAAG,GAAG,IAAI,AAArB,CAAqB,CAAC,aAAa;AAC7C,iBAAS,GAAW,IAAI,AAAf,CAAe,CAAC,cAAc;AACvC,iBAAS,GAAW,OAAO,CAAC,UAAU,GAAG,OAAO,CAAC,SAAS,AAAjD,CAAiD,CAAC,YAAY;AACvE,6BAAqB,GAAW,KAAK,AAAhB,CAAgB,CAAC,yBAAyB"}

package/dist/components/IO/RTC.d.ts

@@ -25,8 +25,6 @@ import { IO } from '../IO';
  * 0x13: RAM Data (Extended RAM Data at address pointed to by 0x10)
  */
 export declare class RTC implements IO {
-    raiseIRQ: () => void;
-    raiseNMI: () => void;
     private userSeconds;
     private userMinutes;
     private userHours;
@@ -52,6 +50,7 @@ export declare class RTC implements IO {
     private watchdog2;
     private watchdogCounterCentis;
     private watchdogCycleCounter;
+    private nmiPending;
     private controlA;
     private controlB;
     private ramAddress;
@@ -100,6 +99,6 @@ export declare class RTC implements IO {
     private stepWatchdog;
     read(address: number): number;
     write(address: number, data: number): void;
-    tick(frequency: number, cycles?: number): void;
+    tick(frequency: number): number;
     reset(coldStart: boolean): void;
 }