@zigc/lib 0.17.0-dev.76 → 0.17.0-dev.813

package/std/zig/llvm/bitcode_writer.zig

@@ -246,14 +246,14 @@ pub fn BitcodeWriter(comptime types: []const type) type {
 
                     try self.bitcode.writeBits(comptime abbrevId(Abbrev), abbrev_len);
 
-                    const fields = std.meta.fields(Abbrev);
+                    const field_names = comptime std.meta.fieldNames(Abbrev);
 
                     // This abbreviation might only contain literals
-                    if (fields.len == 0) return;
+                    if (field_names.len == 0) return;
 
                     comptime var field_index: usize = 0;
                     inline for (Abbrev.ops) |ty| {
-                        const param = @field(params, fields[field_index].name);
+                        const param = @field(params, field_names[field_index]);
                         switch (ty) {
                             .literal => continue,
                             .fixed => |len| try self.bitcode.writeBits(adapter.get(param), len),
@@ -296,7 +296,7 @@ pub fn BitcodeWriter(comptime types: []const type) type {
                             },
                         }
                         field_index += 1;
-                        if (field_index == fields.len) break;
+                        if (field_index == field_names.len) break;
                     }
                 }
 
@@ -404,7 +404,7 @@ fn charTo6Bit(c: u8) u8 {
 }
 
 fn BufType(comptime T: type, comptime min_len: usize) type {
-    return std.meta.Int(.unsigned, @max(min_len, @bitSizeOf(switch (@typeInfo(T)) {
+    return @Int(.unsigned, @max(min_len, @bitSizeOf(switch (@typeInfo(T)) {
         .comptime_int => u32,
         .int => |info| if (info.signedness == .unsigned)
             T
@@ -414,7 +414,7 @@ fn BufType(comptime T: type, comptime min_len: usize) type {
         .bool => u1,
         .@"struct" => |info| switch (info.layout) {
             .auto, .@"extern" => @compileError("Unsupported type: " ++ @typeName(T)),
-            .@"packed" => std.meta.Int(.unsigned, @bitSizeOf(T)),
+            .@"packed" => @Int(.unsigned, @bitSizeOf(T)),
         },
         else => @compileError("Unsupported type: " ++ @typeName(T)),
     })));
@@ -425,7 +425,7 @@ fn bufValue(value: anytype, comptime min_len: usize) BufType(@TypeOf(value), min
         .comptime_int, .int => @intCast(value),
         .@"enum" => @intFromEnum(value),
         .bool => @intFromBool(value),
-        .@"struct" => @intCast(@as(std.meta.Int(.unsigned, @bitSizeOf(@TypeOf(value))), @bitCast(value))),
+        .@"struct" => @intCast(@as(@Int(.unsigned, @bitSizeOf(@TypeOf(value))), @bitCast(value))),
         else => unreachable,
     };
 }

package/std/zig/llvm/ir.zig

@@ -235,7 +235,7 @@ pub const ModuleBlock = struct {
         is_const: AddrSpaceAndIsConst,
         initid: u32,
         linkage: Builder.Linkage,
-        alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+        alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         section: usize,
         visibility: Builder.Visibility,
         thread_local: Builder.ThreadLocal,
@@ -275,7 +275,7 @@ pub const ModuleBlock = struct {
         is_proto: bool,
         linkage: Builder.Linkage,
         paramattr: usize,
-        alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+        alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         section: usize,
         visibility: Builder.Visibility,
         unnamed_addr: Builder.UnnamedAddr,
@@ -1214,7 +1214,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             ty: Builder.Type,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
         };
 
@@ -1230,7 +1230,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             ty: Builder.Type,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
@@ -1246,7 +1246,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             val: u32,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
         };
 
@@ -1262,7 +1262,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             val: u32,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
@@ -1317,7 +1317,7 @@ pub const ModuleBlock = struct {
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         };
 
         pub const CmpXchg = struct {
@@ -1341,7 +1341,7 @@ pub const ModuleBlock = struct {
             sync_scope: Builder.SyncScope,
             failure_ordering: Builder.AtomicOrdering,
             is_weak: bool,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         };
 
         pub const Fence = struct {

package/std/zig/system/arm.zig

@@ -21,7 +21,7 @@ pub const cpu_models = struct {
     };
 
     // implementer = 0x41
-    const ARM = [_]E{
+    const Arm = [_]E{
         E{ .part = 0x926, .m32 = &A32.arm926ej_s },
         E{ .part = 0xb02, .m32 = &A32.mpcore },
         E{ .part = 0xb36, .m32 = &A32.arm1136j_s },
@@ -88,8 +88,12 @@ pub const cpu_models = struct {
         E{ .part = 0xd87, .m64 = &A64.cortex_a725 },
         E{ .part = 0xd88, .m64 = &A64.cortex_a520ae },
         E{ .part = 0xd89, .m64 = &A64.cortex_a720ae },
+        E{ .part = 0xd8a, .m64 = &A64.c1_nano },
+        E{ .part = 0xd8b, .m64 = &A64.c1_pro },
+        E{ .part = 0xd8c, .m64 = &A64.c1_ultra },
         E{ .part = 0xd8e, .m64 = &A64.neoverse_n3 },
         E{ .part = 0xd8f, .m64 = &A64.cortex_a320 },
+        E{ .part = 0xd90, .m64 = &A64.c1_premium },
     };
     // implementer = 0x42
     const Broadcom = [_]E{
@@ -102,10 +106,17 @@ pub const cpu_models = struct {
         E{ .part = 0x0a3, .m64 = &A64.thunderxt83 },
         E{ .part = 0x0a1, .m64 = &A64.thunderxt88 },
         E{ .part = 0x0af, .m64 = &A64.thunderx2t99 },
+        E{ .part = 0x0b0, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b1, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b2, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b3, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b4, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b5, .m64 = &A64.cortex_a57 },
     };
     // implementer = 0x46
     const Fujitsu = [_]E{
         E{ .part = 0x001, .m64 = &A64.a64fx },
+        E{ .part = 0x003, .m64 = &A64.fujitsu_monaka },
     };
     // implementer = 0x48
     const HiSilicon = [_]E{
@@ -137,8 +148,14 @@ pub const cpu_models = struct {
         E{ .part = 0xc00, .m64 = &A64.falkor },
         E{ .part = 0xc01, .m64 = &A64.saphira },
     };
+    // implementer = 0x53
+    const Samsung = [_]E{
+        E{ .part = 0x000, .m64 = &A64.exynos_m1 },
+    };
     // implementer = 0x61
     const Apple = [_]E{
+        E{ .part = 0x020, .m64 = &A64.apple_m1 },
+        E{ .part = 0x021, .m64 = &A64.apple_m1 },
         E{ .part = 0x022, .m64 = &A64.apple_m1 },
         E{ .part = 0x023, .m64 = &A64.apple_m1 },
         E{ .part = 0x024, .m64 = &A64.apple_m1 },
@@ -151,11 +168,43 @@ pub const cpu_models = struct {
         E{ .part = 0x035, .m64 = &A64.apple_m2 },
         E{ .part = 0x038, .m64 = &A64.apple_m2 },
         E{ .part = 0x039, .m64 = &A64.apple_m2 },
+        E{ .part = 0x042, .m64 = &A64.apple_m3 },
+        E{ .part = 0x043, .m64 = &A64.apple_m3 },
+        E{ .part = 0x044, .m64 = &A64.apple_m3 },
+        E{ .part = 0x045, .m64 = &A64.apple_m3 },
+        E{ .part = 0x048, .m64 = &A64.apple_m3 },
+        E{ .part = 0x049, .m64 = &A64.apple_m3 },
+        E{ .part = 0x052, .m64 = &A64.apple_m4 },
+        E{ .part = 0x053, .m64 = &A64.apple_m4 },
+        E{ .part = 0x054, .m64 = &A64.apple_m4 },
+        E{ .part = 0x055, .m64 = &A64.apple_m4 },
+        E{ .part = 0x058, .m64 = &A64.apple_m4 },
+        E{ .part = 0x059, .m64 = &A64.apple_m4 },
+    };
+    // implementer = 0x63
+    const ArmChina = [_]E{
+        E{ .part = 0x132, .m32 = &A32.star_mc1 },
+        E{ .part = 0xd25, .m32 = &A32.star_mc3 },
+    };
+    // implementer = 0x68
+    const Hxt = [_]E{
+        E{ .part = 0x000, .m64 = &A64.cortex_a57 },
+    };
+    // implementer = 0x6d
+    const Microsoft = [_]E{
+        E{ .part = 0xd49, .m64 = &A64.neoverse_n2 },
+    };
+    // implementer = 0xC0
+    const AmpereOne = [_]E{
+        E{ .part = 0xac3, .m64 = &A64.ampere1 },
+        E{ .part = 0xac4, .m64 = &A64.ampere1a },
+        E{ .part = 0xac5, .m64 = &A64.ampere1b },
+        E{ .part = 0xac7, .m64 = &A64.ampere1c },
     };
 
     pub fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model {
         const models = switch (core.implementer) {
-            0x41 => &ARM,
+            0x41 => &Arm,
             0x42 => &Broadcom,
             0x43 => &Cavium,
             0x46 => &Fujitsu,
@@ -163,7 +212,12 @@ pub const cpu_models = struct {
             0x4e => &Nvidia,
             0x50 => &Ampere,
             0x51 => &Qualcomm,
+            0x53 => &Samsung,
             0x61 => &Apple,
+            0x63 => &ArmChina,
+            0x68 => &Hxt,
+            0x6d => &Microsoft,
+            0xC0 => &AmpereOne,
             else => return null,
         };
 

package/std/zig/system/darwin/macos.zig

@@ -411,7 +411,7 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
 
     const current_arch = builtin.cpu.arch;
     switch (current_arch) {
-        .aarch64, .aarch64_be => {
+        .aarch64 => {
             const model = switch (cpu_family) {
                 .ARM_CYCLONE => &Target.aarch64.cpu.apple_a7,
                 .ARM_TYPHOON => &Target.aarch64.cpu.apple_a8,
@@ -420,17 +420,21 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
                 .ARM_MONSOON_MISTRAL => &Target.aarch64.cpu.apple_a11,
                 .ARM_VORTEX_TEMPEST => &Target.aarch64.cpu.apple_a12,
                 .ARM_LIGHTNING_THUNDER => &Target.aarch64.cpu.apple_a13,
-                .ARM_FIRESTORM_ICESTORM => &Target.aarch64.cpu.apple_m1, // a14
-                .ARM_BLIZZARD_AVALANCHE => &Target.aarch64.cpu.apple_m2, // a15
-                .ARM_EVEREST_SAWTOOTH => &Target.aarch64.cpu.apple_m3, // a16
+                .ARM_FIRESTORM_ICESTORM => &Target.aarch64.cpu.apple_a14,
+                .ARM_BLIZZARD_AVALANCHE => &Target.aarch64.cpu.apple_a15,
+                .ARM_EVEREST_SAWTOOTH => &Target.aarch64.cpu.apple_a16,
                 .ARM_IBIZA => &Target.aarch64.cpu.apple_m3, // base
                 .ARM_PALMA => &Target.aarch64.cpu.apple_m3, // max
                 .ARM_LOBOS => &Target.aarch64.cpu.apple_m3, // pro
-                .ARM_COLL => &Target.aarch64.cpu.apple_a17, // a17 pro
+                .ARM_COLL => &Target.aarch64.cpu.apple_a17, // pro
                 .ARM_DONAN => &Target.aarch64.cpu.apple_m4, // base
                 .ARM_BRAVA => &Target.aarch64.cpu.apple_m4, // pro/max
-                .ARM_TAHITI => &Target.aarch64.cpu.apple_m4, // a18 pro
-                .ARM_TUPAI => &Target.aarch64.cpu.apple_m4, // a18
+                .ARM_TAHITI => &Target.aarch64.cpu.apple_a18, // pro
+                .ARM_TUPAI => &Target.aarch64.cpu.apple_a18, // base
+                .ARM_HIDRA => &Target.aarch64.cpu.apple_m5, // base
+                .ARM_SOTRA => &Target.aarch64.cpu.apple_m5, // pro/max
+                .ARM_THERA => &Target.aarch64.cpu.apple_a19, // pro
+                .ARM_TILOS => &Target.aarch64.cpu.apple_a19, // base
                 else => return null,
             };
 

package/std/zig/system/linux.zig

@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
     model: ?*const Target.Cpu.Model = null,
 
     const cpu_names = .{
+        .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
+        .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
         .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
+        .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {

package/std/zig/system/loongarch.zig

@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(
 
     cpu.features.addFeatureSet(cpu.model.features);
 
-    const cfg1 = cpucfg(1);
     const cfg2 = cpucfg(2);
     const cfg3 = cpucfg(3);
 
-    setFeature(&cpu, .ual, bit(cfg1, 20));
+    if (builtin.os.tag == .linux) {
+        const HWCAP = std.os.linux.HWCAP;
+        const hwcap_bits: usize = if (builtin.link_libc)
+            std.c.getauxval(std.elf.AT_HWCAP)
+        else
+            std.os.linux.getauxval(std.elf.AT_HWCAP);
 
-    const has_fpu = bit(cfg2, 0);
-    setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
-    setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
 
-    setFeature(&cpu, .lsx, bit(cfg2, 6));
-    setFeature(&cpu, .lasx, bit(cfg2, 7));
-    setFeature(&cpu, .lvz, bit(cfg2, 10));
+        const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
+        setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
+        setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .lsx, (hwcap_bits & HWCAP.LSX) != 0);
+        setFeature(&cpu, .lasx, (hwcap_bits & HWCAP.LASX) != 0);
 
-    setFeature(&cpu, .lbt, bit(cfg2, 18) and bit(cfg2, 19) and bit(cfg2, 20));
+        setFeature(&cpu, .lvz, (hwcap_bits & HWCAP.LVZ) != 0);
+        setFeature(&cpu, .lbt, (hwcap_bits & HWCAP.LBT_X86) != 0 and (hwcap_bits & HWCAP.LBT_ARM) != 0 and (hwcap_bits & HWCAP.LBT_MIPS) != 0);
+    } else {
+        setFeature(&cpu, .ual, false);
+
+        setFeature(&cpu, .f, false);
+        setFeature(&cpu, .d, false);
+        setFeature(&cpu, .lsx, false);
+        setFeature(&cpu, .lasx, false);
+
+        setFeature(&cpu, .lvz, false);
+        setFeature(&cpu, .lbt, false);
+    }
 
     setFeature(&cpu, .frecipe, bit(cfg2, 25));
     setFeature(&cpu, .div32, bit(cfg2, 26));

package/std/zig/system/windows.zig

@@ -60,14 +60,14 @@ fn getCpuInfoFromRegistry(core: usize, args: anytype) !void {
         @compileError("expected tuple or struct argument, found " ++ @typeName(ArgsType));
     }
 
-    const fields_info = args_type_info.@"struct".fields;
+    const fields_info = args_type_info.@"struct";
 
     // Originally, I wanted to issue a single call with a more complex table structure such that we
     // would sequentially visit each CPU#d subkey in the registry and pull the value of interest into
     // a buffer, however, NT seems to be expecting a single buffer per each table meaning we would
     // end up pulling only the last CPU core info, overwriting everything else.
     // If anyone can come up with a solution to this, please do!
-    const table_size = 1 + fields_info.len;
+    const table_size = 1 + fields_info.field_names.len;
     var table: [table_size + 1]std.os.windows.RTL_QUERY_REGISTRY_TABLE = undefined;
 
     const topkey = std.unicode.utf8ToUtf16LeStringLiteral("\\Registry\\Machine\\HARDWARE\\DESCRIPTION\\System\\CentralProcessor");
@@ -90,11 +90,11 @@ fn getCpuInfoFromRegistry(core: usize, args: anytype) !void {
         .DefaultLength = 0,
     };
 
-    var tmp_bufs: [fields_info.len][max_value_len]u8 align(@alignOf(std.os.windows.UNICODE_STRING)) = undefined;
+    var tmp_bufs: [fields_info.field_names.len][max_value_len]u8 align(@alignOf(std.os.windows.UNICODE_STRING)) = undefined;
 
-    inline for (fields_info, 0..) |field, i| {
+    inline for (fields_info.field_names, 0..) |field_name, i| {
         const ctx: *anyopaque = blk: {
-            switch (@field(args, field.name).value_type) {
+            switch (@field(args, field_name).value_type) {
                 .SZ,
                 .EXPAND_SZ,
                 .MULTI_SZ,
@@ -119,7 +119,7 @@ fn getCpuInfoFromRegistry(core: usize, args: anytype) !void {
         };
 
         var key_buf: [max_value_len / 2 + 1]u16 = undefined;
-        const key_len = try std.unicode.utf8ToUtf16Le(&key_buf, @field(args, field.name).key);
+        const key_len = try std.unicode.utf8ToUtf16Le(&key_buf, @field(args, field_name).key);
         key_buf[key_len] = 0;
 
         table[i + 1] = .{
@@ -153,12 +153,12 @@ fn getCpuInfoFromRegistry(core: usize, args: anytype) !void {
     );
     switch (res) {
         .SUCCESS => {
-            inline for (fields_info, 0..) |field, i| switch (@field(args, field.name).value_type) {
+            inline for (fields_info.field_names, 0..) |field_name, i| switch (@field(args, field_name).value_type) {
                 .SZ,
                 .EXPAND_SZ,
                 .MULTI_SZ,
                 => {
-                    var buf = @field(args, field.name).value_buf;
+                    var buf = @field(args, field_name).value_buf;
                     const entry: *const std.os.windows.UNICODE_STRING = @ptrCast(table[i + 1].EntryContext);
                     const len = try std.unicode.utf16LeToUtf8(buf, entry.slice());
                     buf[len] = 0;
@@ -169,12 +169,12 @@ fn getCpuInfoFromRegistry(core: usize, args: anytype) !void {
                 .QWORD,
                 => {
                     const entry: [*]const u8 = @ptrCast(table[i + 1].EntryContext);
-                    switch (@field(args, field.name).value_type) {
+                    switch (@field(args, field_name).value_type) {
                         .DWORD, .DWORD_BIG_ENDIAN => {
-                            @memcpy(@field(args, field.name).value_buf[0..4], entry[0..4]);
+                            @memcpy(@field(args, field_name).value_buf[0..4], entry[0..4]);
                         },
                         .QWORD => {
-                            @memcpy(@field(args, field.name).value_buf[0..8], entry[0..8]);
+                            @memcpy(@field(args, field_name).value_buf[0..8], entry[0..8]);
                         },
                         else => unreachable,
                     }
@@ -215,10 +215,43 @@ fn genericCpuAndNativeFeatures(arch: Target.Cpu.Arch) Target.Cpu {
             // Override any features that are either present or absent
             setFeature(Feature, &cpu, .neon, IsProcessorFeaturePresent(PF.ARM_NEON_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .crc, IsProcessorFeaturePresent(PF.ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE));
-            setFeature(Feature, &cpu, .crypto, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .aes, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sha2, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .lse, IsProcessorFeaturePresent(PF.ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .dotprod, IsProcessorFeaturePresent(PF.ARM_V82_DP_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .jsconv, IsProcessorFeaturePresent(PF.ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .rcpc, IsProcessorFeaturePresent(PF.ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve, IsProcessorFeaturePresent(PF.ARM_SVE_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve2, IsProcessorFeaturePresent(PF.ARM_SVE2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve2p1, IsProcessorFeaturePresent(PF.ARM_SVE2_1_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_aes, IsProcessorFeaturePresent(PF.ARM_SVE_AES_INSTRUCTIONS_AVAILABLE) or IsProcessorFeaturePresent(PF.ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_bitperm, IsProcessorFeaturePresent(PF.ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .bf16, IsProcessorFeaturePresent(PF.ARM_V86_BF16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_b16b16, IsProcessorFeaturePresent(PF.ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_sha3, IsProcessorFeaturePresent(PF.ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_sm4, IsProcessorFeaturePresent(PF.ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .i8mm, IsProcessorFeaturePresent(PF.ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .f32mm, IsProcessorFeaturePresent(PF.ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .f64mm, IsProcessorFeaturePresent(PF.ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme, IsProcessorFeaturePresent(PF.ARM_SME_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2, IsProcessorFeaturePresent(PF.ARM_SME2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .lse2, IsProcessorFeaturePresent(PF.ARM_LSE2_AVAILABLE));
+            setFeature(Feature, &cpu, .sha3, IsProcessorFeaturePresent(PF.ARM_SHA3_INSTRUCTIONS_AVAILABLE) and IsProcessorFeaturePresent(PF.ARM_SHA512_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .fullfp16, IsProcessorFeaturePresent(PF.ARM_V82_FP16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2p1, IsProcessorFeaturePresent(PF.ARM_SME2_1_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2p2, IsProcessorFeaturePresent(PF.ARM_SME2_2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_aes, IsProcessorFeaturePresent(PF.ARM_SME_AES_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_bitperm, IsProcessorFeaturePresent(PF.ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8dot2, IsProcessorFeaturePresent(PF.ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8dot4, IsProcessorFeaturePresent(PF.ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8fma, IsProcessorFeaturePresent(PF.ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f8f32, IsProcessorFeaturePresent(PF.ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f8f16, IsProcessorFeaturePresent(PF.ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_b16b16, IsProcessorFeaturePresent(PF.ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f64f64, IsProcessorFeaturePresent(PF.ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_i16i64, IsProcessorFeaturePresent(PF.ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_lutv2, IsProcessorFeaturePresent(PF.ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_fa64, IsProcessorFeaturePresent(PF.ARM_SME_FA64_INSTRUCTIONS_AVAILABLE));
         },
         else => {},
     }

package/std/zig/system/x86.zig

@@ -232,7 +232,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
                     cpu.model = &Target.x86.cpu.lunarlake;
                     return;
                 },
-                0xcc => {
+                0xcc, 0xd5 => {
                     cpu.model = &Target.x86.cpu.pantherlake;
                     return;
                 },
@@ -307,6 +307,20 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
             cpu.model = &Target.x86.cpu.pentium4;
             return;
         },
+        18 => switch (model) {
+            0x01, 0x03 => {
+                cpu.model = &Target.x86.cpu.novalake;
+                return;
+            },
+            else => return, // Unknown CPU Model
+        },
+        19 => switch (model) {
+            0x01 => {
+                cpu.model = &Target.x86.cpu.diamondrapids;
+                return;
+            },
+            else => return, // Unknown CPU Model
+        },
         else => return, // Unknown CPU Model
     }
 }
@@ -412,6 +426,8 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
     // AMX requires additional context to be saved by the OS.
     const has_amx_save = xcr0.xtilecfg and xcr0.xtiledata;
 
+    const has_apx_save = xcr0.apx;
+
     setFeature(cpu, .avx, has_avx_save);
     setFeature(cpu, .fma, bit(leaf.ecx, 12) and has_avx_save);
     // Only enable XSAVE if OS has enabled support for saving YMM state.
@@ -470,7 +486,20 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
         }
     }
 
-    if (max_level >= 0x7) {
+    if (max_ext_level >= 0x80000021) {
+        leaf = cpuid(0x80000021, 0);
+
+        // AMD uses a different bit for prefetchi.
+        setFeature(cpu, .prefetchi, bit(leaf.eax, 20));
+    } else {
+        for ([_]Target.x86.Feature{
+            .prefetchi,
+        }) |feat| {
+            setFeature(cpu, feat, false);
+        }
+    }
+
+    const has_avx10 = if (max_level >= 0x7) has_avx10: {
         leaf = cpuid(0x7, 0);
 
         setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
@@ -484,7 +513,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
         setFeature(cpu, .rtm, bit(leaf.ebx, 11));
         // AVX512 is only supported if the OS supports the context save for it.
         setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
-        setFeature(cpu, .evex512, bit(leaf.ebx, 16) and has_avx512_save);
         setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
         setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
         setFeature(cpu, .adx, bit(leaf.ebx, 19));
@@ -556,15 +584,20 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             setFeature(cpu, .avxneconvert, bit(leaf.edx, 5) and has_avx_save);
             setFeature(cpu, .amx_complex, bit(leaf.edx, 8) and has_amx_save);
             setFeature(cpu, .avxvnniint16, bit(leaf.edx, 10) and has_avx_save);
-            setFeature(cpu, .prefetchi, bit(leaf.edx, 14));
+            // This needs to account for prefetchi already being detected above on AMD.
+            setFeature(cpu, .prefetchi, cpu.has(.x86, .prefetchi) or bit(leaf.edx, 14));
             setFeature(cpu, .usermsr, bit(leaf.edx, 15));
             // APX
-            setFeature(cpu, .egpr, bit(leaf.edx, 21));
-            setFeature(cpu, .push2pop2, bit(leaf.edx, 21));
-            setFeature(cpu, .ppx, bit(leaf.edx, 21));
-            setFeature(cpu, .ndd, bit(leaf.edx, 21));
-            setFeature(cpu, .ccmp, bit(leaf.edx, 21));
-            setFeature(cpu, .cf, bit(leaf.edx, 21));
+            setFeature(cpu, .egpr, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .push2pop2, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ppx, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ndd, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ccmp, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .nf, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .cf, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .zu, bit(leaf.edx, 21) and has_apx_save);
+
+            break :has_avx10 bit(leaf.edx, 19);
         } else {
             for ([_]Target.x86.Feature{
                 .sha512,
@@ -582,19 +615,23 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
                 .avxneconvert,
                 .amx_complex,
                 .avxvnniint16,
-                .prefetchi,
+                // prefetchi already handled earlier.
                 .usermsr,
                 .egpr,
                 .push2pop2,
                 .ppx,
                 .ndd,
                 .ccmp,
+                .nf,
                 .cf,
+                .zu,
             }) |feat| {
                 setFeature(cpu, feat, false);
             }
         }
-    } else {
+
+        break :has_avx10 false;
+    } else has_avx10: {
         for ([_]Target.x86.Feature{
             .fsgsbase,
             .sgx,
@@ -605,7 +642,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             .invpcid,
             .rtm,
             .avx512f,
-            .evex512,
             .avx512dq,
             .rdseed,
             .adx,
@@ -664,18 +700,22 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             .avxneconvert,
             .amx_complex,
             .avxvnniint16,
-            .prefetchi,
+            // prefetchi already handled earlier.
             .usermsr,
             .egpr,
             .push2pop2,
             .ppx,
             .ndd,
             .ccmp,
+            .nf,
             .cf,
+            .zu,
         }) |feat| {
             setFeature(cpu, feat, false);
         }
-    }
+
+        break :has_avx10 false;
+    };
 
     if (max_level >= 0xD and has_avx_save) {
         leaf = cpuid(0xD, 0x1);
@@ -721,10 +761,14 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
     if (max_level >= 0x24) {
         leaf = cpuid(0x24, 0);
 
-        setFeature(cpu, .avx10_1, bit(leaf.ebx, 18));
+        const avx_ver = leaf.ebx & 0xff;
+
+        setFeature(cpu, .avx10_1, has_avx10 and avx_ver >= 1);
+        setFeature(cpu, .avx10_2, has_avx10 and avx_ver >= 2);
     } else {
         for ([_]Target.x86.Feature{
             .avx10_1,
+            .avx10_2,
         }) |feat| {
             setFeature(cpu, feat, false);
         }