@zigc/lib 0.17.0-dev.607 → 0.17.0-dev.633

package/libc/include/generic-netbsd/uvm/uvm_swap.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: uvm_swap.h,v 1.26 2020/09/05 16:30:13 riastradh Exp $	*/
+/*	$NetBSD: uvm_swap.h,v 1.29.4.1 2026/04/03 12:38:34 martin Exp $	*/
 
 /*
  * Copyright (c) 1997 Matthew R. Green
@@ -39,10 +39,10 @@
 #endif
 
 struct lwp;
+struct swapent;
 
 #if defined(VMSWAP)
 
-struct swapent;
 struct vm_page;
 
 int	uvm_swap_get(struct vm_page *, int, int);
@@ -55,10 +55,21 @@ void	swapsys_lock(krw_t);
 void	swapsys_unlock(void);
 int	uvm_swap_stats(char *, int,
     void (*)(void *, const struct swapent *), size_t, register_t *);
+void	uvm_swap_decrypt_pages(int startslot, void *p, int npages);
 
 #else /* defined(VMSWAP) */
+
 #define	uvm_swapisfull()	true
-#define uvm_swap_stats(c, l, f, count, retval) (__used f, *retval = 0, ENOSYS)
+
+static inline int
+uvm_swap_stats(char *c, int l, void (*f)(void *, const struct swapent *),
+    size_t count, register_t *retval)
+{
+
+	*retval = 0;
+	return ENOSYS;
+}
+
 #endif /* defined(VMSWAP) */
 
 void	uvm_swap_shutdown(struct lwp *);

package/libc/include/generic-netbsd/wchar.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: wchar.h,v 1.44 2020/03/20 01:08:42 joerg Exp $	*/
+/*	$NetBSD: wchar.h,v 1.46 2024/11/01 16:36:58 nia Exp $	*/
 
 /*-
  * Copyright (c)1999 Citrus Project,
@@ -130,10 +130,15 @@ wchar_t	*wcswcs(const wchar_t *, const wchar_t *);
 wchar_t	*wmemchr(const wchar_t *, wchar_t, size_t);
 int	wmemcmp(const wchar_t *, const wchar_t *, size_t);
 wchar_t	*wmemcpy(wchar_t * __restrict, const wchar_t * __restrict, size_t);
+wchar_t	*wmempcpy(wchar_t * __restrict, const wchar_t * __restrict, size_t);
 wchar_t	*wmemmove(wchar_t *, const wchar_t *, size_t);
 wchar_t	*wmemset(wchar_t *, wchar_t, size_t);
 
-#if defined(_NETBSD_SOURCE)
+/*
+ * IEEE Std 1003.1-2024 (POSIX.1-2024)
+ */
+#if (_POSIX_C_SOURCE - 0) >= 202405L || (_XOPEN_SOURCE - 0 >= 800) || \
+    defined(_NETBSD_SOURCE)
 size_t	wcslcat(wchar_t *, const wchar_t *, size_t);
 size_t	wcslcpy(wchar_t *, const wchar_t *, size_t);
 #endif

package/libc/include/generic-netbsd/x86/bootinfo.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: bootinfo.h,v 1.31 2022/08/20 23:12:00 riastradh Exp $	*/
+/*	$NetBSD: bootinfo.h,v 1.32 2025/04/30 05:15:08 imil Exp $	*/
 
 /*
  * Copyright (c) 1997
@@ -272,6 +272,9 @@ struct bootinfo {
 };
 
 extern struct bootinfo bootinfo;
+#ifdef XEN
+extern bool pvh_boot;
+#endif
 
 void *lookup_bootinfo(int);
 void  aprint_bootinfo(void);

package/libc/include/generic-netbsd/x86/cpu.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.133.4.1 2023/08/09 17:42:01 martin Exp $	*/
+/*	$NetBSD: cpu.h,v 1.140 2025/04/24 01:50:39 riastradh Exp $	*/
 
 /*
  * Copyright (c) 1990 The Regents of the University of California.
@@ -325,6 +325,8 @@ struct cpu_info {
 	struct evcnt	ci_xen_raw_systime_backwards_evcnt;
 	struct evcnt	ci_xen_systime_backwards_hardclock_evcnt;
 	struct evcnt	ci_xen_missed_hardclock_evcnt;
+	struct evcnt	ci_xen_timecounter_backwards_evcnt;
+	struct evcnt	ci_xen_timecounter_jump_evcnt;
 #endif	/* XEN */
 
 #if defined(GPROF) && defined(MULTIPROCESSOR)
@@ -479,6 +481,7 @@ extern uint64_t x86_xsave_features;
 extern size_t x86_xsave_offsets[];
 extern size_t x86_xsave_sizes[];
 extern uint32_t x86_fpu_mxcsr_mask;
+bool x86_fpu_save_separate_p(void);
 
 extern void (*x86_cpu_idle)(void);
 #define	cpu_idle() (*x86_cpu_idle)()
@@ -514,6 +517,8 @@ typedef enum vm_guest {
 	VM_GUEST_VMWARE,
 	VM_GUEST_KVM,
 	VM_GUEST_VIRTUALBOX,
+	VM_GUEST_GENPVH,
+	VM_GUEST_NVMM,
 	VM_LAST
 } vm_guest_t;
 extern vm_guest_t vm_guest;
@@ -543,6 +548,18 @@ vm_guest_is_xenpvh_or_pvhvm(void)
 	}
 }
 
+static __inline bool __unused
+vm_guest_is_pvh(void)
+{
+	switch(vm_guest) {
+	case VM_GUEST_XENPVH:
+	case VM_GUEST_GENPVH:
+		return true;
+	default:
+		return false;
+	}
+}
+
 /* cpu_topology.c */
 void	x86_cpu_topology(struct cpu_info *);
 

package/libc/include/generic-netbsd/x86/cpu_extended_state.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu_extended_state.h,v 1.17.28.1 2023/07/25 11:41:42 martin Exp $	*/
+/*	$NetBSD: cpu_extended_state.h,v 1.19 2025/04/24 01:50:39 riastradh Exp $	*/
 
 #ifndef _X86_CPU_EXTENDED_STATE_H_
 #define _X86_CPU_EXTENDED_STATE_H_
@@ -226,6 +226,8 @@ struct xstate {
  * It is defined this way to separate the definitions and to
  * minimise the number of union/struct selectors.
  * NB: Some userspace stuff (eg firefox) uses it to parse ucontext.
+ * NB: This is not actually the largest possible save space;
+ *     x86_fpu_save_size may be larger.
  */
 union savefpu {
 	struct save87 sv_87;

package/libc/include/generic-netbsd/x86/cpuvar.h

@@ -1,4 +1,4 @@
-/* 	$NetBSD: cpuvar.h,v 1.53 2020/07/14 00:45:53 yamaguchi Exp $ */
+/* 	$NetBSD: cpuvar.h,v 1.55 2025/05/01 05:17:31 imil Exp $ */
 
 /*-
  * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@@ -124,8 +124,11 @@ void x86_cpu_idle_xen(void);
 void	cpu_get_tsc_freq(struct cpu_info *);
 void	pat_init(struct cpu_info *);
 
+bool	has_lapic(void);
+
 extern int cpu_vendor;
 extern bool x86_mp_online;
+extern u_int cpu_max_hypervisor_cpuid;
 
 extern uint32_t cpu_feature[7];
 

package/libc/include/generic-netbsd/x86/float.h

@@ -1,10 +1,33 @@
-/*	$NetBSD: float.h,v 1.6 2013/04/27 21:35:25 joerg Exp $	*/
+/*	$NetBSD: float.h,v 1.8 2024/06/15 11:44:09 rillig Exp $	*/
 
 #ifndef _X86_FLOAT_H_
 #define _X86_FLOAT_H_
 
 #include <sys/featuretest.h>
 
+/*
+ * LDBL_MIN is twice the m68k LDBL_MIN, even though both are 12-byte
+ * floats with the same base properties and both allegedly
+ * IEEE-compliant, because both these representations materialize the
+ * top (integer-part) bit of the mantissa. But on m68k if the exponent
+ * is 0 and the integer bit is set, it's a regular number, whereas on
+ * x86 it's called a pseudo-denormal and apparently treated as a
+ * denormal, so it doesn't count as a valid value for LDBL_MIN.
+ *
+ * x86 citation: Intel 64 and IA-32 Architectures Software Developer's
+ * Manual, vol. 1 (Order Number: 253665-077US, April 2022), Sec. 8.2.2
+ * `Unsupported Double Extended-Precision Floating-Point Encodings
+ * and Pseudo-Denormals', p. 8-14.
+ *
+ * m86k citation: MC68881/MC68882 Floating-Point Coprocessor User's
+ * Manual, Second Edition (Prentice-Hall, 1989, apparently issued by
+ * Freescale), Section 3.2 `Binary Real Data formats', pg. 3-3 bottom
+ * in particular and pp. 3-2 to 3-5 in general.
+ *
+ * If anyone needs to update this comment please make sure the copy in
+ * m68k/include/float.h also gets updated.
+ */
+
 #define	LDBL_MANT_DIG	64
 #define LDBL_EPSILON	1.0842021724855044340E-19L
 #define LDBL_DIG	18

package/libc/include/generic-netbsd/x86/ieee.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: ieee.h,v 1.11 2010/09/15 16:11:28 christos Exp $ */
+/*	$NetBSD: ieee.h,v 1.13 2024/01/02 19:28:25 christos Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -39,6 +39,8 @@
  *
  *	@(#)ieee.h	8.1 (Berkeley) 6/11/93
  */
+#ifndef _X86_IEEE_H_
+#define _X86_IEEE_H_
 
 /*
  * ieee.h defines the machine-dependent layout of the machine's IEEE
@@ -67,13 +69,13 @@
  *   i386:  16 bits.
  */
 struct ieee_ext {
-	u_int	ext_fracl:EXT_FRACLBITS;
-	u_int	ext_frach:EXT_FRACHBITS;
+	uint32_t	ext_fracl:EXT_FRACLBITS;
+	uint32_t	ext_frach:EXT_FRACHBITS;
 #if 0
-	u_int	ext_int:1;
+	uint32_t	ext_int:1;
 #endif
-	u_int	ext_exp:EXT_EXPBITS;
-	u_int	ext_sign:1;
+	uint32_t	ext_exp:EXT_EXPBITS;
+	uint32_t	ext_sign:1;
 };
 
 /*
@@ -114,4 +116,6 @@ union ieee_ext_u {
 #define extu_frach	extu_ext.ext_frach
 
 #define LDBL_NBIT	0x80000000
-#define mask_nbit_l(u)	((u).extu_frach &= ~LDBL_NBIT)
+#define mask_nbit_l(u)	((u).extu_frach &= ~LDBL_NBIT)
+
+#endif /* _X86_IEEE_H_ */

package/libc/include/generic-netbsd/x86/lwp_private.h

@@ -0,0 +1,56 @@
+/*	$NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:16 christos Exp $	*/
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Klaus Klein.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _X86_LWP_PRIVATE_H_
+#define _X86_LWP_PRIVATE_H_
+
+#include <sys/cdefs.h>
+#include <sys/tls.h>
+
+__BEGIN_DECLS
+
+static __inline void *
+__lwp_getprivate_fast(void)
+{
+	void *__tmp;
+
+#ifdef _LP64
+	__asm volatile("movq %%fs:0, %0" : "=r" (__tmp));
+#else
+	__asm volatile("movl %%gs:0, %0" : "=r" (__tmp));
+#endif
+
+	return __tmp;
+}
+
+__END_DECLS
+
+#endif	/* !_X86_LWP_PRIVATE_H_ */

package/libc/include/generic-netbsd/x86/mutex.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: mutex.h,v 1.9.22.1 2023/08/09 17:42:01 martin Exp $	*/
+/*	$NetBSD: mutex.h,v 1.10 2023/07/12 12:50:13 riastradh Exp $	*/
 
 /*-
  * Copyright (c) 2002, 2006, 2009 The NetBSD Foundation, Inc.

package/libc/include/generic-netbsd/x86/specialreg.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: specialreg.h,v 1.198.2.6 2024/10/03 12:00:57 martin Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.219 2025/04/28 13:01:27 riastradh Exp $	*/
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -122,7 +122,23 @@
 #define CR4_PKS		0x01000000 /* Enable Protection Keys for kern pages */
 
 /*
- * Extended Control Register XCR0
+ * Extended Control Register XCR0, also known as XFEATURE_ENABLED_MASK,
+ * with access via XGETBV/XSETBV instructions and support indicated by
+ * CPUID[EAX=0x0d, ECX=0].EAX/EDX.
+ *
+ * References:
+ *
+ * - Intel 64 and IA-32 Architectures Software Developer's Manual,
+ *   Volume 3: System Programming Guide, Intel, Order Number:
+ *   325384-087US, March 2025, Sec. 2.6 `Extended Control Registers
+ *   (Including XCR0)', pp. 2-20 -- 2-22.
+ *
+ * - AMD64 Architecture Programmer's Manual, Volume 2: System
+ *   Programming, Advanced Micro Devices, Publication no. 24593,
+ *   Rev. 3.42, March 2024, Sec. 11.5.2 `XFEATURE_ENABLED_MASK',
+ *   p. 355.
+ *
+ * XXX Missing reference for XCR0_PT, XCR0_HDC, XCR0_LBR, XCR0_HWP.
  */
 #define XCR0_X87	__BIT(0)	/* x87 FPU/MMX state */
 #define XCR0_SSE	__BIT(1)	/* SSE state */
@@ -139,20 +155,45 @@
 #define XCR0_HDC	__BIT(13)	/* Hardware Duty Cycle state */
 #define XCR0_LBR	__BIT(15)	/* Last Branch Record */
 #define XCR0_HWP	__BIT(16)	/* Hardware P-states */
-
-#define XCR0_FLAGS1	"\20"						  \
-	"\1" "x87"	"\2" "SSE"	"\3" "AVX"	"\4" "BNDREGS"	  \
-	"\5" "BNDCSR"	"\6" "Opmask"	"\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \
-	"\11" "PT"	"\12" "PKRU"			"\14" "CET_U"	  \
-	"\15" "CET_S"	"\16" "HDC"			"\20" "LBR"	  \
-	"\21" "HWP"
+#define XCR0_TILECFG	__BIT(17)	/* Intel AMX TILECFG state in XSAVE */
+#define XCR0_TILEDATA	__BIT(18)	/* Intel AMX TILEDATA state in XSAVE */
+#define XCR0_LWP	__BIT(62)	/* AMD Lightweight Profiling (LWP) */
+#define XCR0_X		__BIT(63)	/* AMD: reserved for XCR0 expansion */
+
+#define XCR0_FLAGS1	"\177\020"					  \
+	"b\000"		"x87\0"						  \
+	"b\001"		"SSE\0"						  \
+	"b\002"		"AVX\0"						  \
+	"b\003"		"BNDREGS\0"					  \
+	"b\004"		"BNDCSR\0"					  \
+	"b\005"		"Opmask\0"					  \
+	"b\006"		"ZMM_Hi256\0"					  \
+	"b\007"		"Hi16_ZMM\0"					  \
+	"b\010"		"PT\0"						  \
+	"b\011"		"PKRU\0"					  \
+	"b\013"		"CET_U\0"					  \
+	"b\014"		"CET_S\0"					  \
+	"b\015"		"HDC\0"						  \
+	"b\017"		"LBR\0"						  \
+	"b\020"		"HWP\0"						  \
+	"b\021"		"TILECFG\0"					  \
+	"b\022"		"TILEDATA\0"					  \
+	"b\076"		"LWP\0"						  \
+	"b\077"		"X\0"						  \
+	"\0"
 
 /*
  * Known FPU bits, only these get enabled. The save area is sized for all the
  * fields below.
  */
+#if defined __i386__ || defined XENPV /* XXX XENPV PR kern/59371 */
 #define XCR0_FPU	(XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
 			 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
+#else
+#define XCR0_FPU	(XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
+			 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM | \
+			 XCR0_TILECFG | XCR0_TILEDATA)
+#endif
 
 /*
  * XSAVE component indices, internal to NetBSD.
@@ -883,6 +924,7 @@
 #define CPUID_CAPEX_PREFER_IBRS	   __BIT(18) /* IBRS preferred */
 #define CPUID_CAPEX_IBRS_SAMEMODE  __BIT(19) /* IBRS same speculation limits */
 #define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
+#define CPUID_CAPEX_INVLPGB_NEST   __BIT(21) /* INVLPGB nested translation */
 #define CPUID_CAPEX_AMD_PPIN	   __BIT(23) /* Protected Processor Inventory Number */
 #define CPUID_CAPEX_SSBD	   __BIT(24) /* Speculation Control SSBD */
 #define CPUID_CAPEX_VIRT_SSBD	   __BIT(25) /* Virt Spec Control SSBD */
@@ -899,7 +941,7 @@
 	"\15IBPB"	"\16INT_WBINVD"	"\17IBRS"	"\20STIBP"	   \
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"		   \
 							"\24IBRS_SAMEMODE" \
-	"\25EFER_LSMSLE_UN"				"\30PPIN"	   \
+	"\25EFER_LSMSLE_UN" "\26INVLPGB_NEST"		"\30PPIN"	   \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"	"\34CPPC"	   \
 	"\35PSFD"	"\36BTC_NO"	"\37IBPB_RET"
 
@@ -925,6 +967,7 @@
 #define CPUID_AMD_SVM_VMCBCleanBits   __BIT(5)  /* VMCB Clean Bits support */
 #define CPUID_AMD_SVM_FlushByASID     __BIT(6)  /* Flush by ASID */
 #define CPUID_AMD_SVM_DecodeAssist    __BIT(7)  /* Decode Assists support */
+#define CPUID_AMD_SVM_PmcVirt	      __BIT(8)  /* PMC Virtualization */
 #define CPUID_AMD_SVM_PauseFilter     __BIT(10) /* PAUSE intercept filter */
 #define CPUID_AMD_SVM_PFThreshold     __BIT(12) /* PAUSE filter threshold */
 #define CPUID_AMD_SVM_AVIC	      __BIT(13) /* Advanced Virt. Intr. Ctrl */
@@ -932,7 +975,7 @@
 #define CPUID_AMD_SVM_vGIF	      __BIT(16) /* Virtualized GIF */
 #define CPUID_AMD_SVM_GMET	      __BIT(17) /* Guest Mode Execution Trap */
 #define CPUID_AMD_SVM_X2AVIC	      __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
-#define CPUID_AMD_SVM_SSSCHECK	      __BIT(19)  /* Shadow Stack restrictions */
+#define CPUID_AMD_SVM_SSSCHECK	      __BIT(19) /* Shadow Stack restrictions */
 #define CPUID_AMD_SVM_SPEC_CTRL	      __BIT(20) /* SPEC_CTRL virtualization */
 #define CPUID_AMD_SVM_ROGPT	      __BIT(21) /* Read-Only Guest PTable */
 #define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
@@ -942,19 +985,21 @@
 #define CPUID_AMD_SVM_XLVTOFFFLTCHG   __BIT(27) /* Ext LVToffset FLT changed */
 #define CPUID_AMD_SVM_VMCBADRCHKCHG   __BIT(28) /* VMCB addr check changed */
 #define CPUID_AMD_SVM_BUSLOCKTHRESH   __BIT(29) /* Bus Lock Threshold */
-
+#define CPUID_AMD_SVM_IDLEHLTINTERCEPT __BIT(30) /* Idle HLT Intercept */
+#define CPUID_AMD_SVM_ESHUTDOWN	      __BIT(31) /* Enhanced Shutdown Intr. */
 
 #define CPUID_AMD_SVM_FLAGS	 "\20"					\
 	"\1" "NP"	"\2" "LbrVirt"	"\3" "SVML"	"\4" "NRIPS"	\
 	"\5" "TSCRate"	"\6" "VMCBCleanBits" 				\
 			        "\7" "FlushByASID" "\10" "DecodeAssist"	\
-	"\11" "B08"	"\12" "B09"	"\13" "PauseFilter" "\14" "B11"	\
+	"\11PmcVirt"	"\12" "B09"	"\13" "PauseFilter" "\14" "B11"	\
 	"\15" "PFThreshold" "\16" "AVIC" "\17" "B14"			\
 						"\20" "V_VMSAVE_VMLOAD"	\
 	"\21" "VGIF"	"\22" "GMET"	"\23x2AVIC"	"\24SSSCHECK"	\
 	"\25" "SPEC_CTRL" "\26" "ROGPT"		"\30HOST_MCE_OVERRIDE"	\
 	"\31" "TLBICTL"	"\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
-	"\35VmcbAddrChkChg" "\36BusLockThreshold"
+	"\35VmcbAddrChkChg" "\36BusLockThreshold" "\37IdleHltIntercept" \
+						"\40EnhancedShutdownInterrupt"
 
 /*
  * AMD Instruction-Based Sampling Capabilities.
@@ -972,13 +1017,17 @@
 #define CPUID_IBS_OPBRNFUSE	__BIT(8)  /* Fused branch micro-op indicate */
 #define CPUID_IBS_FETCHCTLEXTD	__BIT(9)  /* IC_IBS_EXTD_CTL MSR */
 #define CPUID_IBS_OPDATA4	__BIT(10) /* IBS op data 4 MSR */
-#define CPUID_IBS_L3MISSFILT	__BIT(11) /* L3 Miss Filtering */
+#define CPUID_IBS_ZEN4E		__BIT(11) /* Zen4 IBS Extensions */
+#define CPUID_IBS_LOADLATFILT	__BIT(12) /* Load Latency Filtering */
+#define CPUID_IBS_UPDDTLBSTAT	__BIT(19) /* Updated DTLB stats */
 
 #define CPUID_IBS_FLAGS	 "\20"						   \
 	"\1IBSFFV"	"\2FetchSam"	"\3OpSam"	"\4RdWrOpCnt"	   \
 	"\5OpCnt"	"\6BrnTrgt"	"\7OpCntExt"	"\10RipInvalidChk" \
 	"\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4"		   \
-						   "\14IbsL3MissFiltering"
+						   "\14Zen4IbsExtensions" \
+	"\15IbsLoadLatencyFiltering"					   \
+						    "\24IbsUpdtdDtlbStats"
 
 /*
  * AMD Cache Topology Information.
@@ -1024,7 +1073,7 @@
 #define CPUID_AMD_ENCMEM_RMPQUERY __BIT(6) /* RMPQUERY instruction */
 #define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7)  /* VMPL Secure Shadow Stack */
 #define CPUID_AMD_ENCMEM_SECTSC	__BIT(8)   /* Secure TSC */
-#define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9)  /* TSC AUX Virtualization */
+#define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */
 #define CPUID_AMD_ENCMEM_HECC	__BIT(10) /* HW Enf Cache Coh across enc dom */
 #define CPUID_AMD_ENCMEM_64BH	__BIT(11)  /* 64Bit Host */
 #define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */
@@ -1032,14 +1081,21 @@
 #define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */
 #define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */
 #define CPUID_AMD_ENCMEM_VTE	__BIT(16)  /* Virtual Transparent Encryption */
-
 #define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */
 #define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18)  /* Virtual TOM MSR */
 #define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */
+#define CPUID_AMD_ENCMEM_PMCVGUEST __BIT(20) /* PMC Virt. for SEV-ES guest */
+#define CPUID_AMD_ENCMEM_RMPREAD __BIT(21)  /* RMPREAD instruction */
+#define CPUID_AMD_ENCMEM_GUESTINTERCEPT __BIT(22) /* Guest Intercept 4SEV-ES */
+#define CPUID_AMD_ENCMEM_SEGRMP __BIT(23)  /* Segmented RMP */
 #define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */
 #define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */
+#define CPUID_AMD_ENCMEM_SECAVIC __BIT(26) /* Secure AVIC */
+#define CPUID_AMD_ENCMEM_ALLOWSEV __BIT(27) /* Allowed SEV */
 #define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */
 #define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */
+#define CPUID_AMD_ENCMEM_HVINUSEWR __BIT(30) /* HV In Use Write Allow */
+#define CPUID_AMD_ENCMEM_IBPBONENTRY __BIT(31) /* IBPB on Entry */
 
 #define CPUID_AMD_ENCMEM_FLAGS	 "\20"					      \
 	"\1" "SME"	"\2" "SEV"	"\3" "PageFlushMsr"	"\4" "SEV-ES" \
@@ -1047,8 +1103,11 @@
 	"\11SecureTSC"	"\12TscAuxVirt"	"\13HwEnfCacheCoh"  "\14" "64BitHost" \
 	"\15" "RSTRINJ"	"\16" "ALTINJ"	"\17" "DebugSwap" "\20PreventHostIbs" \
 	"\21VTE"      "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest"  \
-	"\31VmsaRegProt" "\32SmtProtection"				      \
-	"\35SvsmCommPageMSR" "\36NestedVirtSnpMsr"
+	"\25PmcVirtGuest" "\26RMPREAD"					      \
+				"\27GuestInterceptControl" "\30SegmentedRmp"  \
+	"\31VmsaRegProt" "\32SmtProtection" "\33SecureAvic" "\34AllowedSev"   \
+	"\35SvsmCommPageMSR" "\36NestedVirtSnpMsr" "\37HvInuseWrAllowed"      \
+	"\40IbpbOnEntry"
 
 /*
  * AMD Extended Features 2.
@@ -1066,17 +1125,37 @@
 #define CPUID_AMDEXT2_NOSMMCTL	  __BIT(9) /* SMM_CTL MSR is not supported */
 #define CPUID_AMDEXT2_FSRS	  __BIT(10) /* Fast Short Rep Stosb */
 #define CPUID_AMDEXT2_FSRC	  __BIT(11) /* Fast Short Rep Cmpsb */
+#define CPUID_AMDEXT2_PMCPRECISERETIRE __BIT(12) /* PMC Presize Retire */
 #define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
+#define CPUID_AMDEXT2_L2TLBSIZEX32 __BIT(14) /* L2TLB size encoded as x32 */
+#define CPUID_AMDEXT2_ERMSB	  __BIT(15) /* AMD implementation of ERMSB */
+#define CPUID_AMDEXT2_OPF17RECLAIM __BIT(16) /* Reserve opcode 0f 01/7 */
 #define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
 #define CPUID_AMDEXT2_EPSF	  __BIT(18) /* Enhanced Predictive Store Fwd */
+#define CPUID_AMDEXT2_0F017_RECLAIM __BIT(19) /* Opecode 0f 01/7 reserved */
+#define CPUID_AMDEXT2_PREFETCHI	  __BIT(20) /* IC prefetch support */
+#define CPUID_AMDEXT2_FP512_DOWNGRADE __BIT(21) /* FP512 dpath down to 256 */
+#define CPUID_AMDEXT2_WL_CLASS	  __BIT(22) /* wkld based heuristic feedback */
+#define CPUID_AMDEXT2_ERAPS	  __BIT(24) /* Enhn. Retn. Addr. Pred. Sec. */
+#define CPUID_AMDEXT2_SBPB	  __BIT(27) /* Selective Brnc. Pred. Barrier */
+#define CPUID_AMDEXT2_IBPB_BRTYPE __BIT(28) /* BRanch TYPE prediction flush */
+#define CPUID_AMDEXT2_SRSO_NO	  __BIT(29) /* Not vulnerable to SRSO */
+#define CPUID_AMDEXT2_SRSO_UK_NO  __BIT(30) /* SRSO_NO at user-kern boundary */
+#define CPUID_AMDEXT2_SRSO_MSR_FIX __BIT(31) /* SRSO mitig. bit in BP_CFG[4] */
 
 #define CPUID_AMDEXT2_FLAGS	 "\20"					      \
 	"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing"		      \
 				"\3LfenceAlwaysSerialize" "\4SmmPgCfgLock"    \
 			     "\7NullSelectClearsBase" "\10UpperAddressIgnore" \
 	"\11AutomaticIBRS" "\12NoSmmCtlMSR"	"\13FSRS"	"\14FSRC"     \
-			"\16PrefetchCtlMSR"				      \
-			"\22CpuidUserDis"	"\23EPSF"
+	"\15PMC2PreciseRetire" "\16PrefetchCtlMSR" "\17L2TlbsizeX32"	      \
+							       "\20AMD_ERMSB" \
+	"\21OPCODE_0F017_RECLAIM" "\22CpuidUserDis" "\23EPSF"		      \
+							  "\24FAST_REP_SCASB" \
+	"\25PREFETCHI"	"\26FP512_DOWNGRADE" "\27WL_CLASS_SUPPORT"	      \
+	"\31ERAPS"						"\34SBPB"     \
+	"\35IBPB_BRTYPE" "\36SRSO_NO" "\37SRSO_USER_KERNEL_NO"		      \
+							    "\40SRSO_MSR_FIX"
 
 /*
  * AMD Extended Performance Monitoring and Debug
@@ -1095,7 +1174,16 @@
 #define CPUID_AXPERF_NCPC      __BITS(3, 0)	/* Num of Core PMC counters */
 #define CPUID_AXPERF_NLBRSTACK __BITS(9, 4)	/* Num of LBR Stack entries */
 #define CPUID_AXPERF_NNBPC     __BITS(15, 10)	/* Num of NorthBridge PMCs */
-#define CPUID_AXPERF_NUMCPC    __BITS(21, 16)	/* Num of UMC PMCs */
+#define CPUID_AXPERF_NUMCPC    __BITS(23, 16)	/* Num of UMC PMCs */
+
+/*
+ * AMD Hetero Workload Classification
+ * CPUID Fn8000_0027
+ */
+
+/* %eax */
+
+#define CPUID_HWC_NWC	        __BITS(3, 0) /* Number of Workload Class IDs */
 
 /*
  * Centaur Extended Feature flags.

package/libc/include/m68k-netbsd-none/m68k/asm.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: asm.h,v 1.34 2020/04/17 14:19:43 joerg Exp $	*/
+/*	$NetBSD: asm.h,v 1.37 2025/01/06 10:46:44 martin Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -122,7 +122,7 @@
 
 /*
  * The m68k ALTENTRY macro is very different than the traditional
- * implementation used by other NetBSD ports.  Usually ALTENTRY 
+ * implementation used by other NetBSD ports.  Usually ALTENTRY
  * simply provides an alternate function entry point.  The m68k
  * definition takes a second argument and jumps inside the second
  * function when profiling is enabled.
@@ -139,9 +139,18 @@
 #define ALTENTRY(name, rname)	_ENTRY(_C_LABEL(name))
 #endif
 
+#ifdef _NETBSD_REVISIONID
 #define RCSID(x)	.pushsection ".ident","MS",@progbits,1;		\
 			.asciz x;					\
+			.ascii "$"; .ascii "NetBSD: "; .ascii __FILE__;	\
+			.ascii " "; .ascii _NETBSD_REVISIONID;		\
+			.asciz " $";					\
 			.popsection
+#else
+#define RCSID(x)	.pushsection ".ident","MS",@progbits,1;		\
+			.asciz x;					\
+			.popsection
+#endif
 
 /*
  * Global variables of whatever sort.

package/libc/include/m68k-netbsd-none/m68k/bus_dma.h

@@ -1,4 +1,4 @@
-/* $NetBSD: bus_dma.h,v 1.13 2021/12/05 04:54:20 msaitoh Exp $ */
+/* $NetBSD: bus_dma.h,v 1.14 2023/09/26 12:46:30 tsutsui Exp $ */
 
 /*
  * This file was extracted from alpha/include/bus.h
@@ -193,7 +193,7 @@ struct m68k_bus_dma_tag {
 #define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
 	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
 
-#define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP       
+#define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP
 #define bus_dmatag_destroy(t)
 
 /*

package/libc/include/m68k-netbsd-none/m68k/byte_swap.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: byte_swap.h,v 1.11 2014/03/18 18:20:41 riastradh Exp $	*/
+/*	$NetBSD: byte_swap.h,v 1.11.68.1 2025/12/18 19:57:52 martin Exp $	*/
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #define	M68K_BYTE_SWAP_H_
 
 #ifdef __GNUC__
-#include <sys/types.h>
+#include <sys/stdint.h>
 __BEGIN_DECLS
 
 

package/libc/include/m68k-netbsd-none/m68k/cacheops_30.h

@@ -1,4 +1,4 @@
-/*	$NetBSD: cacheops_30.h,v 1.9 2008/04/28 20:23:26 martin Exp $	*/
+/*	$NetBSD: cacheops_30.h,v 1.10 2023/09/26 12:46:30 tsutsui Exp $	*/
 
 /*-
  * Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -40,7 +40,7 @@ TBIA_30(void)
 	__asm volatile (" pflusha;"
 			  " movc %0,%%cacr" : : "d" (tmp));
 }
-	
+
 /*
  * Invalidate any TLB entry for given VA (TB Invalidate Single)
  */