@zigc/lib 0.17.0-dev.39 → 0.17.0-dev.420

package/std/zig/llvm/ir.zig

@@ -235,7 +235,7 @@ pub const ModuleBlock = struct {
         is_const: AddrSpaceAndIsConst,
         initid: u32,
         linkage: Builder.Linkage,
-        alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+        alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         section: usize,
         visibility: Builder.Visibility,
         thread_local: Builder.ThreadLocal,
@@ -275,7 +275,7 @@ pub const ModuleBlock = struct {
         is_proto: bool,
         linkage: Builder.Linkage,
         paramattr: usize,
-        alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+        alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         section: usize,
         visibility: Builder.Visibility,
         unnamed_addr: Builder.UnnamedAddr,
@@ -1214,7 +1214,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             ty: Builder.Type,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
         };
 
@@ -1230,7 +1230,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             ty: Builder.Type,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
@@ -1246,7 +1246,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             val: u32,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
         };
 
@@ -1262,7 +1262,7 @@ pub const ModuleBlock = struct {
             };
             ptr: u32,
             val: u32,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
@@ -1317,7 +1317,7 @@ pub const ModuleBlock = struct {
             is_volatile: bool,
             success_ordering: Builder.AtomicOrdering,
             sync_scope: Builder.SyncScope,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         };
 
         pub const CmpXchg = struct {
@@ -1341,7 +1341,7 @@ pub const ModuleBlock = struct {
             sync_scope: Builder.SyncScope,
             failure_ordering: Builder.AtomicOrdering,
             is_weak: bool,
-            alignment: std.meta.Int(.unsigned, @bitSizeOf(Builder.Alignment)),
+            alignment: @Int(.unsigned, @bitSizeOf(Builder.Alignment)),
         };
 
         pub const Fence = struct {

package/std/zig/system/arm.zig

@@ -21,7 +21,7 @@ pub const cpu_models = struct {
     };
 
     // implementer = 0x41
-    const ARM = [_]E{
+    const Arm = [_]E{
         E{ .part = 0x926, .m32 = &A32.arm926ej_s },
         E{ .part = 0xb02, .m32 = &A32.mpcore },
         E{ .part = 0xb36, .m32 = &A32.arm1136j_s },
@@ -88,8 +88,12 @@ pub const cpu_models = struct {
         E{ .part = 0xd87, .m64 = &A64.cortex_a725 },
         E{ .part = 0xd88, .m64 = &A64.cortex_a520ae },
         E{ .part = 0xd89, .m64 = &A64.cortex_a720ae },
+        E{ .part = 0xd8a, .m64 = &A64.c1_nano },
+        E{ .part = 0xd8b, .m64 = &A64.c1_pro },
+        E{ .part = 0xd8c, .m64 = &A64.c1_ultra },
         E{ .part = 0xd8e, .m64 = &A64.neoverse_n3 },
         E{ .part = 0xd8f, .m64 = &A64.cortex_a320 },
+        E{ .part = 0xd90, .m64 = &A64.c1_premium },
     };
     // implementer = 0x42
     const Broadcom = [_]E{
@@ -102,10 +106,17 @@ pub const cpu_models = struct {
         E{ .part = 0x0a3, .m64 = &A64.thunderxt83 },
         E{ .part = 0x0a1, .m64 = &A64.thunderxt88 },
         E{ .part = 0x0af, .m64 = &A64.thunderx2t99 },
+        E{ .part = 0x0b0, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b1, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b2, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b3, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b4, .m64 = &A64.cortex_a57 },
+        E{ .part = 0x0b5, .m64 = &A64.cortex_a57 },
     };
     // implementer = 0x46
     const Fujitsu = [_]E{
         E{ .part = 0x001, .m64 = &A64.a64fx },
+        E{ .part = 0x003, .m64 = &A64.fujitsu_monaka },
     };
     // implementer = 0x48
     const HiSilicon = [_]E{
@@ -137,8 +148,14 @@ pub const cpu_models = struct {
         E{ .part = 0xc00, .m64 = &A64.falkor },
         E{ .part = 0xc01, .m64 = &A64.saphira },
     };
+    // implementer = 0x53
+    const Samsung = [_]E{
+        E{ .part = 0x000, .m64 = &A64.exynos_m1 },
+    };
     // implementer = 0x61
     const Apple = [_]E{
+        E{ .part = 0x020, .m64 = &A64.apple_m1 },
+        E{ .part = 0x021, .m64 = &A64.apple_m1 },
         E{ .part = 0x022, .m64 = &A64.apple_m1 },
         E{ .part = 0x023, .m64 = &A64.apple_m1 },
         E{ .part = 0x024, .m64 = &A64.apple_m1 },
@@ -151,11 +168,43 @@ pub const cpu_models = struct {
         E{ .part = 0x035, .m64 = &A64.apple_m2 },
         E{ .part = 0x038, .m64 = &A64.apple_m2 },
         E{ .part = 0x039, .m64 = &A64.apple_m2 },
+        E{ .part = 0x042, .m64 = &A64.apple_m3 },
+        E{ .part = 0x043, .m64 = &A64.apple_m3 },
+        E{ .part = 0x044, .m64 = &A64.apple_m3 },
+        E{ .part = 0x045, .m64 = &A64.apple_m3 },
+        E{ .part = 0x048, .m64 = &A64.apple_m3 },
+        E{ .part = 0x049, .m64 = &A64.apple_m3 },
+        E{ .part = 0x052, .m64 = &A64.apple_m4 },
+        E{ .part = 0x053, .m64 = &A64.apple_m4 },
+        E{ .part = 0x054, .m64 = &A64.apple_m4 },
+        E{ .part = 0x055, .m64 = &A64.apple_m4 },
+        E{ .part = 0x058, .m64 = &A64.apple_m4 },
+        E{ .part = 0x059, .m64 = &A64.apple_m4 },
+    };
+    // implementer = 0x63
+    const ArmChina = [_]E{
+        E{ .part = 0x132, .m32 = &A32.star_mc1 },
+        E{ .part = 0xd25, .m32 = &A32.star_mc3 },
+    };
+    // implementer = 0x68
+    const Hxt = [_]E{
+        E{ .part = 0x000, .m64 = &A64.cortex_a57 },
+    };
+    // implementer = 0x6d
+    const Microsoft = [_]E{
+        E{ .part = 0xd49, .m64 = &A64.neoverse_n2 },
+    };
+    // implementer = 0xC0
+    const AmpereOne = [_]E{
+        E{ .part = 0xac3, .m64 = &A64.ampere1 },
+        E{ .part = 0xac4, .m64 = &A64.ampere1a },
+        E{ .part = 0xac5, .m64 = &A64.ampere1b },
+        E{ .part = 0xac7, .m64 = &A64.ampere1c },
     };
 
     pub fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model {
         const models = switch (core.implementer) {
-            0x41 => &ARM,
+            0x41 => &Arm,
             0x42 => &Broadcom,
             0x43 => &Cavium,
             0x46 => &Fujitsu,
@@ -163,7 +212,12 @@ pub const cpu_models = struct {
             0x4e => &Nvidia,
             0x50 => &Ampere,
             0x51 => &Qualcomm,
+            0x53 => &Samsung,
             0x61 => &Apple,
+            0x63 => &ArmChina,
+            0x68 => &Hxt,
+            0x6d => &Microsoft,
+            0xC0 => &AmpereOne,
             else => return null,
         };
 

package/std/zig/system/linux.zig

@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
     model: ?*const Target.Cpu.Model = null,
 
     const cpu_names = .{
+        .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
+        .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
         .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
+        .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {

package/std/zig/system/loongarch.zig

@@ -31,21 +31,37 @@ pub fn detectNativeCpuAndFeatures(
 
     cpu.features.addFeatureSet(cpu.model.features);
 
-    const cfg1 = cpucfg(1);
     const cfg2 = cpucfg(2);
     const cfg3 = cpucfg(3);
 
-    setFeature(&cpu, .ual, bit(cfg1, 20));
+    if (builtin.os.tag == .linux) {
+        const HWCAP = std.os.linux.HWCAP;
+        const hwcap_bits: usize = if (builtin.link_libc)
+            std.c.getauxval(std.elf.AT_HWCAP)
+        else
+            std.os.linux.getauxval(std.elf.AT_HWCAP);
 
-    const has_fpu = bit(cfg2, 0);
-    setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
-    setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
 
-    setFeature(&cpu, .lsx, bit(cfg2, 6));
-    setFeature(&cpu, .lasx, bit(cfg2, 7));
-    setFeature(&cpu, .lvz, bit(cfg2, 10));
+        const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
+        setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
+        setFeature(&cpu, .d, has_fpu and bit(cfg2, 2));
+        setFeature(&cpu, .lsx, (hwcap_bits & HWCAP.LSX) != 0);
+        setFeature(&cpu, .lasx, (hwcap_bits & HWCAP.LASX) != 0);
 
-    setFeature(&cpu, .lbt, bit(cfg2, 18) and bit(cfg2, 19) and bit(cfg2, 20));
+        setFeature(&cpu, .lvz, (hwcap_bits & HWCAP.LVZ) != 0);
+        setFeature(&cpu, .lbt, (hwcap_bits & HWCAP.LBT_X86) != 0 and (hwcap_bits & HWCAP.LBT_ARM) != 0 and (hwcap_bits & HWCAP.LBT_MIPS) != 0);
+    } else {
+        setFeature(&cpu, .ual, false);
+
+        setFeature(&cpu, .f, false);
+        setFeature(&cpu, .d, false);
+        setFeature(&cpu, .lsx, false);
+        setFeature(&cpu, .lasx, false);
+
+        setFeature(&cpu, .lvz, false);
+        setFeature(&cpu, .lbt, false);
+    }
 
     setFeature(&cpu, .frecipe, bit(cfg2, 25));
     setFeature(&cpu, .div32, bit(cfg2, 26));

package/std/zig/system/windows.zig

@@ -215,10 +215,43 @@ fn genericCpuAndNativeFeatures(arch: Target.Cpu.Arch) Target.Cpu {
             // Override any features that are either present or absent
             setFeature(Feature, &cpu, .neon, IsProcessorFeaturePresent(PF.ARM_NEON_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .crc, IsProcessorFeaturePresent(PF.ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE));
-            setFeature(Feature, &cpu, .crypto, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .aes, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sha2, IsProcessorFeaturePresent(PF.ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .lse, IsProcessorFeaturePresent(PF.ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .dotprod, IsProcessorFeaturePresent(PF.ARM_V82_DP_INSTRUCTIONS_AVAILABLE));
             setFeature(Feature, &cpu, .jsconv, IsProcessorFeaturePresent(PF.ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .rcpc, IsProcessorFeaturePresent(PF.ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve, IsProcessorFeaturePresent(PF.ARM_SVE_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve2, IsProcessorFeaturePresent(PF.ARM_SVE2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve2p1, IsProcessorFeaturePresent(PF.ARM_SVE2_1_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_aes, IsProcessorFeaturePresent(PF.ARM_SVE_AES_INSTRUCTIONS_AVAILABLE) or IsProcessorFeaturePresent(PF.ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_bitperm, IsProcessorFeaturePresent(PF.ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .bf16, IsProcessorFeaturePresent(PF.ARM_V86_BF16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_b16b16, IsProcessorFeaturePresent(PF.ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_sha3, IsProcessorFeaturePresent(PF.ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sve_sm4, IsProcessorFeaturePresent(PF.ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .i8mm, IsProcessorFeaturePresent(PF.ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .f32mm, IsProcessorFeaturePresent(PF.ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .f64mm, IsProcessorFeaturePresent(PF.ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme, IsProcessorFeaturePresent(PF.ARM_SME_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2, IsProcessorFeaturePresent(PF.ARM_SME2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .lse2, IsProcessorFeaturePresent(PF.ARM_LSE2_AVAILABLE));
+            setFeature(Feature, &cpu, .sha3, IsProcessorFeaturePresent(PF.ARM_SHA3_INSTRUCTIONS_AVAILABLE) and IsProcessorFeaturePresent(PF.ARM_SHA512_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .fullfp16, IsProcessorFeaturePresent(PF.ARM_V82_FP16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2p1, IsProcessorFeaturePresent(PF.ARM_SME2_1_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme2p2, IsProcessorFeaturePresent(PF.ARM_SME2_2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_aes, IsProcessorFeaturePresent(PF.ARM_SME_AES_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_bitperm, IsProcessorFeaturePresent(PF.ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8dot2, IsProcessorFeaturePresent(PF.ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8dot4, IsProcessorFeaturePresent(PF.ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .ssve_fp8fma, IsProcessorFeaturePresent(PF.ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f8f32, IsProcessorFeaturePresent(PF.ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f8f16, IsProcessorFeaturePresent(PF.ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_b16b16, IsProcessorFeaturePresent(PF.ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_f64f64, IsProcessorFeaturePresent(PF.ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_i16i64, IsProcessorFeaturePresent(PF.ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_lutv2, IsProcessorFeaturePresent(PF.ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE));
+            setFeature(Feature, &cpu, .sme_fa64, IsProcessorFeaturePresent(PF.ARM_SME_FA64_INSTRUCTIONS_AVAILABLE));
         },
         else => {},
     }

package/std/zig/system/x86.zig

@@ -232,7 +232,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
                     cpu.model = &Target.x86.cpu.lunarlake;
                     return;
                 },
-                0xcc => {
+                0xcc, 0xd5 => {
                     cpu.model = &Target.x86.cpu.pantherlake;
                     return;
                 },
@@ -307,6 +307,20 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
             cpu.model = &Target.x86.cpu.pentium4;
             return;
         },
+        18 => switch (model) {
+            0x01, 0x03 => {
+                cpu.model = &Target.x86.cpu.novalake;
+                return;
+            },
+            else => return, // Unknown CPU Model
+        },
+        19 => switch (model) {
+            0x01 => {
+                cpu.model = &Target.x86.cpu.diamondrapids;
+                return;
+            },
+            else => return, // Unknown CPU Model
+        },
         else => return, // Unknown CPU Model
     }
 }
@@ -412,6 +426,8 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
     // AMX requires additional context to be saved by the OS.
     const has_amx_save = xcr0.xtilecfg and xcr0.xtiledata;
 
+    const has_apx_save = xcr0.apx;
+
     setFeature(cpu, .avx, has_avx_save);
     setFeature(cpu, .fma, bit(leaf.ecx, 12) and has_avx_save);
     // Only enable XSAVE if OS has enabled support for saving YMM state.
@@ -470,7 +486,20 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
         }
     }
 
-    if (max_level >= 0x7) {
+    if (max_ext_level >= 0x80000021) {
+        leaf = cpuid(0x80000021, 0);
+
+        // AMD uses a different bit for prefetchi.
+        setFeature(cpu, .prefetchi, bit(leaf.eax, 20));
+    } else {
+        for ([_]Target.x86.Feature{
+            .prefetchi,
+        }) |feat| {
+            setFeature(cpu, feat, false);
+        }
+    }
+
+    const has_avx10 = if (max_level >= 0x7) has_avx10: {
         leaf = cpuid(0x7, 0);
 
         setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
@@ -484,7 +513,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
         setFeature(cpu, .rtm, bit(leaf.ebx, 11));
         // AVX512 is only supported if the OS supports the context save for it.
         setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
-        setFeature(cpu, .evex512, bit(leaf.ebx, 16) and has_avx512_save);
         setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
         setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
         setFeature(cpu, .adx, bit(leaf.ebx, 19));
@@ -556,15 +584,20 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             setFeature(cpu, .avxneconvert, bit(leaf.edx, 5) and has_avx_save);
             setFeature(cpu, .amx_complex, bit(leaf.edx, 8) and has_amx_save);
             setFeature(cpu, .avxvnniint16, bit(leaf.edx, 10) and has_avx_save);
-            setFeature(cpu, .prefetchi, bit(leaf.edx, 14));
+            // This needs to account for prefetchi already being detected above on AMD.
+            setFeature(cpu, .prefetchi, cpu.has(.x86, .prefetchi) or bit(leaf.edx, 14));
             setFeature(cpu, .usermsr, bit(leaf.edx, 15));
             // APX
-            setFeature(cpu, .egpr, bit(leaf.edx, 21));
-            setFeature(cpu, .push2pop2, bit(leaf.edx, 21));
-            setFeature(cpu, .ppx, bit(leaf.edx, 21));
-            setFeature(cpu, .ndd, bit(leaf.edx, 21));
-            setFeature(cpu, .ccmp, bit(leaf.edx, 21));
-            setFeature(cpu, .cf, bit(leaf.edx, 21));
+            setFeature(cpu, .egpr, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .push2pop2, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ppx, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ndd, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .ccmp, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .nf, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .cf, bit(leaf.edx, 21) and has_apx_save);
+            setFeature(cpu, .zu, bit(leaf.edx, 21) and has_apx_save);
+
+            break :has_avx10 bit(leaf.edx, 19);
         } else {
             for ([_]Target.x86.Feature{
                 .sha512,
@@ -582,19 +615,23 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
                 .avxneconvert,
                 .amx_complex,
                 .avxvnniint16,
-                .prefetchi,
+                // prefetchi already handled earlier.
                 .usermsr,
                 .egpr,
                 .push2pop2,
                 .ppx,
                 .ndd,
                 .ccmp,
+                .nf,
                 .cf,
+                .zu,
             }) |feat| {
                 setFeature(cpu, feat, false);
             }
         }
-    } else {
+
+        break :has_avx10 false;
+    } else has_avx10: {
         for ([_]Target.x86.Feature{
             .fsgsbase,
             .sgx,
@@ -605,7 +642,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             .invpcid,
             .rtm,
             .avx512f,
-            .evex512,
             .avx512dq,
             .rdseed,
             .adx,
@@ -664,18 +700,22 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
             .avxneconvert,
             .amx_complex,
             .avxvnniint16,
-            .prefetchi,
+            // prefetchi already handled earlier.
             .usermsr,
             .egpr,
             .push2pop2,
             .ppx,
             .ndd,
             .ccmp,
+            .nf,
             .cf,
+            .zu,
         }) |feat| {
             setFeature(cpu, feat, false);
         }
-    }
+
+        break :has_avx10 false;
+    };
 
     if (max_level >= 0xD and has_avx_save) {
         leaf = cpuid(0xD, 0x1);
@@ -721,10 +761,14 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
     if (max_level >= 0x24) {
         leaf = cpuid(0x24, 0);
 
-        setFeature(cpu, .avx10_1, bit(leaf.ebx, 18));
+        const avx_ver = leaf.ebx & 0xff;
+
+        setFeature(cpu, .avx10_1, has_avx10 and avx_ver >= 1);
+        setFeature(cpu, .avx10_2, has_avx10 and avx_ver >= 2);
     } else {
         for ([_]Target.x86.Feature{
             .avx10_1,
+            .avx10_2,
         }) |feat| {
             setFeature(cpu, feat, false);
         }

package/std/zig/system.zig

@@ -461,14 +461,8 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target {
             result.cpu.features.removeFeature(@intFromEnum(Target.arm.Feature.vfp2));
         }
 
-        // https://github.com/llvm/llvm-project/issues/135283
-        if (result.cpu.arch.isMIPS() and result.abi.float() == .soft) {
-            result.cpu.features.addFeature(@intFromEnum(Target.mips.Feature.soft_float));
-        }
-
-        // https://github.com/llvm/llvm-project/issues/168992
-        if (result.cpu.arch == .s390x) {
-            result.cpu.features.removeFeature(@intFromEnum(Target.s390x.Feature.vector));
+        if (result.cpu.arch.isXtensa() and result.abi == .call0) {
+            result.cpu.features.removeFeature(@intFromEnum(Target.xtensa.Feature.windowed));
         }
     }
 

package/std/zig/target.zig

@@ -76,15 +76,12 @@ pub const available_libcs = [_]ArchOsAbi{
     .{ .arch = .mips64el, .os = .linux, .abi = .muslabi64, .os_ver = .{ .major = 2, .minor = 3, .patch = 48 } },
     .{ .arch = .mips64el, .os = .linux, .abi = .muslabin32, .os_ver = .{ .major = 2, .minor = 6, .patch = 0 } },
     .{ .arch = .mips64el, .os = .openbsd, .abi = .none, .os_ver = .{ .major = 4, .minor = 7, .patch = 0 } },
-    .{ .arch = .powerpc, .os = .linux, .abi = .gnueabi, .os_ver = .{ .major = 1, .minor = 3, .patch = 45 }, .glibc_triple = "powerpc-linux-gnu-soft" },
-    .{ .arch = .powerpc, .os = .linux, .abi = .gnueabihf, .os_ver = .{ .major = 1, .minor = 3, .patch = 45 }, .glibc_triple = "powerpc-linux-gnu" },
     .{ .arch = .powerpc, .os = .linux, .abi = .musleabi, .os_ver = .{ .major = 1, .minor = 3, .patch = 45 } },
     .{ .arch = .powerpc, .os = .linux, .abi = .musleabihf, .os_ver = .{ .major = 1, .minor = 3, .patch = 45 } },
     .{ .arch = .powerpc, .os = .netbsd, .abi = .eabi, .os_ver = .{ .major = 6, .minor = 0, .patch = 0 } },
     .{ .arch = .powerpc, .os = .netbsd, .abi = .eabihf, .os_ver = .{ .major = 1, .minor = 4, .patch = 0 } },
     .{ .arch = .powerpc, .os = .openbsd, .abi = .eabihf, .os_ver = .{ .major = 2, .minor = 8, .patch = 0 } },
     .{ .arch = .powerpc64, .os = .freebsd, .abi = .none, .os_ver = .{ .major = 8, .minor = 0, .patch = 0 } },
-    .{ .arch = .powerpc64, .os = .linux, .abi = .gnu, .os_ver = .{ .major = 2, .minor = 6, .patch = 0 } },
     .{ .arch = .powerpc64, .os = .linux, .abi = .musl, .os_ver = .{ .major = 2, .minor = 6, .patch = 0 } },
     .{ .arch = .powerpc64, .os = .openbsd, .abi = .none, .os_ver = .{ .major = 6, .minor = 8, .patch = 0 } },
     .{ .arch = .powerpc64le, .os = .freebsd, .abi = .none, .os_ver = .{ .major = 13, .minor = 0, .patch = 0 } },
@@ -245,7 +242,7 @@ pub fn glibcArchNameHeaders(arch: std.Target.Cpu.Arch) [:0]const u8 {
         .arm, .armeb => "arm",
         .loongarch64 => "loongarch",
         .mips, .mipsel, .mips64, .mips64el => "mips",
-        .powerpc, .powerpc64, .powerpc64le => "powerpc",
+        .powerpc64le => "powerpc",
         .riscv32, .riscv64 => "riscv",
         .sparc, .sparc64 => "sparc",
         .x86, .x86_64 => "x86",

package/std/zig/tokenizer.zig

@@ -64,7 +64,6 @@ pub const Token = struct {
 
     pub const Tag = enum {
         invalid,
-        invalid_periodasterisks,
         identifier,
         string_literal,
         multiline_string_literal_line,
@@ -109,7 +108,6 @@ pub const Token = struct {
         minus_pipe_equal,
         asterisk,
         asterisk_equal,
-        asterisk_asterisk,
         asterisk_percent,
         asterisk_percent_equal,
         asterisk_pipe,
@@ -197,7 +195,6 @@ pub const Token = struct {
                 .container_doc_comment,
                 => null,
 
-                .invalid_periodasterisks => ".**",
                 .bang => "!",
                 .pipe => "|",
                 .pipe_pipe => "||",
@@ -236,7 +233,6 @@ pub const Token = struct {
                 .minus_pipe_equal => "-|=",
                 .asterisk => "*",
                 .asterisk_equal => "*=",
-                .asterisk_asterisk => "**",
                 .asterisk_percent => "*%",
                 .asterisk_percent_equal => "*%=",
                 .asterisk_pipe => "*|",
@@ -386,7 +382,6 @@ pub const Tokenizer = struct {
         angle_bracket_angle_bracket_right,
         period,
         period_2,
-        period_asterisk,
         saw_at_sign,
         invalid,
     };
@@ -569,10 +564,6 @@ pub const Tokenizer = struct {
                         result.tag = .asterisk_equal;
                         self.index += 1;
                     },
-                    '*' => {
-                        result.tag = .asterisk_asterisk;
-                        self.index += 1;
-                    },
                     '%' => continue :state .asterisk_percent,
                     '|' => continue :state .asterisk_pipe,
                     else => result.tag = .asterisk,
@@ -915,7 +906,10 @@ pub const Tokenizer = struct {
                 self.index += 1;
                 switch (self.buffer[self.index]) {
                     '.' => continue :state .period_2,
-                    '*' => continue :state .period_asterisk,
+                    '*' => {
+                        result.tag = .period_asterisk;
+                        self.index += 1;
+                    },
                     else => result.tag = .period,
                 }
             },
@@ -931,14 +925,6 @@ pub const Tokenizer = struct {
                 }
             },
 
-            .period_asterisk => {
-                self.index += 1;
-                switch (self.buffer[self.index]) {
-                    '*' => result.tag = .invalid_periodasterisks,
-                    else => result.tag = .period_asterisk,
-                }
-            },
-
             .slash => {
                 self.index += 1;
                 switch (self.buffer[self.index]) {
@@ -1343,31 +1329,6 @@ test "correctly parse pointer assignment" {
     });
 }
 
-test "correctly parse pointer dereference followed by asterisk" {
-    try testTokenize("\"b\".* ** 10", &.{
-        .string_literal,
-        .period_asterisk,
-        .asterisk_asterisk,
-        .number_literal,
-    });
-
-    try testTokenize("(\"b\".*)** 10", &.{
-        .l_paren,
-        .string_literal,
-        .period_asterisk,
-        .r_paren,
-        .asterisk_asterisk,
-        .number_literal,
-    });
-
-    try testTokenize("\"b\".*** 10", &.{
-        .string_literal,
-        .invalid_periodasterisks,
-        .asterisk_asterisk,
-        .number_literal,
-    });
-}
-
 test "range literals" {
     try testTokenize("0...9", &.{ .number_literal, .ellipsis3, .number_literal });
     try testTokenize("'0'...'9'", &.{ .char_literal, .ellipsis3, .char_literal });

package/std/zig.zig

@@ -744,6 +744,7 @@ pub fn parseTargetQueryOrReportFatalError(
 pub const EnvVar = enum {
     ZIG_GLOBAL_CACHE_DIR,
     ZIG_LOCAL_CACHE_DIR,
+    ZIG_LOCAL_PKG_DIR,
     ZIG_LIB_DIR,
     ZIG_LIBC,
     ZIG_BUILD_RUNNER,
@@ -810,7 +811,6 @@ pub const SimpleComptimeReason = enum(u32) {
     compile_error_string,
     inline_assembly_code,
     atomic_order,
-    array_mul_factor,
     slice_cat_operand,
     inline_call_target,
     generic_call_target,
@@ -876,7 +876,7 @@ pub const SimpleComptimeReason = enum(u32) {
     casted_to_comptime_enum,
     casted_to_comptime_int,
     casted_to_comptime_float,
-    std_builtin_decl,
+    std_lang_decl,
 
     pub fn message(r: SimpleComptimeReason) []const u8 {
         return switch (r) {
@@ -898,7 +898,6 @@ pub const SimpleComptimeReason = enum(u32) {
             .compile_error_string => "compile error string must be comptime-known",
             .inline_assembly_code => "inline assembly code must be comptime-known",
             .atomic_order         => "atomic order must be comptime-known",
-            .array_mul_factor     => "array multiplication factor must be comptime-known",
             .slice_cat_operand    => "slice being concatenated must be comptime-known",
             .inline_call_target   => "function being called inline must be comptime-known",
             .generic_call_target  => "generic function being called must be comptime-known",
@@ -960,7 +959,7 @@ pub const SimpleComptimeReason = enum(u32) {
             .casted_to_comptime_enum      => "value casted to enum with 'comptime_int' tag type must be comptime-known",
             .casted_to_comptime_int       => "value casted to 'comptime_int' must be comptime-known",
             .casted_to_comptime_float     => "value casted to 'comptime_float' must be comptime-known",
-            .std_builtin_decl             => "'std.builtin' declaration values must be comptime-known",
+            .std_lang_decl                => "'std.lang' declaration values must be comptime-known",
             // zig fmt: on
         };
     }