@zigc/lib 0.17.0-dev.39 → 0.17.0-dev.420

package/std/os/plan9.zig

@@ -299,7 +299,7 @@ pub fn openat(dirfd: i32, path: [*:0]const u8, flags: u32, _: mode_t) usize {
     const dir_path = std.mem.span(@as([*:0]u8, @ptrCast(&dir_path_buf)));
     const total_path = std.fs.path.join(alloc, &.{ dir_path, std.mem.span(path) }) catch unreachable; // the allocation shouldn't fail because it should not exceed max_path_bytes
     fba.reset();
-    const total_path_z = alloc.dupeZ(u8, total_path) catch unreachable; // should not exceed max_path_bytes + 1
+    const total_path_z = alloc.dupeSentinel(u8, total_path, 0) catch unreachable; // should not exceed max_path_bytes + 1
     return open(total_path_z.ptr, flags);
 }
 

package/std/os/uefi/hii.zig

@@ -66,7 +66,7 @@ pub const WideGlyph = extern struct {
     attributes: WideGlyphAttributes,
     glyph_col_1: [19]u8,
     glyph_col_2: [19]u8,
-    _pad: [3]u8 = [_]u8{0} ** 3,
+    _pad: [3]u8 = @splat(0),
 };
 
 pub const StringPackage = extern struct {

package/std/os/uefi/tables/boot_services.zig

@@ -158,12 +158,10 @@ pub const BootServices = extern struct {
     _locateProtocol: *const fn (protocol: *const Guid, registration: ?EventRegistration, interface: *?*const anyopaque) callconv(cc) Status,
 
     /// Installs one or more protocol interfaces into the boot services environment
-    // TODO: use callconv(cc) instead once that works
-    _installMultipleProtocolInterfaces: *const fn (handle: *Handle, ...) callconv(.c) Status,
+    _installMultipleProtocolInterfaces: *const fn (handle: *?Handle, ...) callconv(cc) Status,
 
     /// Removes one or more protocol interfaces into the boot services environment
-    // TODO: use callconv(cc) instead once that works
-    _uninstallMultipleProtocolInterfaces: *const fn (handle: *Handle, ...) callconv(.c) Status,
+    _uninstallMultipleProtocolInterfaces: *const fn (handle: Handle, ...) callconv(cc) Status,
 
     /// Computes and returns a 32-bit CRC for a data buffer.
     _calculateCrc32: *const fn (data: [*]const u8, data_size: usize, *u32) callconv(cc) Status,
@@ -1238,8 +1236,9 @@ fn protocolInterfaces(
         @TypeOf(interfaces),
     ) = undefined;
     result[0] = handle_arg;
+    result[result.len - 1] = null;
 
-    var idx: usize = 1;
+    comptime var idx: usize = 1;
     inline for (interfaces) |interface| {
         const InterfacePtr = @TypeOf(interface);
         const Interface = switch (@typeInfo(InterfacePtr)) {
@@ -1272,13 +1271,15 @@ fn ProtocolInterfaces(HandleType: type, Interfaces: type) type {
         @compileError("expected tuple of protocol interfaces, got " ++ @typeName(Interfaces));
     const interfaces_info = interfaces_type_info.@"struct";
 
-    var tuple_types: [interfaces_info.fields.len * 2 + 1]type = undefined;
+    var tuple_types: [interfaces_info.fields.len * 2 + 2]type = undefined;
     tuple_types[0] = HandleType;
+    tuple_types[tuple_types.len - 1] = ?*const Guid;
+
     var idx = 1;
-    while (idx < tuple_types.len) : (idx += 2) {
+    while (idx < tuple_types.len - 1) : (idx += 2) {
         tuple_types[idx] = *const Guid;
         tuple_types[idx + 1] = *const anyopaque;
     }
 
-    return std.meta.Tuple(tuple_types[0..]);
+    return @Tuple(tuple_types[0..]);
 }

package/std/os/uefi/tables/runtime_services.zig

@@ -419,7 +419,7 @@ pub const RuntimeServices = extern struct {
     pub const DebugDisposition = enum(usize) {
         const Bits = packed struct(usize) {
             optional_ptr: bool = false,
-            _pad: std.meta.Int(.unsigned, @bitSizeOf(usize) - 1) = 0,
+            _pad: @Int(.unsigned, @bitSizeOf(usize) - 1) = 0,
         };
 
         pointer = @bitCast(Bits{}),

package/std/os/windows.zig

@@ -5665,7 +5665,136 @@ pub const PF = enum(DWORD) {
     ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE = 44,
 
     /// This Arm processor implements the Arm v8.3 LRCPC instructions (for example, LDAPR). Note that certain Arm v8.2 CPUs may optionally support the LRCPC instructions.
-    ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE,
+    ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE = 45,
+
+    /// This Arm processor implements the SVE (Scalable Vector Extension) instructions (FEAT_SVE).
+    ARM_SVE_INSTRUCTIONS_AVAILABLE = 46,
+
+    /// This Arm processor implements the SVE2 instructions (FEAT_SVE2).
+    ARM_SVE2_INSTRUCTIONS_AVAILABLE = 47,
+
+    /// This Arm processor implements the SVE2.1 instructions (FEAT_SVE2p1).
+    ARM_SVE2_1_INSTRUCTIONS_AVAILABLE = 48,
+
+    /// This Arm processor implements the SVE AES instructions (FEAT_SVE_AES).
+    ARM_SVE_AES_INSTRUCTIONS_AVAILABLE = 49,
+
+    /// This Arm processor implements the SVE 128-bit polynomial multiply long instructions (FEAT_SVE_PMULL128).
+    ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE = 50,
+
+    /// This Arm processor implements the SVE bit permute instructions (FEAT_SVE_BitPerm).
+    ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE = 51,
+
+    /// This Arm processor implements the SVE BF16 (BFloat16) instructions (FEAT_BF16).
+    ARM_SVE_BF16_INSTRUCTIONS_AVAILABLE = 52,
+
+    /// This Arm processor implements the SVE EBF16 (Extended BFloat16) instructions (FEAT_EBF16).
+    ARM_SVE_EBF16_INSTRUCTIONS_AVAILABLE = 53,
+
+    /// This Arm processor implements the SVE B16B16 instructions (FEAT_SVE_B16B16).
+    ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE = 54,
+
+    /// This Arm processor implements the SVE SHA-3 cryptographic instructions (FEAT_SVE_SHA3).
+    ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE = 55,
+
+    /// This Arm processor implements the SVE SM4 cryptographic instructions (FEAT_SVE_SM4).
+    ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE = 56,
+
+    /// This Arm processor implements the SVE I8MM (Int8 matrix multiply) instructions (FEAT_I8MM).
+    ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE = 57,
+
+    /// This Arm processor implements the SVE F32MM (FP32 matrix multiply) instructions (FEAT_F32MM).
+    ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE = 58,
+
+    /// This Arm processor implements the SVE F64MM (FP64 matrix multiply) instructions (FEAT_F64MM).
+    ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE = 59,
+
+    /// This x64 processor implements the BMI2 instruction set.
+    BMI2_INSTRUCTIONS_AVAILABLE = 60,
+
+    /// This x64 processor implements the MOVDIR64B instruction.
+    MOVDIR64B_INSTRUCTION_AVAILABLE = 61,
+
+    /// This Arm processor implements the LSE2 atomic instructions (FEAT_LSE2).
+    ARM_LSE2_AVAILABLE = 62,
+
+    /// This Arm processor implements the SHA-3 cryptographic instructions (FEAT_SHA3).
+    ARM_SHA3_INSTRUCTIONS_AVAILABLE = 64,
+
+    /// This Arm processor implements the SHA-512 cryptographic instructions (FEAT_SHA512).
+    ARM_SHA512_INSTRUCTIONS_AVAILABLE = 65,
+
+    /// This Arm processor implements the I8MM (Int8 matrix multiply) NEON instructions (FEAT_I8MM).
+    ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE = 66,
+
+    /// This Arm processor implements the FP16 (half-precision floating point) NEON instructions (FEAT_FP16).
+    ARM_V82_FP16_INSTRUCTIONS_AVAILABLE = 67,
+
+    /// This Arm processor implements the BF16 (BFloat16) NEON instructions (FEAT_BF16).
+    ARM_V86_BF16_INSTRUCTIONS_AVAILABLE = 68,
+
+    /// This Arm processor implements the EBF16 (Extended BFloat16) NEON instructions (FEAT_EBF16).
+    ARM_V86_EBF16_INSTRUCTIONS_AVAILABLE = 69,
+
+    /// This Arm processor implements the SME (Scalable Matrix Extension) instructions (FEAT_SME).
+    ARM_SME_INSTRUCTIONS_AVAILABLE = 70,
+
+    /// This Arm processor implements the SME2 instructions (FEAT_SME2).
+    ARM_SME2_INSTRUCTIONS_AVAILABLE = 71,
+
+    /// This Arm processor implements the SME2.1 instructions (FEAT_SME2p1).
+    ARM_SME2_1_INSTRUCTIONS_AVAILABLE = 72,
+
+    /// This Arm processor implements the SME2.2 instructions (FEAT_SME2p2).
+    ARM_SME2_2_INSTRUCTIONS_AVAILABLE = 73,
+
+    /// This Arm processor implements the SVE AES instructions when in Streaming SVE mode (FEAT_SSVE_AES).
+    ARM_SME_AES_INSTRUCTIONS_AVAILABLE = 74,
+
+    /// This Arm processor implements the SVE bit permute instructions when in Streaming SVE mode (FEAT_SSVE_BitPerm).
+    ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE = 75,
+
+    /// This Arm processor implements the SVE FMMLA (widening, 4-way, FP8 to FP16) instruction when in Streaming SVE mode (FEAT_SSVE_F8F16MM).
+    ARM_SME_SF8MM4_INSTRUCTIONS_AVAILABLE = 76,
+
+    /// This Arm processor implements the SVE FMMLA (widening, 8-way, FP8 to FP32) instruction when in Streaming SVE mode (FEAT_SSVE_F8F32MM).
+    ARM_SME_SF8MM8_INSTRUCTIONS_AVAILABLE = 77,
+
+    /// This Arm processor implements the SVE2 FP8DOT2 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT2).
+    ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE = 78,
+
+    /// This Arm processor implements the SVE2 FP8DOT4 instructions when in Streaming SVE mode (FEAT_SSVE_FP8DOT4).
+    ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE = 79,
+
+    /// This Arm processor implements the SVE2 FP8FMA instructions when in Streaming SVE mode (FEAT_SSVE_FP8FMA).
+    ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE = 80,
+
+    /// This Arm processor implements the SME F8F32 instructions (FEAT_SME_F8F32).
+    ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE = 81,
+
+    /// This Arm processor implements the SME F8F16 instructions (FEAT_SME_F8F16).
+    ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE = 82,
+
+    /// This Arm processor implements the SME F16F16 instructions (FEAT_SME_F16F16).
+    ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE = 83,
+
+    /// This Arm processor implements the SME B16B16 instructions (FEAT_SME_B16B16).
+    ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE = 84,
+
+    /// This Arm processor implements the SME F64F64 instructions (FEAT_SME_F64F64).
+    ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE = 85,
+
+    /// This Arm processor implements the SME I16I64 instructions (FEAT_SME_I16I64).
+    ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE = 86,
+
+    /// This Arm processor implements the SME LUTv2 instructions (FEAT_SME_LUTv2).
+    ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE = 87,
+
+    /// This Arm processor implements SME FA64 (Full AArch64 instruction set when in Streaming SVE mode) (FEAT_SME_FA64).
+    ARM_SME_FA64_INSTRUCTIONS_AVAILABLE = 88,
+
+    /// This x64 processor implements the UMONITOR instruction.
+    UMONITOR_INSTRUCTION_AVAILABLE = 89,
 };
 
 pub const MAX_WOW64_SHARED_ENTRIES = 16;

package/std/os.zig

@@ -1,4 +1,5 @@
 const builtin = @import("builtin");
+const std = @import("std.zig");
 const native_os = builtin.os.tag;
 
 pub const linux = @import("os/linux.zig");
@@ -8,6 +9,41 @@ pub const wasi = @import("os/wasi.zig");
 pub const emscripten = @import("os/emscripten.zig");
 pub const windows = @import("os/windows.zig");
 
+/// Returns whether the Zig standard library requires libc in order to interface
+/// with the operating system on the given target.
+pub fn targetRequiresLibC(target: *const std.Target) bool {
+    if (target.requiresLibC()) return true;
+    return switch (target.os.tag) {
+        .linux => switch (target.cpu.arch) {
+            // https://codeberg.org/ziglang/zig/issues/30942
+            .csky,
+            // https://codeberg.org/ziglang/zig/issues/30943
+            .hppa,
+            .hppa64,
+            // https://codeberg.org/ziglang/zig/issues/30944
+            .microblaze,
+            .microblazeel,
+            // https://codeberg.org/ziglang/zig/issues/30946
+            .sh,
+            .sheb,
+            // https://codeberg.org/ziglang/zig/issues/30945
+            .sparc,
+            => true,
+            else => false,
+        },
+        .freebsd => true, // https://codeberg.org/ziglang/zig/issues/30981
+        .netbsd => true, // https://codeberg.org/ziglang/zig/issues/30980
+        .openbsd => true, // https://codeberg.org/ziglang/zig/issues/30982
+        else => false,
+    };
+}
+
+/// Returns whether the Zig standard library requires libc in order to interface
+/// with the operating system on the current target.
+pub fn requiresLibC() bool {
+    return targetRequiresLibC(&builtin.target);
+}
+
 test {
     _ = linux;
     if (native_os == .uefi) _ = uefi;

package/std/pie.zig

@@ -22,6 +22,7 @@ const R_RISCV_RELATIVE = 3;
 const R_390_RELATIVE = 12;
 const R_SH_RELATIVE = 165;
 const R_SPARC_RELATIVE = 22;
+const R_XTENSA_RELATIVE = 5;
 
 const R_RELATIVE = switch (builtin.cpu.arch) {
     .x86 => R_386_RELATIVE,
@@ -43,6 +44,7 @@ const R_RELATIVE = switch (builtin.cpu.arch) {
     .s390x => R_390_RELATIVE,
     .sh, .sheb => R_SH_RELATIVE,
     .sparc, .sparc64 => R_SPARC_RELATIVE,
+    .xtensa, .xtensaeb => R_XTENSA_RELATIVE,
     else => @compileError("Missing R_RELATIVE definition for this target"),
 };
 
@@ -261,6 +263,25 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
                 : [ret] "=r" (-> [*]const elf.Dyn),
                 :
                 : .{ .l7 = true }),
+            .xtensa, .xtensaeb => asm volatile (
+                \\ .weak _DYNAMIC
+                \\ .hidden _DYNAMIC
+                // Set things up such that after the `call0`, `a0` will point 1 byte before the
+                // embedded constant. Note that `call0` is a 3-byte instruction, so we need both
+                // `.balign` directives to be safe.
+                \\ .balign 4
+                \\ .begin no-transform
+                \\ call0 1f
+                \\ .end no-transform
+                \\ .balign 4
+                \\ .word _DYNAMIC - .
+                \\1:
+                \\ add a0, a0, 1
+                \\ l32i a8, a0, 0
+                \\ add %[ret], a0, a8
+                : [ret] "=a" (-> [*]const elf.Dyn),
+                :
+                : .{ .a0 = true, .a8 = true }),
             else => {
                 @compileError("PIE startup is not yet supported for this target!");
             },

package/std/posix.zig

@@ -803,7 +803,7 @@ pub fn dl_iterate_phdr(
             }
         }.callbackC, @ptrCast(@constCast(&context)))) {
             0 => return,
-            else => |err| return @as(Error, @errorCast(@errorFromInt(@as(std.meta.Int(.unsigned, @bitSizeOf(anyerror)), @intCast(err))))),
+            else => |err| return @as(Error, @errorCast(@errorFromInt(@as(@Int(.unsigned, @bitSizeOf(anyerror)), @intCast(err))))),
         }
     }
 
@@ -834,7 +834,7 @@ pub fn dl_iterate_phdr(
     while (it.next()) |entry| {
         const phdrs: []elf.ElfN.Phdr = if (entry.addr != 0) phdrs: {
             const ehdr: *elf.ElfN.Ehdr = @ptrFromInt(entry.addr);
-            assert(mem.eql(u8, ehdr.ident[0..4], elf.MAGIC));
+            assert(mem.eql(u8, &ehdr.ident.magic, elf.MAGIC));
             const phdrs: [*]elf.ElfN.Phdr = @ptrFromInt(entry.addr + ehdr.phoff);
             break :phdrs phdrs[0..ehdr.phnum];
         } else getSelfPhdrs();

package/std/process/Environ.zig

@@ -754,7 +754,7 @@ pub fn createPosixBlock(
             },
             .nothing => {},
         };
-        envp[envp_len] = try gpa.dupeZ(u8, mem.span(entry));
+        envp[envp_len] = try gpa.dupeSentinel(u8, mem.span(entry), 0);
         envp_len += 1;
     }
 

package/std/process.zig

@@ -3,6 +3,7 @@ const native_os = builtin.os.tag;
 
 const std = @import("std.zig");
 const Io = std.Io;
+const Dir = std.Io.Dir;
 const File = std.Io.File;
 const fs = std.fs;
 const mem = std.mem;
@@ -85,7 +86,7 @@ pub fn currentPathAlloc(io: Io, allocator: Allocator) CurrentPathAllocError![:0]
         error.NameTooLong => unreachable,
         else => |e| return e,
     };
-    return allocator.dupeZ(u8, buffer[0..n]);
+    return allocator.dupeSentinel(u8, buffer[0..n], 0);
 }
 
 test currentPathAlloc {
@@ -130,7 +131,7 @@ pub fn posixGetUserInfo(io: Io, name: []const u8) !UserInfo {
     return posixGetUserInfoPasswdStream(name, &file_reader.interface) catch |err| switch (err) {
         error.ReadFailed => return file_reader.err.?,
         error.EndOfStream => return error.UserNotFound,
-        error.CorruptPasswordFile => return error.CorruptPasswordFile,
+        error.CorruptPasswordFile => |e| return e,
     };
 }
 
@@ -734,7 +735,7 @@ pub fn executablePathAlloc(io: Io, allocator: Allocator) ExecutablePathAllocErro
         error.NameTooLong => unreachable,
         else => |e| return e,
     };
-    return allocator.dupeZ(u8, buffer[0..n]);
+    return allocator.dupeSentinel(u8, buffer[0..n], 0);
 }
 
 pub const ExecutablePathError = ExecutablePathBaseError || error{NameTooLong};
@@ -784,7 +785,7 @@ pub fn executableDirPathAlloc(io: Io, allocator: Allocator) ExecutablePathAllocE
 
 pub const OpenExecutableError = File.OpenError || ExecutablePathError || File.LockError;
 
-pub fn openExecutable(io: Io, flags: File.OpenFlags) OpenExecutableError!File {
+pub fn openExecutable(io: Io, flags: Dir.OpenFileOptions) OpenExecutableError!File {
     return io.vtable.processExecutableOpen(io.userdata, flags);
 }
 
@@ -845,7 +846,7 @@ pub fn abort() noreturn {
         exit(127); // Pid 1 might not be signalled in some containers.
     }
     switch (native_os) {
-        .uefi, .wasi, .emscripten, .cuda, .amdhsa => @trap(),
+        .uefi, .wasi, .emscripten, .cuda, .amdhsa, .other, .freestanding => @trap(),
         else => posix.system.abort(),
     }
 }

package/std/simd.zig

@@ -157,13 +157,6 @@ pub fn join(a: anytype, b: anytype) @Vector(vectorLength(@TypeOf(a)) + vectorLen
 /// Returns a vector whose elements alternates between those of each input vector.
 /// For example, `interlace(.{[4]u32{11, 12, 13, 14}, [4]u32{21, 22, 23, 24}})` returns a vector containing `.{11, 21, 12, 22, 13, 23, 14, 24}`.
 pub fn interlace(vecs: anytype) @Vector(vectorLength(@TypeOf(vecs[0])) * vecs.len, std.meta.Child(@TypeOf(vecs[0]))) {
-    // interlace doesn't work on MIPS, for some reason.
-    // Notes from earlier debug attempt:
-    //  The indices are correct. The problem seems to be with the @shuffle builtin.
-    //  On MIPS, the test that interlaces small_base gives { 0, 2, 0, 0, 64, 255, 248, 200, 0, 0 }.
-    //  Calling this with two inputs seems to work fine, but I'll let the compile error trigger for all inputs, just to be safe.
-    if (builtin.cpu.arch.isMIPS()) @compileError("TODO: Find out why interlace() doesn't work on MIPS");
-
     const VecType = @TypeOf(vecs[0]);
     const vecs_arr = @as([vecs.len]VecType, vecs);
     const Child = std.meta.Child(@TypeOf(vecs_arr[0]));
@@ -247,13 +240,11 @@ test "vector patterns" {
     try std.testing.expectEqual([8]u32{ 10, 20, 30, 40, 55, 66, 77, 88 }, join(base, other_base));
     try std.testing.expectEqual([2]u32{ 20, 30 }, extract(base, 1, 2));
 
-    if (!builtin.cpu.arch.isMIPS()) {
-        try std.testing.expectEqual([8]u32{ 10, 55, 20, 66, 30, 77, 40, 88 }, interlace(.{ base, other_base }));
+    try std.testing.expectEqual([8]u32{ 10, 55, 20, 66, 30, 77, 40, 88 }, interlace(.{ base, other_base }));
 
-        const small_braid = interlace(small_bases);
-        try std.testing.expectEqual([10]u8{ 0, 2, 4, 6, 8, 1, 3, 5, 7, 9 }, small_braid);
-        try std.testing.expectEqual(small_bases, deinterlace(small_bases.len, small_braid));
-    }
+    const small_braid = interlace(small_bases);
+    try std.testing.expectEqual([10]u8{ 0, 2, 4, 6, 8, 1, 3, 5, 7, 9 }, small_braid);
+    try std.testing.expectEqual(small_bases, deinterlace(small_bases.len, small_braid));
 }
 
 /// Joins two vectors, shifts them leftwards (towards lower indices) and extracts the leftmost elements into a vector the length of a and b.
@@ -384,9 +375,6 @@ pub fn prefixScanWithFunc(
     /// For example, this should be 0 for addition or 1 for multiplication.
     comptime identity: std.meta.Child(@TypeOf(vec)),
 ) if (ErrorType == void) @TypeOf(vec) else ErrorType!@TypeOf(vec) {
-    // I haven't debugged this, but it might be a cousin of sorts to what's going on with interlace.
-    if (builtin.cpu.arch.isMIPS()) @compileError("TODO: Find out why prefixScan doesn't work on MIPS");
-
     const len = vectorLength(@TypeOf(vec));
 
     if (hop == 0) @compileError("hop can not be 0; you'd be going nowhere forever!");
@@ -456,11 +444,6 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a
 }
 
 test "vector prefix scan" {
-    if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
-
-    if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-
     const int_base = @Vector(4, i32){ 11, 23, 9, -21 };
     const float_base = @Vector(4, f32){ 2, 0.5, -10, 6.54321 };
     const bool_base = @Vector(4, bool){ true, false, true, false };

package/std/sort.zig

@@ -749,9 +749,9 @@ test partitionPoint {
 
 /// Returns a tuple of the lower and upper indices in `items` between which all
 /// elements return `.eq` when given to `compareFn`.
-/// - If no element in `items` returns `.eq`, both indices are the
-/// index of the first element in `items` returning `.gt`.
-/// - If no element in `items` returns `.gt`, both indices equal `items.len`.
+/// If no element in `items` returns `.eq`, both indices are the index of the
+/// first element in `items` which returns `.gt`, or if no element returns `.gt`,
+/// both indices are `items.len`.
 ///
 /// `items` must be sorted in ascending order with respect to `compareFn`:
 /// ```

package/std/start.zig

@@ -20,8 +20,13 @@ comptime {
     _ = root;
 
     if (builtin.output_mode == .Lib and builtin.link_mode == .dynamic) {
-        if (native_os == .windows and !@hasDecl(root, "_DllMainCRTStartup")) {
-            @export(&_DllMainCRTStartup, .{ .name = "_DllMainCRTStartup" });
+        const dll_main_crt_startup = if (builtin.abi.isGnu()) "DllMainCRTStartup" else "_DllMainCRTStartup";
+        if (native_os == .windows and !builtin.link_libc and !@hasDecl(root, dll_main_crt_startup)) {
+            @export(&DllMainCRTStartup, .{ .name = dll_main_crt_startup });
+        } else if (native_os == .windows and builtin.link_libc and @hasDecl(root, "DllMain")) {
+            if (!@typeInfo(@TypeOf(root.DllMain)).@"fn".calling_convention.eql(.winapi)) {
+                @export(&DllMain, .{ .name = "DllMain" });
+            }
         }
     } else if (builtin.output_mode == .Exe or @hasDecl(root, "main")) {
         if (builtin.link_libc and @hasDecl(root, "main")) {
@@ -71,7 +76,7 @@ comptime {
     }
 }
 
-fn _DllMainCRTStartup(
+fn DllMainCRTStartup(
     hinstDLL: std.os.windows.HINSTANCE,
     fdwReason: std.os.windows.DWORD,
     lpReserved: std.os.windows.LPVOID,
@@ -81,12 +86,20 @@ fn _DllMainCRTStartup(
     }
 
     if (@hasDecl(root, "DllMain")) {
-        return root.DllMain(hinstDLL, fdwReason, lpReserved);
+        return root.DllMain(@ptrCast(hinstDLL), fdwReason, lpReserved);
     }
 
     return .TRUE;
 }
 
+fn DllMain(
+    hinstDLL: std.os.windows.HINSTANCE,
+    fdwReason: std.os.windows.DWORD,
+    lpReserved: std.os.windows.LPVOID,
+) callconv(.winapi) std.os.windows.BOOL {
+    return root.DllMain(@ptrCast(hinstDLL), fdwReason, lpReserved);
+}
+
 fn wasm_freestanding_start() callconv(.c) void {
     // This is marked inline because for some reason LLVM in
     // release mode fails to inline it, and we want fewer call frames in stack traces.
@@ -156,6 +169,7 @@ fn _start() callconv(.naked) noreturn {
             .kvx => ".cfi_undefined r14",
             .loongarch32, .loongarch64 => ".cfi_undefined 1",
             .m68k => ".cfi_undefined %%pc",
+            .m88k => ".cfi_undefined %%r1",
             .microblaze, .microblazeel => ".cfi_undefined r15",
             .mips, .mipsel, .mips64, .mips64el => ".cfi_undefined $ra",
             .or1k => ".cfi_undefined r9",
@@ -169,6 +183,7 @@ fn _start() callconv(.naked) noreturn {
             .sparc, .sparc64 => ".cfi_undefined %%i7",
             .x86 => ".cfi_undefined %%eip",
             .x86_64 => ".cfi_undefined %%rip",
+            .xtensa, .xtensaeb => "", // No CFI support.
             else => @compileError("unsupported arch"),
         });
 
@@ -318,6 +333,16 @@ fn _start() callconv(.naked) noreturn {
             \\ lea %[posixCallMainAndExit] - . - 8, %%a0
             \\ jsr (%%pc, %%a0)
             ,
+            .m88k =>
+            // r1 = LR, r30 = FP, r31 = SP
+            \\ or %%r0, %%r0, %%r0
+            \\ or %%r0, %%r0, %%r0
+            \\ or %%30, %%r0, %%r0
+            \\ or %%r1, %%r0, %%r0
+            \\ or %%r2, %%r31, %%r0
+            \\ clr %%r31, %%r31, 4<0>
+            \\ br.n %[posixCallMainAndExit]
+            ,
             .microblaze, .microblazeel =>
             // r1 = SP, r15 = LR, r19 = FP, r20 = GP
             \\ ori r15, r0, r0
@@ -462,6 +487,15 @@ fn _start() callconv(.naked) noreturn {
             \\ sub %%sp, 2047, %%sp
             \\ ba,a %[posixCallMainAndExit]
             ,
+            .xtensa, .xtensaeb =>
+            // a0 = LR, a7 = FP, a1 = SP
+            \\ movi a0, 0
+            \\ movi a7, 0
+            \\ mov a2, sp
+            \\ movi a8, -16
+            \\ and sp, sp, a8
+            \\ callx0 %[posixCallMainAndExit]
+            ,
             else => @compileError("unsupported arch"),
         }
         :
@@ -686,12 +720,11 @@ fn mainWithoutEnv(c_argc: c_int, c_argv: [*][*:0]c_char) callconv(.c) c_int {
 /// General error message for a malformed return type
 const bad_main_ret = "expected return type of main to be 'void', '!void', 'noreturn', 'u8', or '!u8'";
 
-const use_debug_allocator = !is_wasm and switch (builtin.mode) {
-    .Debug => true,
-    .ReleaseSafe => !builtin.link_libc, // Not ideal, but the best we have for now.
+const use_safe_allocator = !is_wasm and switch (builtin.mode) {
+    .Debug, .ReleaseSafe => true,
     .ReleaseFast, .ReleaseSmall => !builtin.link_libc and builtin.single_threaded, // Also not ideal.
 };
-var debug_allocator: std.heap.DebugAllocator(.{}) = .init;
+var safe_allocator: std.heap.SafeAllocator = .init(std.heap.page_allocator, .{});
 
 inline fn callMain(args: std.process.Args.Vector, environ: std.process.Environ.Block) u8 {
     const fn_info = @typeInfo(@TypeOf(root.main)).@"fn";
@@ -701,8 +734,8 @@ inline fn callMain(args: std.process.Args.Vector, environ: std.process.Environ.B
         .environ = .{ .block = environ },
     }));
 
-    const gpa = if (use_debug_allocator)
-        debug_allocator.allocator()
+    const gpa = if (use_safe_allocator)
+        safe_allocator.allocator()
     else if (builtin.link_libc)
         std.heap.c_allocator
     else if (is_wasm)
@@ -712,8 +745,8 @@ inline fn callMain(args: std.process.Args.Vector, environ: std.process.Environ.B
     else
         comptime unreachable;
 
-    defer if (use_debug_allocator) {
-        _ = debug_allocator.deinit(); // Leaks do not affect return code.
+    defer if (use_safe_allocator) {
+        _ = safe_allocator.deinit(); // Leaks do not affect return code.
     };
 
     const arena_backing_allocator = if (is_wasm) gpa else std.heap.page_allocator;

package/std/std.zig

@@ -9,7 +9,9 @@ pub const StaticStringMapWithEql = static_string_map.StaticStringMapWithEql;
 pub const Deque = @import("deque.zig").Deque;
 pub const DoublyLinkedList = @import("DoublyLinkedList.zig");
 pub const DynLib = @import("dynamic_library.zig").DynLib;
+/// Deprecated: use `bit_set.DynamicManaged`.
 pub const DynamicBitSet = bit_set.DynamicBitSet;
+/// Deprecated: use `bit_set.Dynamic`.
 pub const DynamicBitSetUnmanaged = bit_set.DynamicBitSetUnmanaged;
 pub const EnumArray = enums.EnumArray;
 pub const EnumMap = enums.EnumMap;
@@ -24,6 +26,7 @@ pub const Progress = @import("Progress.zig");
 pub const Random = @import("Random.zig");
 pub const SemanticVersion = @import("SemanticVersion.zig");
 pub const SinglyLinkedList = @import("SinglyLinkedList.zig");
+/// Deprecated: use `bit_set.Static`.
 pub const StaticBitSet = bit_set.StaticBitSet;
 pub const StringHashMap = hash_map.StringHashMap;
 pub const StringHashMapUnmanaged = hash_map.StringHashMapUnmanaged;
@@ -62,7 +65,11 @@ pub const array_hash_map = @import("array_hash_map.zig");
 pub const atomic = @import("atomic.zig");
 pub const base64 = @import("base64.zig");
 pub const bit_set = @import("bit_set.zig");
-pub const builtin = @import("builtin.zig");
+/// Deprecated; use `lang`.
+///
+/// To be removed after Zig 0.17.0.
+pub const builtin = lang;
+pub const lang = @import("lang.zig");
 pub const c = @import("c.zig");
 pub const coff = @import("coff.zig");
 pub const compress = @import("compress.zig");