@tscircuit/schematic-trace-solver 0.0.121 → 0.0.123

package/tests/repros/assets/repro161-power-section-autolayout.input.json

@@ -0,0 +1,578 @@
+{
+  "chips": [
+    {
+      "chipId": "schematic_component_0",
+      "center": {
+        "x": 0,
+        "y": 0
+      },
+      "width": 2.5,
+      "height": 4,
+      "pins": [
+        {
+          "pinId": "schematic_port_0",
+          "x": 1.25,
+          "y": 1.4000000000000001
+        },
+        {
+          "pinId": "schematic_port_1",
+          "x": 1.25,
+          "y": 1.2
+        },
+        {
+          "pinId": "schematic_port_2",
+          "x": 1.25,
+          "y": 0.8499999999999999
+        },
+        {
+          "pinId": "schematic_port_3",
+          "x": 1.25,
+          "y": 0.6499999999999997
+        },
+        {
+          "pinId": "schematic_port_4",
+          "x": 1.25,
+          "y": 0.2999999999999998
+        },
+        {
+          "pinId": "schematic_port_5",
+          "x": 1.25,
+          "y": 0.09999999999999987
+        },
+        {
+          "pinId": "schematic_port_6",
+          "x": 1.25,
+          "y": -0.10000000000000009
+        },
+        {
+          "pinId": "schematic_port_7",
+          "x": 1.25,
+          "y": -0.30000000000000004
+        },
+        {
+          "pinId": "schematic_port_8",
+          "x": 1.25,
+          "y": -0.6500000000000001
+        },
+        {
+          "pinId": "schematic_port_9",
+          "x": 1.25,
+          "y": -0.8500000000000001
+        },
+        {
+          "pinId": "schematic_port_10",
+          "x": 1.25,
+          "y": -1.2000000000000002
+        },
+        {
+          "pinId": "schematic_port_11",
+          "x": 1.25,
+          "y": -1.4000000000000001
+        },
+        {
+          "pinId": "schematic_port_12",
+          "x": -0.37500000000000006,
+          "y": -2
+        },
+        {
+          "pinId": "schematic_port_13",
+          "x": -0.17500000000000004,
+          "y": -2
+        },
+        {
+          "pinId": "schematic_port_14",
+          "x": 0.024999999999999967,
+          "y": -2
+        },
+        {
+          "pinId": "schematic_port_15",
+          "x": 0.22500000000000003,
+          "y": -2
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_1",
+      "center": {
+        "x": 5.0249999999999995,
+        "y": -0.7950000000000014
+      },
+      "width": 1.040000000000001,
+      "height": 0.6799999999999999,
+      "pins": [
+        {
+          "pinId": "schematic_port_16",
+          "x": 4.504999999999999,
+          "y": -0.8650000000000013,
+          "_facingDirection": "x-"
+        },
+        {
+          "pinId": "schematic_port_17",
+          "x": 5.545,
+          "y": -0.8650000000000013,
+          "_facingDirection": "x+"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_2",
+      "center": {
+        "x": 2.88,
+        "y": -0.6500000000000015
+      },
+      "width": 0.8399999999999999,
+      "height": 1.1000000000000003,
+      "pins": [
+        {
+          "pinId": "schematic_port_18",
+          "x": 3.1799999999999997,
+          "y": -0.10000000000000131
+        },
+        {
+          "pinId": "schematic_port_19",
+          "x": 3.19,
+          "y": -1.2000000000000015
+        },
+        {
+          "pinId": "schematic_port_20",
+          "x": 2.46,
+          "y": -0.7500000000000013
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_3",
+      "center": {
+        "x": 3.0125,
+        "y": 1.4099999999999986
+      },
+      "width": 1.0850000000000004,
+      "height": 0.6000000000000001,
+      "pins": [
+        {
+          "pinId": "schematic_port_21",
+          "x": 2.795,
+          "y": 1.7099999999999986,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_22",
+          "x": 2.795,
+          "y": 1.1099999999999985,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_4",
+      "center": {
+        "x": 2.65,
+        "y": -3.2050000000000014
+      },
+      "width": 2,
+      "height": 0.7999999999999998,
+      "pins": [
+        {
+          "pinId": "schematic_port_23",
+          "x": 1.65,
+          "y": -3.0050000000000012
+        },
+        {
+          "pinId": "schematic_port_24",
+          "x": 1.65,
+          "y": -3.2050000000000014
+        },
+        {
+          "pinId": "schematic_port_25",
+          "x": 1.65,
+          "y": -3.4050000000000016
+        },
+        {
+          "pinId": "schematic_port_26",
+          "x": 3.65,
+          "y": -3.3050000000000015
+        },
+        {
+          "pinId": "schematic_port_27",
+          "x": 3.65,
+          "y": -3.1050000000000013
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_5",
+      "center": {
+        "x": 5.055,
+        "y": 0.9799999999999988
+      },
+      "width": 0.9200000000000008,
+      "height": 0.76,
+      "pins": [
+        {
+          "pinId": "schematic_port_28",
+          "x": 4.92,
+          "y": 1.3599999999999988,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_29",
+          "x": 4.92,
+          "y": 0.5999999999999988,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_6",
+      "center": {
+        "x": 4.914999999999999,
+        "y": -3.8050000000000015
+      },
+      "width": 1.04,
+      "height": 0.7600000000000011,
+      "pins": [
+        {
+          "pinId": "schematic_port_30",
+          "x": 4.72,
+          "y": -3.4250000000000007,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_31",
+          "x": 4.72,
+          "y": -4.185000000000002,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_7",
+      "center": {
+        "x": 6.464999999999999,
+        "y": -3.8050000000000015
+      },
+      "width": 1.4499999999999993,
+      "height": 0.7799999999999994,
+      "pins": [
+        {
+          "pinId": "schematic_port_32",
+          "x": 6.289999999999999,
+          "y": -4.195000000000001,
+          "_facingDirection": "y-"
+        },
+        {
+          "pinId": "schematic_port_33",
+          "x": 6.289999999999999,
+          "y": -3.415000000000002,
+          "_facingDirection": "y+"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_8",
+      "center": {
+        "x": 7.794999999999999,
+        "y": -3.8050000000000015
+      },
+      "width": 0.9199999999999999,
+      "height": 0.7600000000000011,
+      "pins": [
+        {
+          "pinId": "schematic_port_34",
+          "x": 7.659999999999999,
+          "y": -3.4250000000000007,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_35",
+          "x": 7.659999999999999,
+          "y": -4.185000000000002,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_9",
+      "center": {
+        "x": 9.8025,
+        "y": -5.3450000000000015
+      },
+      "width": 1.0150000000000006,
+      "height": 1.1300000000000008,
+      "pins": [
+        {
+          "pinId": "schematic_port_36",
+          "x": 9.62,
+          "y": -5.910000000000002,
+          "_facingDirection": "y-"
+        },
+        {
+          "pinId": "schematic_port_37",
+          "x": 9.62,
+          "y": -4.780000000000001,
+          "_facingDirection": "y+"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_10",
+      "center": {
+        "x": 9.7775,
+        "y": -3.8050000000000015
+      },
+      "width": 0.9649999999999999,
+      "height": 0.6000000000000014,
+      "pins": [
+        {
+          "pinId": "schematic_port_38",
+          "x": 9.62,
+          "y": -4.105000000000002
+        },
+        {
+          "pinId": "schematic_port_39",
+          "x": 9.62,
+          "y": -3.505000000000001
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_11",
+      "center": {
+        "x": 0.19500000000000028,
+        "y": -7.1949999999999985
+      },
+      "width": 0.5,
+      "height": 0.7599999999999998,
+      "pins": [
+        {
+          "pinId": "schematic_port_40",
+          "x": 0.19500000000000026,
+          "y": -7.574999999999998,
+          "_facingDirection": "y-"
+        },
+        {
+          "pinId": "schematic_port_41",
+          "x": 0.1950000000000003,
+          "y": -6.814999999999999,
+          "_facingDirection": "y+"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    },
+    {
+      "chipId": "schematic_component_12",
+      "center": {
+        "x": 4.8925,
+        "y": 2.7899999999999983
+      },
+      "width": 1.085,
+      "height": 0.5999999999999996,
+      "pins": [
+        {
+          "pinId": "schematic_port_42",
+          "x": 4.675,
+          "y": 3.089999999999998,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_43",
+          "x": 4.675,
+          "y": 2.4899999999999984,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "Power Input & 3V3 Regulator"
+    }
+  ],
+  "directConnections": [
+    {
+      "netId": ".U3 > .BYP to .C2 > .pin1",
+      "pinIds": [
+        "schematic_port_26",
+        "schematic_port_30"
+      ]
+    },
+    {
+      "netId": ".R1 > .pin1 to .LED1 > .cathode",
+      "pinIds": [
+        "schematic_port_38",
+        "schematic_port_37"
+      ]
+    }
+  ],
+  "netConnections": [
+    {
+      "netId": "V5",
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.36,
+      "pinIds": [
+        "schematic_port_0",
+        "schematic_port_1",
+        "schematic_port_17",
+        "schematic_port_20",
+        "schematic_port_21"
+      ]
+    },
+    {
+      "netId": "DP",
+      "netLabelWidth": 0.36,
+      "pinIds": [
+        "schematic_port_4",
+        "schematic_port_5"
+      ]
+    },
+    {
+      "netId": "DM",
+      "netLabelWidth": 0.36,
+      "pinIds": [
+        "schematic_port_6",
+        "schematic_port_7"
+      ]
+    },
+    {
+      "netId": "GND",
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.48,
+      "pinIds": [
+        "schematic_port_10",
+        "schematic_port_11",
+        "schematic_port_12",
+        "schematic_port_13",
+        "schematic_port_14",
+        "schematic_port_15",
+        "schematic_port_22",
+        "schematic_port_24",
+        "schematic_port_29",
+        "schematic_port_31",
+        "schematic_port_32",
+        "schematic_port_35",
+        "schematic_port_36",
+        "schematic_port_40"
+      ]
+    },
+    {
+      "netId": "VBUS",
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.6,
+      "pinIds": [
+        "schematic_port_16",
+        "schematic_port_19",
+        "schematic_port_23",
+        "schematic_port_28",
+        "schematic_port_42"
+      ]
+    },
+    {
+      "netId": "BATT",
+      "netLabelWidth": 0.6,
+      "pinIds": [
+        "schematic_port_18"
+      ]
+    },
+    {
+      "netId": "LDO_EN",
+      "netLabelWidth": 0.84,
+      "pinIds": [
+        "schematic_port_25",
+        "schematic_port_41"
+      ]
+    },
+    {
+      "netId": "V3V3",
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.6,
+      "pinIds": [
+        "schematic_port_27",
+        "schematic_port_33",
+        "schematic_port_34",
+        "schematic_port_39"
+      ]
+    },
+    {
+      "netId": "LDO_H",
+      "netLabelWidth": 0.72,
+      "pinIds": [
+        "schematic_port_43"
+      ]
+    }
+  ],
+  "textBoxes": [
+    {
+      "chipId": "schematic_component_0",
+      "center": {
+        "x": 1.07,
+        "y": 1.7149999999999999
+      },
+      "width": 0.3599999999999999,
+      "height": 0.24999999999999978,
+      "text": "J1"
+    },
+    {
+      "chipId": "schematic_component_4",
+      "center": {
+        "x": 3.07,
+        "y": -3.735000000000001
+      },
+      "width": 2.04,
+      "height": 0.17999999999999972,
+      "text": "MIC5219_3_3YM5_TR"
+    },
+    {
+      "chipId": "schematic_component_4",
+      "center": {
+        "x": 2.17,
+        "y": -2.6900000000000013
+      },
+      "width": 0.3600000000000003,
+      "height": 0.24999999999999956,
+      "text": "U3"
+    }
+  ],
+  "availableNetLabelOrientations": {
+    "V5": [
+      "y+"
+    ],
+    "GND": [
+      "y-"
+    ],
+    "DP": [
+      "x-",
+      "x+"
+    ],
+    "DM": [
+      "x-",
+      "x+"
+    ],
+    "VBUS": [
+      "y+"
+    ],
+    "BATT": [
+      "x-",
+      "x+"
+    ],
+    "LDO_EN": [
+      "x-",
+      "x+"
+    ],
+    "V3V3": [
+      "y+"
+    ],
+    "LDO_H": [
+      "x-",
+      "x+"
+    ]
+  },
+  "maxMspPairDistance": 8,
+  "_hideRatsNet": false
+}

package/tests/repros/repro-bq25895-cross-net-trace-overlap.test.ts

@@ -1,6 +1,7 @@
 import { expect, test } from "bun:test"
 import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
 import type { SolvedTracePath } from "lib/solvers/SchematicTraceLinesSolver/SchematicTraceLinesSolver"
+import { getTraceCorners } from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
 import { SCHEMATIC_TRACE_MIN_VISUAL_CENTERLINE_CLEARANCE } from "lib/utils/doesPathCoincideWithTraces"
 import "tests/fixtures/matcher"
 import inputProblem from "./assets/repro-bq25895-cross-net-trace-overlap.input.json"
@@ -71,5 +72,17 @@ test("BQ25895 CE and GND traces keep visible parallel clearance", () => {
   )
 
   expect(hasInsufficientCeAndGroundClearance).toBe(false)
+
+  const output = solver.netLabelTraceCollisionSolver!.getOutput()
+  const groundLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "GND",
+  )!
+  const groundLabelTrace = output.traces.find((trace) =>
+    groundLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+
+  expect(getTraceCorners(groundLabelTrace.tracePath)).toContainEqual(
+    groundLabel.anchorPoint,
+  )
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-missing-trace-netlabel.test.ts

@@ -1,4 +1,5 @@
 import { expect, test } from "bun:test"
+import { getTraceCorners } from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
 import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
 import inputProblem from "./assets/repro-missing-trace-netlabel.input.json"
 import "tests/fixtures/matcher"
@@ -10,5 +11,16 @@ test("repro148 missing trace becomes net labels", () => {
 
   solver.solve()
 
+  const output = solver.sameNetJunctionAlignmentSolver!.getOutput()
+  const powerLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "V3V3",
+  )!
+  const powerTrace = output.traces.find((trace) =>
+    powerLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+
+  expect(getTraceCorners(powerTrace.tracePath)).toContainEqual(
+    powerLabel.anchorPoint,
+  )
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-netlabel-overlap-trace.test.ts

@@ -1,4 +1,10 @@
 import { expect, test } from "bun:test"
+import { traceCrossesBoundsInterior } from "lib/solvers/AvailableNetOrientationSolver/geometry"
+import {
+  getTraceCorners,
+  rectsOverlap,
+} from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
+import { getRectBounds } from "lib/solvers/NetLabelPlacementSolver/SingleNetLabelPlacementSolver/geometry"
 import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
 import inputProblem from "./assets/repro-netlabel-overlap-trace.input.json"
 import "tests/fixtures/matcher"
@@ -10,5 +16,37 @@ test("repro147 netlabel overlaps trace", () => {
 
   solver.solve()
 
+  const output = solver.sameNetJunctionAlignmentSolver!.getOutput()
+  const groundLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "GND",
+  )!
+  const groundTrace = output.traces.find((trace) =>
+    groundLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+  const groundLabelBounds = getRectBounds(
+    groundLabel.center,
+    groundLabel.width,
+    groundLabel.height,
+  )
+
+  expect(getTraceCorners(groundTrace.tracePath)).toContainEqual(
+    groundLabel.anchorPoint,
+  )
+  expect(
+    inputProblem.chips.some((chip) =>
+      rectsOverlap(
+        groundLabelBounds,
+        getRectBounds(chip.center, chip.width, chip.height),
+      ),
+    ),
+  ).toBe(false)
+  expect(
+    traceCrossesBoundsInterior(
+      groundLabelBounds,
+      Object.fromEntries(
+        output.traces.map((trace) => [trace.mspPairId, trace]),
+      ),
+    ),
+  ).toBe(false)
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-nrf52810-clock-routing.test.ts

@@ -0,0 +1,28 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import "tests/fixtures/matcher"
+import inputProblem from "./assets/repro-nrf52810-clock-routing.input.json"
+
+// Extracted from the nRF52810 clock-source schematic shown in the reproduction:
+// a four-pin 32 MHz crystal and a two-pin 32.768 kHz crystal, each connected
+// to an MCU schematic box, two load capacitors, and section-local GND labels.
+test("repro nRF52810 HF and LF crystal trace/net-label routing", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+
+  solver.solve()
+
+  expect(solver.mspConnectionPairSolver?.mspConnectionPairs).toHaveLength(11)
+  expect(
+    solver.schematicTraceLinesSolver?.failedConnectionPairs.map(
+      (pair) => pair.mspPairId,
+    ),
+  ).toEqual([
+    "schematic_port_39-schematic_port_43", // U1.XC2 -> X1.XTAL2
+    "schematic_port_45-schematic_port_47", // U1.XL2 -> X2.OSC2
+    "schematic_port_41-schematic_port_40", // X1.GND2 -> X1.GND1
+  ])
+  expect(
+    solver.sameNetJunctionAlignmentSolver?.getOutput().netLabelPlacements,
+  ).toHaveLength(10)
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})