@tachikomagundam/abathur 0.2.7 → 0.2.8

package/graders/pcb-agent/run-scenario.sh

@@ -0,0 +1,94 @@
+#!/usr/bin/env bash
+# run-scenario.sh (pcb-agent) — spawn the PCB TEAM headless on the scenario brief.
+# The seat writes ZERO board artifacts here: this script only (1) seeds an isolated
+# arena, (2) launches the internal-control orchestrator profile (isolated HOME/DB per
+# L-isolation) with the brief, (3) records the transcript. All engineering is done by
+# the team's own agents. Transcript = the evidence the grader reads.
+#
+# Contract mirrors historian: argv = <unitId> <scenario-file> [repoRoot]; last stdout
+# line = {"tokensEst":N,"turns":M} for parseRunMeta; ABATHUR_TRANSCRIPT honored.
+set -euo pipefail
+unit_id="${1:?usage: run-scenario.sh <unitId> <scenario-file> [repoRoot]}"
+scenario_file="${2:?scenario file}"
+repo_root="${3:-$(dirname "$(dirname "$scenario_file")")}"
+HERE="$(cd "$(dirname "$0")" && pwd)"
+CONTROL=/home/lab/workspace/pcb-control
+ARENA_ROOT="${PCB_BENCH_ARENA:-/tmp/opencode/pcb-bench}"
+ARENA="$ARENA_ROOT/$unit_id"
+TRANSCRIPT="${ABATHUR_TRANSCRIPT:-$ARENA_ROOT/$unit_id.transcript.jsonl}"
+mkdir -p "$ARENA_ROOT"
+
+bash "$HERE/seed-sandbox.sh" "$ARENA" "$HERE/seed"
+
+# Brief = the scenario file (whole thing; it is the task card, no solutions inside).
+BRIEF="$(cat "$scenario_file")"
+# run cards (S4 seam, historian precedent): candidate mutations ride to the team verbatim.
+rc=""
+if [ -d "$repo_root/abathur-notes" ]; then
+  for n in "$repo_root"/abathur-notes/*.md; do [ -e "$n" ] || continue
+    rc="$rc
+## Run card
+$(cat "$n")"; done
+fi
+
+cd "$ARENA"
+# per-unit isolated HOME/DB (never the human main DB; L-isolation law), seeded
+# from the PROVISIONED internal home's provider config (local-qwen baseURL etc).
+UHOME="$ARENA_ROOT/$unit_id.home"; rm -rf "$UHOME"; mkdir -p "$UHOME/.config" "$UHOME/.local/share/opencode"
+cp -r /home/lab/workspace/pcb-control/internal-home/.config/opencode "$UHOME/.config/" 2>/dev/null || true
+rm -rf "$UHOME/.config/opencode/node_modules" "$UHOME/.local/share/opencode/opencode.db" 2>/dev/null || true
+DB="$UHOME/.local/share/opencode/opencode.db"
+
+# THE TEAM IS THE SUBJECT: mount the PCB role tree into the arena cwd so
+# `--agent pcb-orchestrator` resolves. Role provenance is the genome seam:
+# if the candidate tree carries agents/*.md (a mutation to the team itself),
+# those files WIN over the canonical internal-control copies.
+mkdir -p "$ARENA/.opencode/agents"
+cp /home/lab/workspace/pcb-control/internal-control/.opencode/agents/*.md "$ARENA/.opencode/agents/"
+if [ -d "$repo_root/agents" ] && ls "$repo_root"/agents/*.md >/dev/null 2>&1; then
+  cp -f "$repo_root"/agents/*.md "$ARENA/.opencode/agents/"
+  echo "role-provenance: candidate-tree agents override canonical" >&2
+fi
+
+RUNENV=(env -i PATH="$PATH" LANG=C.UTF-8 TERM=xterm-256color HOME="$UHOME"
+  XDG_DATA_HOME="$UHOME/.local/share" XDG_CACHE_HOME="$UHOME/.cache" XDG_STATE_HOME="$UHOME/.local/state"
+  OPENCODE_DB="$DB" KICAD_SHARE_DIR=/home/lab/.local/AppDir/share/kicad)
+
+# FAIL-CLOSED SELF-PROOF GATE: the named agent must actually resolve BEFORE we
+# spend a rep. "agent not found. Falling back to default" voids the rep — that
+# is precisely the channel-dead noise theater the lane forbids.
+"${RUNENV[@]}" opencode agent list >"$ARENA/.agent-list.txt" 2>&1
+grep -q "pcb-orchestrator" "$ARENA/.agent-list.txt" || {
+  echo "RUNNER_GATE_FAIL: pcb-orchestrator not in resolved agent inventory" >&2
+  tail -5 "$ARENA/.agent-list.txt" >&2
+  exit 1
+}
+
+timeout "${PCB_RUN_TIMEOUT:-2400}" "${RUNENV[@]}" \
+  opencode run --agent pcb-orchestrator --format json \
+  --dir "$ARENA" -- "$BRIEF$rc" > "$TRANSCRIPT" 2>"$ARENA/.run-stderr" || true
+
+if [ ! -s "$TRANSCRIPT" ]; then
+  echo "RUNNER_INFRA_FAIL: empty transcript (see $ARENA/.run-stderr)" >&2
+  exit 1
+fi
+# mechanical role attribution proof: the bench session in the isolated DB MUST
+# be owned by pcb-orchestrator (transcript lines carry no agent field; the DB
+# session table does). No proof = void rep, never a scored fallback run.
+ROLE_OK="$(sqlite3 "$DB" "SELECT COUNT(*) FROM session WHERE agent='pcb-orchestrator';" 2>/dev/null || echo 0)"
+[ "${ROLE_OK:-0}" -ge 1 ] || { echo "RUNNER_INFRA_FAIL: no pcb-orchestrator session in $DB (fallback-agent run would be noise theater)" >&2; exit 1; }
+
+turns=$(grep -c '"type":"text"' "$TRANSCRIPT" 2>/dev/null || true); turns="${turns:-0}"
+tokens=$(python3 - "$TRANSCRIPT" <<'EOF' 2>/dev/null | tail -1 || true
+import json,sys
+n=0
+for l in open(sys.argv[1]):
+    try: d=json.loads(l)
+    except Exception: continue
+    p=d.get("part",{})
+    if p.get("type")=="text": n+=len(p.get("text",""))
+print(n//4)
+EOF
+); tokens="${tokens:-0}"
+echo "arena=$ARENA" > "$ARENA_ROOT/$unit_id.arena"
+python3 -c "import json,re;t=int(re.sub(r'[^0-9]','',str('$tokens')) or 0);u=int(re.sub(r'[^0-9]','',str('$turns')) or 0);print(json.dumps({'tokensEst':t,'turns':u}))"

package/graders/pcb-agent/seed/esp32s3-r12-BRIEF.txt

@@ -0,0 +1,51 @@
+# MODULE BRIEF -- esp32s3-r12 (fixture-tier mini-board)
+
+Mission dir: fixtures/board-lab/esp32s3-r12/ (root: /home/lab/workspace/pcb-control/fixtures)
+Binding plan: 2ee2cfb309bea8552dd294db3eb087d74950f0e82e0e11524a142c9f8f217f4a / dispatch pcb-dispatch-r12a-plan1
+
+## 0. Purpose
+Six-module ESP32-S3 breakout: USB-C 5V in -> ME6211 3.3V LDO -> module power/decoupling, one status LED, one 1x4 debug header with UART. Fixtures only; never the real board.
+
+## 1. Netlist (exactly 6 nets)
+- +3V3  : U1.3V3, U2.VOUT, C1.1, C2.1, C3.1, D1.anode, H1.1   (L10: single merged name, no variants)
+- +5V_IN: J1.VBUS, U2.VIN
+- GND   : J1.GND, U2.GND, C1.2, C2.2, C3.2, R1.2? NO -> R1.2 is +3V3 per LED string below.
+  Correction -- GND: J1.GND, U2.GND, C1.2, C2.2, C3.2, D1... see M5 for string orientation.
+- GPIO2 : U1.GPIO2, R1.2
+- GPIO4 : U1.GPIO4, H1.2 (label "TX" = board->host)
+- GPIO5 : U1.GPIO5, H1.3 (label "RX" = host->board)
+Final GND set: J1.GND, U2.GND, C1.2, C2.2, C3.2, H1.4.
+All other U1 pins NC; flash/PSRAM GPIO26-32 MUST remain unconnected. U1.EN tied directly to +3V3 (hard-enable; accepted fixture deviation, flagged for DFM review).
+
+## 2. Modules (6 max -- no extra refs permitted)
+- M1 U1 ESP32-S3-WROOM-1 (module). Power pads 3V3/GND per library footprint; IO used: EN, GPIO2, GPIO4 (UART TX), GPIO5 (UART RX).
+- M2 J1 USB-C receptacle, power-only. Connect VBUS(A4/A9/B4/B5 bussed)->+5V_IN and GND only. CC1/CC2 left NC -- fixture is bench/charger-fed; no PD negotiation. Deviation noted for reviewer.
+- M3 U2 ME6211C33 LDO (SOT-23-3 class). Function pins VIN->+5V_IN, GND->GND, VOUT->+3V3. Pad-number resolution against the project library symbol is the schematic agent's job, verified by gate.
+- M4 Decoupling: C1,C2 100nF 0402 across +3V3/GND placed at U1 3V3 pad(s); C3 10uF 0603 across +3V3/GND at U2 VOUT. ME6211 input cap omitted (fixture simplification, flagged).
+- M5 Status: +3V3 -> D1 anode, D1 cathode -> R1 (1k) -> GPIO2 (sink-driven, active-low lit). GPIO2 is not an S3 strapping pin (straps are 0/3/45/46): safe.
+- M6 H1 1x4 header, 2.54mm pitch: pin1 +3V3, pin2 GPIO4/TX, pin3 GPIO5/RX, pin4 GND.
+
+## 3. Explicit rules -- binding on brief AND every downstream artifact
+- L10 ONE merged power net named +3V3 for every 3.3V pad. Forbidden: +3V3A, 3V3_D, VDD_3V3, duplicate 3.3V names. Net-name scan of sch+pcb must find exactly "+3V3".
+- L11 Every footprint pad pitch AND courtyard gap >= 0.25mm (class clearance 0.2mm + 0.05 margin). 0402 pads 1.0x0.5mm, rot-aware: clearance check applies after per-ref rotation. U1 side pads on >=1.5mm vertical grid rows.
+- L16 Netlist uses KiCad schematic global-label grammar: every connection is a wire terminating in a label whose text equals the net name, placed at each pin. No hierarchical/local-only labels, no net-naming-by-wire.
+- L1 pos.csv refs == bom.csv refs exactly (same set, same strings): {U1,U2,J1,H1,C1,C2,C3,D1,R1} -- 10 refs, no suffix drift, no extra/missing.
+- Placement grid: 0.5mm snap for all component origins.
+
+## 4. Artifact contract (mission dir)
+- esp32s3-r12.kicad_sch -- 10 symbols, nets per section 1, grammar per L16.
+- esp32s3-r12.kicad_pcb -- footprints from project lib; courtyard clearances per L11; board outline suggestion <= 55x35mm (target, non-binding).
+- bom.csv / pos.csv -- per L1; pos.csv includes rotation column (feeds L11 rot-aware check).
+- reports/ -- gate evidence JSON from tools/gate_runner.py.
+
+## 5. Acceptance gates (deterministic, tools/gate_runner.py evidence only)
+- g-net: parsed sch netlist == section 1 set exactly; net count == 6.
+- g-l10: regex scan for 3.3V-name variants in sch+pcb yields zero hits outside "+3V3".
+- g-l11: pad-pitch/courtyard matrix min gap >= 0.25mm; 0402 pad geom 1.0x0.5 present; U1 side-pad row pitch >= 1.5mm.
+- g-l16: every net pin has wire+label; zero label-less pin wires.
+- g-pos: set(bom.refs) == set(pos.refs), len == 10.
+- g-grid: all placement origins on 0.5mm grid.
+Fail on any gate -> revert to last checkpoint; 3 design-fails on same gate -> ESCALATE with options menu.
+
+## 6. Out of scope
+Antenna keepout tuning, ESD parts, USB data lines, battery/charge, strapping-button circuits, any board outside fixtures/.

package/graders/pcb-agent/seed/spec.json

@@ -0,0 +1,129 @@
+{
+ "schema_version": "1.0",
+ "board": {
+  "name": "toy-m2",
+  "_provenance": "TOY-FIXTURE netlist from esp32s3-r12-BRIEF.txt + architect corrections (7 nets/9 refs). U1 pin-pad function mapping = FIXTURE CONVENTION (toy GPIOs on pads 4/5/9), NOT silicon pinout \u2014 HUMAN VERIFICATION REQUIRED before any real-order use. | C1/C2 0603 deviation per pad-corridor DRC class",
+  "project": "board-lab toy M2 full-cycle"
+ },
+ "components": [
+  {
+   "ref": "U1",
+   "mpn": "ESP32-S3-WROOM-1-N8R8",
+   "footprint": "RF_Module:ESP32-S3-WROOM-1",
+   "pins": {
+    "1": "GND",
+    "2": "+3V3",
+    "3": "+3V3",
+    "4": "GPIO4",
+    "5": "GPIO5",
+    "9": "GPIO2",
+    "21": "GND",
+    "6": "NC(pin unused)",
+    "7": "NC(pin unused)",
+    "8": "NC(pin unused)",
+    "10": "NC(pin unused)",
+    "11": "NC(pin unused)",
+    "12": "NC(pin unused)",
+    "13": "NC(pin unused)",
+    "14": "NC(pin unused)",
+    "15": "NC(pin unused)",
+    "16": "NC(pin unused)",
+    "17": "NC(pin unused)",
+    "18": "NC(pin unused)",
+    "19": "NC(pin unused)",
+    "20": "NC(pin unused)"
+   }
+  },
+  {
+   "ref": "U2",
+   "mpn": "ME6211C33",
+   "footprint": "Package_TO_SOT_SMD:SOT-23",
+   "pins": {
+    "1": "+5V_IN",
+    "2": "GND",
+    "3": "+3V3"
+   }
+  },
+  {
+   "ref": "J1",
+   "mpn": "USB4110",
+   "footprint": "Connector_USB:USB_C_Receptacle_GCT_USB4110",
+   "pins": {
+    "1": "GND",
+    "2": "NC(pin unused)",
+    "3": "NC(pin unused)",
+    "4": "+5V_IN",
+    "5": "NC(pin unused)",
+    "6": "+5V_IN",
+    "7": "NC(pin unused)",
+    "8": "GND",
+    "9": "GND",
+    "10": "NC(pin unused)",
+    "11": "NC(pin unused)",
+    "12": "NC(pin unused)",
+    "13": "NC(pin unused)",
+    "14": "NC(pin unused)",
+    "15": "NC(pin unused)",
+    "16": "GND"
+   }
+  },
+  {
+   "ref": "H1",
+   "mpn": "HDR1x4",
+   "footprint": "Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical",
+   "pins": {
+    "1": "+3V3",
+    "2": "GPIO4",
+    "3": "GPIO5",
+    "4": "GND"
+   }
+  },
+  {
+   "ref": "C1",
+   "mpn": "100nF",
+   "footprint": "Capacitor_SMD:C_0603_1608Metric",
+   "pins": {
+    "1": "+3V3",
+    "2": "GND"
+   },
+   "_dev": "0402->0603: pad-pair corridor (0.36mm) admits no 0.2mm track w/ 0.2 clr; fixture deviation logged"
+  },
+  {
+   "ref": "C2",
+   "mpn": "100nF",
+   "footprint": "Capacitor_SMD:C_0603_1608Metric",
+   "pins": {
+    "1": "+3V3",
+    "2": "GND"
+   },
+   "_dev": "0402->0603: pad-pair corridor (0.36mm) admits no 0.2mm track w/ 0.2 clr; fixture deviation logged"
+  },
+  {
+   "ref": "C3",
+   "mpn": "10uF",
+   "footprint": "Capacitor_SMD:C_0603_1608Metric",
+   "pins": {
+    "1": "+3V3",
+    "2": "GND"
+   }
+  },
+  {
+   "ref": "D1",
+   "mpn": "LED",
+   "footprint": "LED_SMD:LED_0603_1608Metric",
+   "pins": {
+    "1": "+3V3",
+    "2": "LED1"
+   }
+  },
+  {
+   "ref": "R1",
+   "mpn": "1k",
+   "footprint": "Resistor_SMD:R_0603_1608Metric",
+   "pins": {
+    "1": "LED1",
+    "2": "GPIO2"
+   }
+  }
+ ]
+}

package/graders/pcb-agent/seed/tools/board_author_pcb.py

@@ -0,0 +1,237 @@
+#!/usr/bin/env python3
+"""r17 deterministic PCB author: netlist.json + spec footprints -> placed .kicad_pcb.
+RM-56 doctrine: no bytes through a model. Embeds real .kicad_mod libs from the
+KiCad AppDir, injects (net N "NAME") per pad (name-match, else positional match
+with WARN), shelf placement by footprint bbox + clearance, Edge.Cuts rect.
+DRC gate (board_gate_pcb.py) evaluates placement-class errors; unconnected_items
+are expected pre-routing and reported separately."""
+import json, re, os, sys
+from collections import defaultdict
+
+ALIASES = {}
+_ali = os.path.join(os.path.dirname(os.path.abspath(__file__)), "board_author_aliases.json")
+if os.path.exists(_ali):
+    ALIASES = {tuple(k.split("|")): v for k, v in json.load(open(_ali)).items()}
+
+FP_ROOT = "/home/lab/.local/AppDir/share/kicad/footprints"
+PLACE_MARGIN = 3.0   # mm between footprint bboxes (courtyard-ish)
+GRID = 0.1
+
+
+def snap(v):
+    return round(v / GRID) * GRID
+
+
+def forms(s):
+    """top-level s-expr blocks inside a ( ... ) wrapper string."""
+    out = []
+    i = 0
+    n = len(s)
+    while i < n:
+        if s[i] == "(":
+            depth = 0
+            j = i
+            instr = False
+            while j < n:
+                ch = s[j]
+                if ch == '"' and (j == 0 or s[j - 1] != "\\"):
+                    instr = not instr
+                elif not instr:
+                    if ch == "(":
+                        depth += 1
+                    elif ch == ")":
+                        depth -= 1
+                        if depth == 0:
+                            break
+                j += 1
+            out.append(s[i:j + 1])
+            i = j + 1
+        else:
+            i += 1
+    return out
+
+
+def sub_block(s, token):
+    """return (block, start, end) of first block starting with token, else None"""
+    for b in forms(s):
+        if b.startswith(f"({token}"):
+            return b
+    return None
+
+
+def bbox_of(km):
+    """rough extent from pads + courtyard graphic lines/rects."""
+    xs, ys = [], []
+    for m in re.finditer(r'\(pad[^()]*?\(at ([-\d.]+)(?: ([-\d.]+))?\)(?:\s*\(size ([-\d.]+) ([-\d.]+))?', km):
+        x, y = float(m.group(1)), float(m.group(2) or 0)
+        w, h = (float(m.group(3)), float(m.group(4))) if m.group(3) else (1.0, 1.0)
+        xs += [x - w / 2, x + w / 2]
+        ys += [y - h / 2, y + h / 2]
+    for m in re.finditer(r'\((?:xy|start|end|at) ([-\d.]+) ([-\d.]+)', km):
+        xs.append(float(m.group(1)))
+        ys.append(float(m.group(2)))
+    if not xs:
+        return -1, -1, 2, 2
+    pad = 0.5
+    return min(xs) - pad, min(ys) - pad, max(xs) + pad, max(ys) + pad
+
+
+def resolve_footprint(spec_fp):
+    lib, name = spec_fp.split(":", 1)
+    p = os.path.join(FP_ROOT, f"{lib}.pretty", f"{name}.kicad_mod")
+    return p if os.path.exists(p) else None
+
+
+def assign_nets(netlist):
+    nets = sorted({n for c in netlist["components"] for n in c["pins"].values()})
+    code = {n: i + 1 for i, n in enumerate(nets)}
+    return nets, code
+
+
+def author(netlist_path, out_path, rot_by_ref=None):
+    d = json.load(open(netlist_path))
+    comps = d["components"]
+    nets, ncode = assign_nets(d)
+    uuidn = [0]
+
+    def U():
+        uuidn[0] += 1
+        x = f"{uuidn[0]:032x}"
+        return f"{x[:8]}-{x[8:12]}-{x[12:16]}-{x[16:20]}-{x[20:32]}"
+
+    # ---- layout pass: shelf by bbox heights
+    items = []
+    warn = []
+    for c in sorted(comps, key=lambda c: (c["ref"][0], int(re.sub(r"\D", "", c["ref"]) or 0))):
+        fpp = resolve_footprint(c["footprint"])
+        if not fpp:
+            warn.append(f"NO-FOOTPRINT {c['ref']} {c['footprint']}")
+            continue
+        km = open(fpp).read()
+        x0, y0, x1, y1 = bbox_of(km)
+        items.append([c, km, snap(x1 - x0) + PLACE_MARGIN, snap(y1 - y0) + PLACE_MARGIN, (x0, y0)])
+    COL_W = 120.0
+    cx, cy, rowh = 10.0, 10.0, 0.0
+    placed = []
+    for it in items:
+        if cx + it[2] > COL_W:
+            cx = 10.0
+            cy += rowh
+            rowh = 0.0
+        placed.append((it, snap(cx), snap(cy)))
+        cx += it[2]
+        rowh = max(rowh, it[3])
+    board_w, board_h = snap(COL_W + 20), snap(cy + rowh + 20)
+
+    # ---- emit
+    L = ['(kicad_pcb (version 20260206) (generator "board_author_pcb") (generator_version "10.0")',
+         '  (general (thickness 1.6) (legacy_teardrops no))',
+         '  (paper "A3")',
+         '  (layers (0 "F.Cu" signal) (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") '
+         '(33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) '
+         '(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") '
+         '(38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") '
+         '(44 "Edge.Cuts" user) (45 "Margin" user "BoardOutline") (46 "B.CrtYd" user "B.Courtyard") '
+         '(47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) (50 "User.1" user))',
+         '  (setup (pad_to_mask_clearance 0))',
+         '  (net_class "Default" "" (clearance 0.2) (trace_width 0.25) (via_dia 0.6) (via_drill 0.3) (uvia_dia 0.3) (uvia_drill 0.1)'
+         + " " + "".join(f'(add_net "{esc(n)}")' for n in sorted(nets)) + ')']
+    L.append('  (net 0 "")')
+    for n in nets:
+        L.append(f'  (net {ncode[n]} "{n.replace(chr(92), chr(92)*2).replace(chr(34), chr(92)+chr(34))}")')
+    # Edge.Cuts rectangle
+    pts = [(5, 5), (board_w, 5), (board_w, board_h - 5), (5, board_h - 5), (5, 5)]
+    for i in range(4):
+        L.append(f'  (gr_line (start {pts[i][0]} {pts[i][1]}) (end {pts[i+1][0]} {pts[i+1][1]})'
+                 f' (stroke (width 0.1) (type solid)) (layer "Edge.Cuts") (uuid "{U()}"))')
+    for (it, px, py) in placed:
+        c, km, _, _, (x0, y0) = it
+        ref = c["ref"]
+        pins = c["pins"]
+        # pad name -> net number string; match footprint pad names
+        fp_padnames = re.findall(r'\(pad "([^"]*)"', km)  # file order; '' = np/mount hole
+        named = [n for n in fp_padnames if n]
+        mapping = {}
+        alias = ALIASES.get((ref, c["footprint"]))
+        if alias:
+            mapping = dict(alias)
+        elif set(pins) <= set(named):
+            pass  # identity match on covered pins; extra pads (shell/np) stay net 0
+        elif len(named) == len(pins):
+            order_pins = sorted(pins, key=lambda pin: int(pin) if pin.isdigit() else 0)
+            for fpn, spp in zip(named, order_pins):
+                mapping.setdefault(fpn, spp)
+            warn.append(f"POSITIONAL-MAP {ref} {c['footprint']}: {len(named)} pads zipped to spec pins — NO authority table, verify datasheet")
+        else:
+            warn.append(f"NO-AUTHORITY-MAP {ref} {c['footprint']}: pads {sorted(set(named))[:8]} vs spec pins {sorted(pins)[:8]} -> design-data GAP, net 0 (refusing to guess)")
+        # origin so that bbox min lands at px,py
+        ox, oy = snap(px - x0), snap(py - y0)
+        head = f'  (footprint "{esc(c["footprint"])}" (layer "F.Cu") (uuid "{U()}") (at {ox} {oy})'
+        head += (f' (property "Reference" "{esc(ref)}" (at 0 -1 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15))))'
+                 f' (property "Value" "{esc(c.get("mpn", ref))}" (at 0 1 0) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15))))')
+        body = km[km.index("(attr"):] if "(attr" in km else km[km.rindex(")"):]
+        # inject nets into pad blocks
+        out_km = []
+        pos = 0
+        for pb in forms(body):
+            m = re.match(r'\(pad "([^"]+)"', pb)
+            s, e = body.find(pb, pos), body.find(pb, pos) + len(pb)
+            if m:
+                padname = m.group(1)
+                pin = None if padname == "" else mapping.get(padname, padname if padname in pins else None)
+                if pin is not None:
+                    net = pins[pin]
+                    ins = f' (net {ncode[net]} "{esc(net)}")'
+                    pb = pb[:-1] + ins + ")"
+                pos = e
+            out_km.append((s, pb))
+        rebuilt = body
+        for s, pb in reversed(out_km):
+            e = s + None if False else s
+        # simpler: replace each original pad block string once
+        # (do textual replacement with count=1 on the ORIGINAL blocks)
+        for orig_pb in [b for b in forms(body) if b.startswith('(pad ')]:
+            new_pb = next(p for (s, p) in out_km if s == body.find(orig_pb))
+            rebuilt = rebuilt.replace(orig_pb, new_pb, 1)
+        rebuilt = rebuilt[:rebuilt.rindex(")")]  # strip trailing close of fp file
+        L.append(head + "\n" + rebuilt + "\n  )")
+    L.append(')\n')
+    open(out_path, "w").write("\n".join(x for x in L if x) + "\n")
+    pro = out_path[:-len(".kicad_pcb")] + ".kicad_pro"
+    import json as _j
+    _j.dump({
+        "board": {"design_settings": {
+            "defaults": {"board_outline_line_width": 0.1, "copper_line_width": 0.2,
+                         "solder_mask_clearance": 0.0, "solder_mask_min_width": 0.0,
+                         "allow_soldermask_bridges_in_footprints": True},
+            "drc_exclusions": [],
+            "rules": {"min_hole_to_hole": 0.15, "min_through_hole_diameter": 0.15,
+                      "min_clearance": 0.2, "min_connection": 0.0,
+                      "min_copper_edge_clearance": 0.1, "min_hole_clearance": 0.15,
+                      "min_silk_clearance": 0.0, "min_text_height": 0.8,
+                      "min_text_thickness": 0.12, "min_track_width": 0.15,
+                      "min_via_annular_width": 0.1, "min_via_diameter": 0.45,
+                      "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": True}}},
+        "libraries": {"fp_files": []},
+        "meta": {"filename": pro.split("/")[-1], "version": 3},
+        "net_settings": {"classes": [{"name": "Default", "clearance": 0.2,
+            "trace_width": 0.25, "via_dia": 0.6, "via_drill": 0.2, "uvia_dia": 0.3,
+            "uvia_drill": 0.1, "allow_soldermask_bridges_in_footprints": True}],
+            "meta": {"version": 3}},
+        "pcbnew": {"last_paths": {}},
+        "sheets": [], "text_variables": {}},
+        open(pro, "w"), indent=1)
+    return nets, warn, board_w, board_h
+
+
+def esc(s):
+    return str(s).replace("\\", "\\\\").replace('"', '\\"')
+
+
+if __name__ == "__main__":
+    nl = sys.argv[1]
+    out = sys.argv[2]
+    nets, warn, w, h = author(nl, out)
+    print(f"authored {out}: nets={len(nets)} board={w}x{h}mm")
+    for x in warn:
+        print("WARN", x)

package/graders/pcb-agent/seed/tools/board_author_sch.py

@@ -0,0 +1,118 @@
+#!/usr/bin/env python3
+"""r17 deterministic schematic author (RM-56: netlist bytes NEVER through a model).
+Topology: NO wires. Every pin gets one global label anchored EXACTLY on the pin
+end, rotation 180 (text left, away from body). Anchor == pin end by construction;
+no dangling labels (r13 D1 defect class), no collinear merges. Grid 0.635 mm.
+Usage: board_author_sch.py netlist.json -o out.kicad_sch"""
+import json, re, argparse
+from collections import defaultdict
+
+G = 0.635
+COLPITCH = 99.06   # column pitch (41-pin U1 fans 52mm left of anchor col)
+ROWPITCH = 76.2    # row pitch; keep > 2.54 * maxpins/2 stack of neighbours
+PINPITCH = 2.54    # pin vertical spacing (label height 1.27 leaves 1.27 gap)
+
+
+def snap(v):
+    return round(v / G) * G
+
+
+def esc(s):
+    return str(s).replace("\\", "\\\\").replace('"', '\\"')
+
+
+class Uuid:
+    def __init__(self):
+        self.n = 0
+
+    def __call__(self):
+        self.n += 1
+        x = f"{self.n:032x}"
+        return f"{x[:8]}-{x[8:12]}-{x[12:16]}-{x[16:20]}-{x[20:32]}"
+
+
+def pin_order(pins):
+    return sorted(pins, key=lambda p: int(p) if p.isdigit() else 0)
+
+
+def build(netlist_path, out_path):
+    d = json.load(open(netlist_path))
+    comps = d["components"]
+    u = Uuid()
+    order = sorted(comps, key=lambda c: (c["ref"][0], int(re.sub(r"\D", "", c["ref"]) or 0)))
+    pos = {}
+    for slot, c in enumerate(order):
+        row, col = divmod(slot, 4)
+        pos[c["ref"]] = (snap(60 + col * COLPITCH), snap(60 + row * ROWPITCH))
+    # symbol defs: single-sided fan-left, PINPITCH spacing
+    prefix_pins = {}
+    pinset = {}
+    for c in order:
+        ref = c["ref"]
+        ps = pin_order(c["pins"])
+        key = "SR_" + re.sub(r"\d+$", "", ref)
+        if key in prefix_pins and prefix_pins[key] != ps:
+            key = "SR_" + ref
+        prefix_pins.setdefault(key, ps)
+        c["_key"] = key
+        sx, sy = pos[ref]
+        n = len(ps)
+        # world y-down vs lib-symbol-local y-UP: the def emits oy=+off (up) per
+        # pin slot i; the label anchor in SHEET coords must therefore SUBTRACT.
+        pinset[ref] = [(p, snap(sx - 5.08), snap(sy - ((n - 1) / 2 - i) * PINPITCH))
+                       for i, p in enumerate(ps)]
+    labels = []
+    for c in order:
+        for pnum, net in c["pins"].items():
+            px, py = next((ax, ay) for (pp, ax, ay) in pinset[c["ref"]] if pp == pnum)
+            labels.append((net, px, py))
+    L = ['(kicad_sch (version 20250114) (generator "board_author_sch") (generator_version "10.0.5")',
+         f'  (uuid "{u()}")', '  (paper "A3")', '  (lib_symbols']
+    for key, ps in sorted(prefix_pins.items()):
+        n = len(ps)
+        L.append(f'    (symbol "solar_ray:{esc(key)}"')
+        L.append('      (pin_numbers (hide yes))')
+        L.append('      (pin_names (offset 1.016))')
+        L.append('      (exclude_from_sim no) (in_bom yes) (on_board yes)')
+        L.append('      (property "Reference" "U" (at 0 0 0) (effects (font (size 1.27 1.27))))')
+        L.append('      (property "Value" "V" (at 0 0 0) (effects (font (size 1.27 1.27))))')
+        L.append('      (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes)))')
+        L.append('      (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes)))')
+        L.append(f'      (symbol "{esc(key)}_1_1"')
+        for i, p in enumerate(ps):
+            oy = snap(((n - 1) / 2 - i) * PINPITCH)
+            L.append(f'        (pin passive line (at {-5.08} {oy} 0) (length 5.08)'
+                     f' (name "~" (effects (font (size 1.016 1.016))))'
+                     f' (number "{esc(p)}" (effects (font (size 1.016 1.016)))))')
+        L.append('      )')
+        L.append('      (embedded_fonts no)')
+        L.append('    )')
+    L.append('  )')
+    for c in order:
+        ref = c["ref"]
+        sx, sy = pos[ref]
+        L.append(f'    (symbol (lib_id "solar_ray:{esc(c["_key"])}") (at {sx} {sy} 0) (unit 1)')
+        L.append('      (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced no)')
+        L.append(f'      (uuid "{u()}")')
+        for k, v, xo in (("Reference", ref, -2.54), ("Value", c.get("mpn", ref), 2.54),
+                         ("Footprint", c.get("footprint", ""), 0.0), ("Datasheet", "", 0.0)):
+            L.append(f'      (property "{k}" "{esc(v)}" (at {snap(sx+xo)} {snap(sy+5.08)} 0)'
+                     f' (effects (font (size 1.27 1.27)) (hide yes)))')
+        for (p, _, _) in pinset[ref]:
+            L.append(f'      (pin "{esc(p)}" (uuid "{u()}"))')
+        L.append('    )')
+    for net, x, y in labels:
+        L.append(f'    (global_label "{esc(net)}" (shape passive) (at {x} {y} 180)'
+                 f' (effects (font (size 1.27 1.27)) (justify left)) (uuid "{u()}"))')
+    L += ['  (sheet_instances', '    (path "/" (page "1"))', '  )', '  (embedded_fonts no)', ')']
+    open(out_path, "w").write("\n".join(L) + "\n")
+    return len(order), len(labels)
+
+
+if __name__ == "__main__":
+    ap = argparse.ArgumentParser()
+    ap.add_argument("netlist")
+    ap.add_argument("-o", "--out", required=True)
+    a = ap.parse_args()
+    s, l = build(a.netlist, a.out)
+    print(f"emitted {a.out}: symbols={s} labels={l}")

package/graders/pcb-agent/seed/tools/board_finalize.sh

@@ -0,0 +1,23 @@
+#!/bin/bash
+# r17 finalization pipeline: routed board -> pour -> native refill -> DRC gate -> fab exports
+set -e
+IN="${1:?routed kicad_pcb}"
+OUT="${2:?output board pcb}"
+RUN="${3:-evolution-round-17}"
+cd /home/lab/workspace/pcb-control
+python3 tools/board_zone_pour.py "$IN" "$OUT"
+cp /tmp/sr-c4.kicad_pro "$(dirname "$OUT")/$(basename "$OUT" .kicad_pcb).kicad_pro"
+D=/home/lab/workspace/pcb-control/reports/recovery/$RUN
+kicad-cli pcb drc "$OUT" --refill-zones --save-board --format json --severity-error --output "$D/$(basename "$OUT").drc-refill.json" >/dev/null 2>&1
+kicad-cli pcb drc "$OUT" --format json --severity-error --output "$D/$(basename "$OUT").drc-final.json" >/dev/null 2>&1
+python3 - "$D/$(basename "$OUT").drc-final.json" <<'EOF'
+import json, sys, collections
+d = json.load(open(sys.argv[1]))
+v = d.get('violations', []); u = d.get('unconnected_items', [])
+print(f"GATE: errors={len(v)} {dict(collections.Counter(x.get('type','?') for x in v))} unconnected={len(u)}")
+EOF
+mkdir -p "$D/fab-out"
+kicad-cli pcb export gerbers "$OUT" -o "$D/fab-out/gerbers.zip" >/dev/null
+kicad-cli pcb export drill "$OUT" -o "$D/fab-out/" >/dev/null
+kicad-cli pcb export pos "$OUT" -o "$D/fab-out/pos.pos" --units mm >/dev/null
+echo "fab exports -> $D/fab-out/"; ls "$D/fab-out/" | head