@schemd/core 0.2.1 → 0.3.1

package/dist/types.d.ts

@@ -11,16 +11,20 @@
 export declare const PASSIVE_KINDS: readonly ["resistor", "capacitor", "inductor"];
 /** A supported passive two-terminal component keyword. */
 export type PassiveKind = (typeof PASSIVE_KINDS)[number];
+/** Compact variant registry shared by the three passive families. */
+export declare const PASSIVE_TYPES: readonly ["fixed", "variable", "rheostat", "potentiometer", "thermistor", "ldr", "polarized", "coupled", "transformer"];
+/** A validated passive construction variant. */
+export type PassiveType = (typeof PASSIVE_TYPES)[number];
 /** Discrete analog and boundary component keywords accepted by the DSL. */
 export declare const ANALOG_KINDS: readonly ["diode", "transistor", "port", "ground"];
 /** A supported discrete analog or boundary component keyword. */
 export type AnalogKind = (typeof ANALOG_KINDS)[number];
 /** Valid diode construction variants. */
-export declare const DIODE_TYPES: readonly ["standard", "schottky", "zener", "led"];
+export declare const DIODE_TYPES: readonly ["standard", "schottky", "zener", "led", "photodiode", "varactor", "scr", "triac"];
 /** A diode construction variant selected by the `type` attribute. */
 export type DiodeType = (typeof DIODE_TYPES)[number];
 /** Valid bipolar and field-effect transistor variants. */
-export declare const TRANSISTOR_TYPES: readonly ["npn", "pnp", "nmos", "pmos"];
+export declare const TRANSISTOR_TYPES: readonly ["npn", "pnp", "nmos", "pmos", "njfet", "pjfet", "nigbt", "pigbt"];
 /** A transistor variant selected by the `type` attribute. */
 export type TransistorType = (typeof TRANSISTOR_TYPES)[number];
 /** Valid electrical ground symbol styles. */
@@ -28,19 +32,57 @@ export declare const GROUND_STYLES: readonly ["chassis", "earth", "signal"];
 /** A ground symbol style selected by the `style` attribute. */
 export type GroundStyle = (typeof GROUND_STYLES)[number];
 /** Classical logic gate keywords supported by the vector renderer. */
-export declare const CLASSICAL_GATE_KINDS: readonly ["nand", "nor", "xor", "and", "or", "not"];
+export declare const ELECTRICAL_COMPONENT_KINDS: readonly ["source", "junction", "testpoint", "connector", "power", "switch", "protection", "amplifier", "resonator", "meter", "load"];
+export type ElectricalComponentKind = (typeof ELECTRICAL_COMPONENT_KINDS)[number];
+export declare const SOURCE_TYPES: readonly ["voltage-dc", "voltage-ac", "voltage-pulse", "current-dc", "current-ac", "battery", "vcvs", "vccs", "ccvs", "cccs"];
+export type SourceType = (typeof SOURCE_TYPES)[number];
+export declare const POWER_TYPES: readonly ["vcc", "vdd", "vss", "positive", "negative"];
+export type PowerType = (typeof POWER_TYPES)[number];
+export declare const SWITCH_TYPES: readonly ["spst", "spdt", "pushbutton", "relay"];
+export type SwitchType = (typeof SWITCH_TYPES)[number];
+export declare const PROTECTION_TYPES: readonly ["fuse", "breaker"];
+export type ProtectionType = (typeof PROTECTION_TYPES)[number];
+export declare const AMPLIFIER_TYPES: readonly ["opamp", "comparator", "instrumentation"];
+export type AmplifierType = (typeof AMPLIFIER_TYPES)[number];
+export declare const RESONATOR_TYPES: readonly ["crystal", "ceramic"];
+export type ResonatorType = (typeof RESONATOR_TYPES)[number];
+export declare const METER_TYPES: readonly ["voltmeter", "ammeter"];
+export type MeterType = (typeof METER_TYPES)[number];
+export declare const LOAD_TYPES: readonly ["lamp", "motor", "speaker", "buzzer"];
+export type LoadType = (typeof LOAD_TYPES)[number];
+/** Classical logic gates with IEEE- and IEC-style vector contours. */
+export declare const CLASSICAL_GATE_KINDS: readonly ["nand", "nor", "xor", "xnor", "and", "or", "not"];
 /** A supported classical logic gate keyword. */
 export type ClassicalGateKind = (typeof CLASSICAL_GATE_KINDS)[number];
 /** Native and polymorphic quantum operator keywords. */
-export declare const QUANTUM_GATE_KINDS: readonly ["hadamard", "cnot", "qgate"];
+export declare const DIGITAL_COMPONENT_KINDS: readonly ["buffer", "logic", "clock", "flipflop", "mux", "encoder", "decoder", "register", "counter", "adder", "comparator", "bus"];
+export type DigitalComponentKind = (typeof DIGITAL_COMPONENT_KINDS)[number];
+export declare const BUFFER_TYPES: readonly ["plain", "tristate", "tristate-inverter", "schmitt", "schmitt-inverter"];
+export type BufferType = (typeof BUFFER_TYPES)[number];
+export declare const LOGIC_STATES: readonly ["high", "low", "unknown", "high-z"];
+export type LogicState = (typeof LOGIC_STATES)[number];
+export declare const FLIPFLOP_TYPES: readonly ["sr-latch", "d-latch", "d", "jk", "t"];
+export type FlipFlopType = (typeof FLIPFLOP_TYPES)[number];
+export declare const MUX_TYPES: readonly ["mux", "demux"];
+export type MuxType = (typeof MUX_TYPES)[number];
+export declare const ADDER_TYPES: readonly ["half", "full"];
+export type AdderType = (typeof ADDER_TYPES)[number];
+export declare const BUS_TYPES: readonly ["tap", "splitter", "joiner"];
+export type BusType = (typeof BUS_TYPES)[number];
+/** Native, named, and polymorphic quantum operator keywords. */
+export declare const NAMED_QUANTUM_GATE_KINDS: readonly ["xgate", "ygate", "zgate", "sgate", "sdg", "tgate", "tdg", "sx", "phase", "rx", "ry", "rz", "ugate"];
+export type NamedQuantumGateKind = (typeof NAMED_QUANTUM_GATE_KINDS)[number];
+export declare const QUANTUM_SPECIAL_KINDS: readonly ["measure", "reset", "prepare", "swap", "control", "cz", "cphase", "toffoli", "controlled", "barrier", "delay", "classical-bit", "classical-register"];
+export type QuantumSpecialKind = (typeof QUANTUM_SPECIAL_KINDS)[number];
+export declare const QUANTUM_GATE_KINDS: readonly ["hadamard", "cnot", "qgate", "xgate", "ygate", "zgate", "sgate", "sdg", "tgate", "tdg", "sx", "phase", "rx", "ry", "rz", "ugate"];
 /** A supported native or polymorphic quantum gate keyword. */
 export type QuantumGateKind = (typeof QUANTUM_GATE_KINDS)[number];
 /** First-class UML node keywords spanning structural and behavioral diagrams. */
-export declare const UML_COMPONENT_KINDS: readonly ["class", "actor", "usecase", "state", "lifeline", "note", "package", "initial", "final"];
+export declare const UML_COMPONENT_KINDS: readonly ["class", "interface", "provided-interface", "required-interface", "enumeration", "datatype", "object", "component", "component-port", "artifact", "node", "device", "execution", "system", "actor", "usecase", "state", "lifeline", "action", "decision", "merge", "fork", "join", "activity-final", "flow-final", "object-node", "send-signal", "receive-signal", "partition", "activation", "destruction", "fragment", "interaction", "gate", "found", "lost", "choice", "state-junction", "history", "entry", "exit", "terminate", "region", "note", "package", "initial", "final"];
 /** A supported UML node keyword. */
 export type UmlComponentKind = (typeof UML_COMPONENT_KINDS)[number];
 /** Complete, collision-free component keyword registry. */
-export declare const COMPONENT_KINDS: readonly ["resistor", "capacitor", "inductor", "diode", "transistor", "port", "ground", "nand", "nor", "xor", "and", "or", "not", "hadamard", "cnot", "qgate", "class", "actor", "usecase", "state", "lifeline", "note", "package", "initial", "final", "ic"];
+export declare const COMPONENT_KINDS: readonly ["resistor", "capacitor", "inductor", "diode", "transistor", "port", "ground", "source", "junction", "testpoint", "connector", "power", "switch", "protection", "amplifier", "resonator", "meter", "load", "nand", "nor", "xor", "xnor", "and", "or", "not", "buffer", "logic", "clock", "flipflop", "mux", "encoder", "decoder", "register", "counter", "adder", "comparator", "bus", "hadamard", "cnot", "qgate", "xgate", "ygate", "zgate", "sgate", "sdg", "tgate", "tdg", "sx", "phase", "rx", "ry", "rz", "ugate", "measure", "reset", "prepare", "swap", "control", "cz", "cphase", "toffoli", "controlled", "barrier", "delay", "classical-bit", "classical-register", "class", "interface", "provided-interface", "required-interface", "enumeration", "datatype", "object", "component", "component-port", "artifact", "node", "device", "execution", "system", "actor", "usecase", "state", "lifeline", "action", "decision", "merge", "fork", "join", "activity-final", "flow-final", "object-node", "send-signal", "receive-signal", "partition", "activation", "destruction", "fragment", "interaction", "gate", "found", "lost", "choice", "state-junction", "history", "entry", "exit", "terminate", "region", "note", "package", "initial", "final", "ic"];
 /** Any component keyword that can begin a declaration. */
 export type ComponentKind = (typeof COMPONENT_KINDS)[number];
 /** Built-in semantic color tokens that hosts can theme through CSS. */
@@ -85,6 +127,12 @@ export interface SchematicPoint {
     /** Vertical coordinate. */
     y: number;
 }
+/** Author-facing quarter-turn orientations for direction-sensitive components. */
+export declare const SCHEMATIC_ORIENTATIONS: readonly ["right", "down", "left", "up"];
+/** A direction-sensitive component's canonical quarter-turn orientation. */
+export type SchematicOrientation = (typeof SCHEMATIC_ORIENTATIONS)[number];
+/** Compact clockwise quarter-turn count used by exact layout arithmetic. */
+export type SchematicQuarterTurn = 0 | 1 | 2 | 3;
 /** Shared immutable source metadata for every parsed component. */
 interface ComponentBase extends SchematicPoint {
     /** Document-unique component identifier used by connection endpoints. */
@@ -96,39 +144,56 @@ interface ComponentBase extends SchematicPoint {
     /** One-based source line used for deterministic diagnostics. */
     line: number;
 }
+/** Shared metadata for symbols whose canonical geometry supports quarter turns. */
+export interface DirectionalComponentBase extends ComponentBase {
+    /** Explicit orientation; absence preserves the legacy canonical direction. */
+    orientation?: SchematicOrientation;
+}
 /** Parsed resistor, capacitor, or inductor component. */
-export interface PassiveComponent extends ComponentBase {
+export interface PassiveComponent extends DirectionalComponentBase {
     /** Specific two-terminal passive kind. */
     kind: PassiveKind;
+    /** Non-default construction variant; absence means fixed. */
+    passiveType?: PassiveType;
 }
 /** Parsed diode with its selected physical symbol variant. */
-export interface DiodeComponent extends ComponentBase {
+export interface DiodeComponent extends DirectionalComponentBase {
     /** Discriminant for diode components. */
     kind: 'diode';
     /** Standard, Schottky, Zener, or LED vector treatment. */
     diodeType: DiodeType;
 }
 /** Parsed bipolar or field-effect transistor. */
-export interface TransistorComponent extends ComponentBase {
+export interface TransistorComponent extends DirectionalComponentBase {
     /** Discriminant for transistor components. */
     kind: 'transistor';
     /** Electrical device family and polarity. */
     transistorType: TransistorType;
 }
 /** Parsed system-boundary input/output terminal. */
-export interface PortComponent extends ComponentBase {
+export interface PortComponent extends DirectionalComponentBase {
     /** Discriminant for boundary ports. */
     kind: 'port';
+    /** Optional bus width; absence is a scalar port. */
+    width?: number;
 }
 /** Parsed zero-volt reference symbol. */
-export interface GroundComponent extends ComponentBase {
+export interface GroundComponent extends DirectionalComponentBase {
     /** Discriminant for ground references. */
     kind: 'ground';
     /** Chassis, earth, or signal-ground visual form. */
     groundStyle: GroundStyle;
 }
+/** Variant value accepted by one of the compact electrical symbol families. */
+export type ElectricalVariant = SourceType | PowerType | SwitchType | ProtectionType | AmplifierType | ResonatorType | MeterType | LoadType;
+/** Parsed source, switch, functional block, load, or electrical node. */
+export interface ElectricalComponent extends DirectionalComponentBase {
+    kind: ElectricalComponentKind;
+    /** Family-specific validated variant; absent only for junction/testpoint/connector. */
+    variant?: ElectricalVariant;
+}
 /** Parsed IEEE- or IEC-style classical logic gate. */
-export interface ClassicalGateComponent extends ComponentBase {
+export interface ClassicalGateComponent extends DirectionalComponentBase {
     /** Logic operation represented by the gate. */
     kind: ClassicalGateKind;
     /** Validated number of addressable input pins, from 1 through 32. */
@@ -138,8 +203,23 @@ export interface ClassicalGateComponent extends ComponentBase {
     /** Symbol convention used when generating the gate contour. */
     standard: 'ieee' | 'iec';
 }
+/** Compact digital block normalized from storage, selection, arithmetic, and bus keywords. */
+export interface DigitalComponent extends DirectionalComponentBase {
+    kind: DigitalComponentKind;
+    /** Family-specific variant such as tristate, D flip-flop, or splitter. */
+    variant?: BufferType | LogicState | FlipFlopType | MuxType | AdderType | BusType;
+    /** Validated logical input count. */
+    inputs: number;
+    /** Validated logical output count. */
+    outputs: number;
+    /** Scalar width or bus width represented by relevant terminals. */
+    width: number;
+    /** Deterministic body dimensions used by ports, obstacles, and SVG generation. */
+    bodyWidth: number;
+    bodyHeight: number;
+}
 /** Parsed native or user-labelled quantum operator. */
-export interface QuantumGateComponent extends ComponentBase {
+export interface QuantumGateComponent extends DirectionalComponentBase {
     /** Quantum operator family. */
     kind: QuantumGateKind;
     /** Optional operator parameter rendered through the micro-math pipeline. */
@@ -149,6 +229,22 @@ export interface QuantumGateComponent extends ComponentBase {
     /** Optional phase expression. */
     phase?: string;
 }
+/** Non-unitary, multi-wire, control, timing, or classical quantum-circuit primitive. */
+export interface QuantumSpecialComponent extends DirectionalComponentBase {
+    kind: QuantumSpecialKind;
+    /** Positive or negative standalone/embedded control marker. */
+    controlType?: 'positive' | 'negative' | 'classical';
+    /** Operator rendered at the target of a generalized controlled gate. */
+    operator?: string;
+    /** Number of control tracks. */
+    controls: number;
+    /** Number of target tracks. */
+    targets: number;
+    /** Total parallel tracks accepted by barriers, delays, and registers. */
+    wires: number;
+    /** Classical register width, or one for scalar quantum/classical nodes. */
+    width: number;
+}
 /** Pin names registered on each side of a polymorphic integrated circuit. */
 export interface IntegratedCircuitPins {
     /** Pins distributed from top to bottom on the left edge. */
@@ -161,7 +257,7 @@ export interface IntegratedCircuitPins {
     bottom: readonly string[];
 }
 /** Parsed custom multi-terminal integrated-circuit block. */
-export interface IcComponent extends ComponentBase {
+export interface IcComponent extends DirectionalComponentBase {
     /** Discriminant for custom integrated circuits and architecture blocks. */
     kind: 'ic';
     /** Addressable, side-aware pin registry. */
@@ -176,7 +272,7 @@ export type IntegratedCircuitComponent = IcComponent;
 /** Parsed UML class with independently sized attribute and operation compartments. */
 export interface UmlClassComponent extends ComponentBase {
     /** UML class node discriminant. */
-    kind: 'class';
+    kind: 'class' | 'interface' | 'enumeration' | 'datatype' | 'object';
     /** Optional stereotype displayed above the class name. */
     stereotype?: string;
     /** Attribute declarations in source order. */
@@ -198,7 +294,7 @@ export interface UmlStateComponent extends ComponentBase {
 }
 /** Parsed UML ellipse, note, package, or sequence lifeline. */
 export interface UmlSizedComponent extends ComponentBase {
-    kind: 'usecase' | 'lifeline' | 'note' | 'package';
+    kind: 'usecase' | 'lifeline' | 'note' | 'package' | 'component' | 'artifact' | 'node' | 'device' | 'execution' | 'system' | 'action' | 'object-node' | 'partition' | 'activation' | 'fragment' | 'interaction' | 'region';
     bodyWidth: number;
     bodyHeight: number;
 }
@@ -208,18 +304,23 @@ export interface UmlActorComponent extends ComponentBase {
 }
 /** Parsed UML initial or final pseudostate. */
 export interface UmlPseudostateComponent extends ComponentBase {
-    kind: 'initial' | 'final';
+    kind: 'initial' | 'final' | 'provided-interface' | 'required-interface' | 'component-port' | 'decision' | 'merge' | 'fork' | 'join' | 'activity-final' | 'flow-final' | 'send-signal' | 'receive-signal' | 'destruction' | 'gate' | 'found' | 'lost' | 'choice' | 'state-junction' | 'history' | 'entry' | 'exit' | 'terminate';
+    /** History depth; present only on history pseudostates. */
+    variant?: 'shallow' | 'deep';
 }
 /** Every UML component accepted by the compiler. */
 export type UmlComponent = UmlClassComponent | UmlStateComponent | UmlSizedComponent | UmlActorComponent | UmlPseudostateComponent;
 /** Discriminated union of every component node accepted by the renderer. */
-export type SchematicComponent = PassiveComponent | DiodeComponent | TransistorComponent | PortComponent | GroundComponent | ClassicalGateComponent | QuantumGateComponent | IcComponent | UmlComponent;
+export type SchematicComponent = PassiveComponent | DiodeComponent | TransistorComponent | PortComponent | GroundComponent | ElectricalComponent | ClassicalGateComponent | DigitalComponent | QuantumGateComponent | QuantumSpecialComponent | IcComponent | UmlComponent;
 /** UML relationship semantics used to derive line style and endpoint markers. */
-export declare const UML_RELATION_KINDS: readonly ["association", "dependency", "generalization", "realization", "aggregation", "composition", "message", "transition", "include", "extend"];
+export declare const UML_RELATION_KINDS: readonly ["association", "dependency", "generalization", "realization", "aggregation", "composition", "message", "synchronous", "asynchronous", "return", "control-flow", "object-flow", "assembly", "delegation", "transition", "include", "extend"];
 /** A supported UML relationship. */
 export type UmlRelationKind = (typeof UML_RELATION_KINDS)[number];
 /** Electrical signal or a first-class UML relationship. */
 export type SchematicRelationKind = 'signal' | UmlRelationKind;
+/** Physical/semantic channel carried by a signal connection. */
+export declare const SCHEMATIC_SIGNAL_KINDS: readonly ["electrical", "digital", "quantum", "classical"];
+export type SchematicSignalKind = (typeof SCHEMATIC_SIGNAL_KINDS)[number];
 /** Address of one component terminal in a connection declaration. */
 export interface SchematicEndpoint {
     /** Document-local component identifier. */
@@ -243,6 +344,10 @@ export interface SchematicConnection {
     markerEnd: SchematicSignalMarker;
     /** Electrical or UML relationship semantics. */
     relation?: SchematicRelationKind;
+    /** Non-default signal domain; absence preserves legacy electrical behavior. */
+    signalKind?: SchematicSignalKind;
+    /** Validated bus/register width; absence denotes a scalar connection. */
+    width?: number;
     /** Optional text centered beside the routed connector. */
     label?: string;
     /** Whether the trace uses the UML dependency dash pattern. */

package/dist/types.js

@@ -1,16 +1,167 @@
 export const PASSIVE_KINDS = ['resistor', 'capacitor', 'inductor'];
+export const PASSIVE_TYPES = [
+    'fixed',
+    'variable',
+    'rheostat',
+    'potentiometer',
+    'thermistor',
+    'ldr',
+    'polarized',
+    'coupled',
+    'transformer'
+];
 export const ANALOG_KINDS = ['diode', 'transistor', 'port', 'ground'];
-export const DIODE_TYPES = ['standard', 'schottky', 'zener', 'led'];
-export const TRANSISTOR_TYPES = ['npn', 'pnp', 'nmos', 'pmos'];
+export const DIODE_TYPES = [
+    'standard',
+    'schottky',
+    'zener',
+    'led',
+    'photodiode',
+    'varactor',
+    'scr',
+    'triac'
+];
+export const TRANSISTOR_TYPES = ['npn', 'pnp', 'nmos', 'pmos', 'njfet', 'pjfet', 'nigbt', 'pigbt'];
 export const GROUND_STYLES = ['chassis', 'earth', 'signal'];
-export const CLASSICAL_GATE_KINDS = ['nand', 'nor', 'xor', 'and', 'or', 'not'];
-export const QUANTUM_GATE_KINDS = ['hadamard', 'cnot', 'qgate'];
+export const ELECTRICAL_COMPONENT_KINDS = [
+    'source',
+    'junction',
+    'testpoint',
+    'connector',
+    'power',
+    'switch',
+    'protection',
+    'amplifier',
+    'resonator',
+    'meter',
+    'load'
+];
+export const SOURCE_TYPES = [
+    'voltage-dc',
+    'voltage-ac',
+    'voltage-pulse',
+    'current-dc',
+    'current-ac',
+    'battery',
+    'vcvs',
+    'vccs',
+    'ccvs',
+    'cccs'
+];
+export const POWER_TYPES = ['vcc', 'vdd', 'vss', 'positive', 'negative'];
+export const SWITCH_TYPES = ['spst', 'spdt', 'pushbutton', 'relay'];
+export const PROTECTION_TYPES = ['fuse', 'breaker'];
+export const AMPLIFIER_TYPES = ['opamp', 'comparator', 'instrumentation'];
+export const RESONATOR_TYPES = ['crystal', 'ceramic'];
+export const METER_TYPES = ['voltmeter', 'ammeter'];
+export const LOAD_TYPES = ['lamp', 'motor', 'speaker', 'buzzer'];
+export const CLASSICAL_GATE_KINDS = ['nand', 'nor', 'xor', 'xnor', 'and', 'or', 'not'];
+export const DIGITAL_COMPONENT_KINDS = [
+    'buffer',
+    'logic',
+    'clock',
+    'flipflop',
+    'mux',
+    'encoder',
+    'decoder',
+    'register',
+    'counter',
+    'adder',
+    'comparator',
+    'bus'
+];
+export const BUFFER_TYPES = [
+    'plain',
+    'tristate',
+    'tristate-inverter',
+    'schmitt',
+    'schmitt-inverter'
+];
+export const LOGIC_STATES = ['high', 'low', 'unknown', 'high-z'];
+export const FLIPFLOP_TYPES = ['sr-latch', 'd-latch', 'd', 'jk', 't'];
+export const MUX_TYPES = ['mux', 'demux'];
+export const ADDER_TYPES = ['half', 'full'];
+export const BUS_TYPES = ['tap', 'splitter', 'joiner'];
+export const NAMED_QUANTUM_GATE_KINDS = [
+    'xgate',
+    'ygate',
+    'zgate',
+    'sgate',
+    'sdg',
+    'tgate',
+    'tdg',
+    'sx',
+    'phase',
+    'rx',
+    'ry',
+    'rz',
+    'ugate'
+];
+export const QUANTUM_SPECIAL_KINDS = [
+    'measure',
+    'reset',
+    'prepare',
+    'swap',
+    'control',
+    'cz',
+    'cphase',
+    'toffoli',
+    'controlled',
+    'barrier',
+    'delay',
+    'classical-bit',
+    'classical-register'
+];
+export const QUANTUM_GATE_KINDS = [
+    'hadamard',
+    'cnot',
+    'qgate',
+    ...NAMED_QUANTUM_GATE_KINDS
+];
 export const UML_COMPONENT_KINDS = [
     'class',
+    'interface',
+    'provided-interface',
+    'required-interface',
+    'enumeration',
+    'datatype',
+    'object',
+    'component',
+    'component-port',
+    'artifact',
+    'node',
+    'device',
+    'execution',
+    'system',
     'actor',
     'usecase',
     'state',
     'lifeline',
+    'action',
+    'decision',
+    'merge',
+    'fork',
+    'join',
+    'activity-final',
+    'flow-final',
+    'object-node',
+    'send-signal',
+    'receive-signal',
+    'partition',
+    'activation',
+    'destruction',
+    'fragment',
+    'interaction',
+    'gate',
+    'found',
+    'lost',
+    'choice',
+    'state-junction',
+    'history',
+    'entry',
+    'exit',
+    'terminate',
+    'region',
     'note',
     'package',
     'initial',
@@ -19,12 +170,16 @@ export const UML_COMPONENT_KINDS = [
 export const COMPONENT_KINDS = [
     ...PASSIVE_KINDS,
     ...ANALOG_KINDS,
+    ...ELECTRICAL_COMPONENT_KINDS,
     ...CLASSICAL_GATE_KINDS,
+    ...DIGITAL_COMPONENT_KINDS,
     ...QUANTUM_GATE_KINDS,
+    ...QUANTUM_SPECIAL_KINDS,
     ...UML_COMPONENT_KINDS,
     'ic'
 ];
 export const SEMANTIC_COLORS = ['amber', 'blue', 'cyan', 'purple', 'slate', 'emerald'];
+export const SCHEMATIC_ORIENTATIONS = ['right', 'down', 'left', 'up'];
 export const UML_RELATION_KINDS = [
     'association',
     'dependency',
@@ -33,10 +188,18 @@ export const UML_RELATION_KINDS = [
     'aggregation',
     'composition',
     'message',
+    'synchronous',
+    'asynchronous',
+    'return',
+    'control-flow',
+    'object-flow',
+    'assembly',
+    'delegation',
     'transition',
     'include',
     'extend'
 ];
+export const SCHEMATIC_SIGNAL_KINDS = ['electrical', 'digital', 'quantum', 'classical'];
 export const SCHEMD_OUTPUT_MODES = ['default', 'embedded-css', 'full'];
 export const SCHEMD_SEMANTIC_HOOKS = ['nodes', 'ports', 'wires'];
 export const SCHEMATIC_SIGNAL_MARKERS = [

package/package.json

@@ -1,80 +1,85 @@
 {
-	"name": "@schemd/core",
-	"version": "0.2.1",
-	"description": "Zero-dependency text-to-SVG compiler for schematics and UML.",
-	"homepage": "https://johnowolabiidogun.dev/tools/schemd",
-	"bugs": {
-		"url": "https://github.com/Sirneij/schemd/issues"
-	},
-	"repository": {
-		"type": "git",
-		"url": "git+https://github.com/Sirneij/schemd.git"
-	},
-	"type": "module",
-	"sideEffects": false,
-	"browser": false,
-	"main": "./dist/index.js",
-	"types": "./dist/index.d.ts",
-	"files": [
-		"dist",
-		"README.md",
-		"assets/brand/schemd-logo.svg",
-		"assets/brand/schemd-mark.svg"
-	],
-	"exports": {
-		".": {
-			"types": "./dist/index.d.ts",
-			"import": "./dist/index.js"
-		},
-		"./parser": {
-			"types": "./dist/parser.d.ts",
-			"import": "./dist/parser.js"
-		},
-		"./renderer": {
-			"types": "./dist/renderer.d.ts",
-			"import": "./dist/renderer.js"
-		},
-		"./compiler": {
-			"types": "./dist/compiler.d.ts",
-			"import": "./dist/compiler.js"
-		},
-		"./layout": {
-			"types": "./dist/layout.d.ts",
-			"import": "./dist/layout.js"
-		},
-		"./math-label": {
-			"types": "./dist/math-label.d.ts",
-			"import": "./dist/math-label.js"
-		},
-		"./types": {
-			"types": "./dist/types.d.ts",
-			"import": "./dist/types.js"
-		}
-	},
-	"scripts": {
-		"build": "node -e \"require('node:fs').rmSync('dist',{ recursive: true, force: true })\" && tsc -p tsconfig.build.json && tsc -p tsconfig.types.json",
-		"check": "tsc -p tsconfig.json --noEmit",
-		"prepack": "npm run build",
-		"size": "node scripts/check-bundle-size.mjs",
-		"test": "vitest run",
-		"test:coverage": "vitest run --coverage"
-	},
-	"devDependencies": {
-		"@vitest/coverage-v8": "^4.1.10",
-		"typescript": "^6.0.3",
-		"vite": "^8.1.4",
-		"vitest": "^4.1.10"
-	},
-	"engines": {
-		"node": ">=24"
-	},
-	"keywords": [
-		"schemd",
-		"schematic",
-		"svg",
-		"compiler",
-		"engineering",
-		"uml"
-	],
-	"license": "MIT"
+  "name": "@schemd/core",
+  "version": "0.3.1",
+  "description": "Zero-dependency text-to-SVG compiler for schematics and UML.",
+  "homepage": "https://schemd.johnowolabiidogun.dev",
+  "bugs": {
+    "url": "https://github.com/schemd/core/issues"
+  },
+  "repository": {
+    "type": "git",
+    "url": "git+https://github.com/schemd/core.git"
+  },
+  "author": {
+    "name": "John Owolabi Idogun",
+    "url": "https://www.johnowolabiidogun.dev"
+  },
+  "packageManager": "bun@1.3.14",
+  "type": "module",
+  "sideEffects": false,
+  "browser": false,
+  "main": "./dist/index.js",
+  "types": "./dist/index.d.ts",
+  "files": [
+    "dist",
+    "README.md",
+    "CHANGELOG.md"
+  ],
+  "exports": {
+    ".": {
+      "types": "./dist/index.d.ts",
+      "import": "./dist/index.js"
+    },
+    "./parser": {
+      "types": "./dist/parser.d.ts",
+      "import": "./dist/parser.js"
+    },
+    "./renderer": {
+      "types": "./dist/renderer.d.ts",
+      "import": "./dist/renderer.js"
+    },
+    "./compiler": {
+      "types": "./dist/compiler.d.ts",
+      "import": "./dist/compiler.js"
+    },
+    "./layout": {
+      "types": "./dist/layout.d.ts",
+      "import": "./dist/layout.js"
+    },
+    "./math-label": {
+      "types": "./dist/math-label.d.ts",
+      "import": "./dist/math-label.js"
+    },
+    "./types": {
+      "types": "./dist/types.d.ts",
+      "import": "./dist/types.js"
+    }
+  },
+  "scripts": {
+    "build": "node -e \"require('node:fs').rmSync('dist',{ recursive: true, force: true })\" && tsc -p tsconfig.build.json && tsc -p tsconfig.types.json",
+    "benchmark": "bun run build && node scripts/benchmark.mjs",
+    "check": "tsc -p tsconfig.json --noEmit",
+    "prepack": "bun run build",
+    "size": "node scripts/check-bundle-size.mjs",
+    "test": "vitest run",
+    "test:coverage": "vitest run --coverage"
+  },
+  "devDependencies": {
+    "@vitest/coverage-v8": "^4.1.10",
+    "typescript": "^6.0.3",
+    "vite": "^8.1.4",
+    "vitest": "^4.1.10"
+  },
+  "engines": {
+    "node": ">=24"
+  },
+  "keywords": [
+    "schemd",
+    "schematic",
+    "svg",
+    "compiler",
+    "engineering",
+    "uml"
+  ],
+  "license": "MIT"
 }