@micro-os-plus/architecture-riscv 4.1.0

package/include/micro-os-plus/architecture-riscv/plic-functions.h

@@ -0,0 +1,278 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_PLIC_FUNCTIONS_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_PLIC_FUNCTIONS_H_
+
+// ----------------------------------------------------------------------------
+
+#include <micro-os-plus/architecture-riscv/types.h>
+
+#include <stdbool.h>
+
+// ----------------------------------------------------------------------------
+
+// RISC-V PLIC support functions.
+
+#if defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+namespace riscv
+{
+  namespace plic
+  {
+    // ------------------------------------------------------------------------
+
+    using source_t = riscv_plic_source_t;
+    using priority_t = riscv_plic_priority_t;
+
+    /**
+     * @brief Initialize the interrupt controller.
+     * @par Parameters
+     *  None.
+     * @par Returns
+     *  Nothing.
+     *
+     * @details
+     * Do not assume the controller registers were cleared by reset,
+     * instead set them explicitly to reasonable default values, for
+     * example disable all interrupts and set the threshold to zero.
+     *
+     * @note
+     * This function must be called from each target (hart).
+     */
+    void
+    initialize (void);
+
+    /**
+     * @brief Clear all PLIC priorities.
+     * @par Parameters
+     *  None.
+     * @par Returns
+     *  Nothing.
+     *
+     * @details
+     * Do not assume the controller registers were cleared by reset,
+     * instead set them explicitly to reasonable default values, for
+     * example set all priorities to 0.
+     *
+     * @note
+     * The priorities are unique for the entire PLIC, do not call
+     * this function from each target (hart), since it might
+     * override values set by other targets.
+     */
+    void
+    clear_priorities (void);
+
+    /**
+     * @brief Set the interrupt threshold for the current target (hart).
+     * @param [in] priority The new threshold value.
+     * @return The previous threshold value.
+     *
+     * @details
+     * Each interrupt target (usually a hart) has an associated
+     * priority threshold, held in
+     * a platform-specific memory-mapped register. Only active
+     * interrupts that have a priority strictly greater than the
+     * threshold will cause an interrupt notification to be sent
+     * to the target.
+     *
+     * Different interrupt targets need not support the same set of
+     * priority threshold values. Interrupt target threshold registers
+     * should be WARL fields to allow software to determine the
+     * supported thresholds. A threshold register should always be
+     * able to hold the value zero, in which case, no interrupts
+     * are masked. If implemented, the threshold register will usually
+     * also be able to hold the maximum priority level, in which case
+     * all interrupts are masked.
+     */
+    priority_t
+    threshold (priority_t priority);
+
+    /**
+     * @brief Get the interrupt threshold for the current target (hart).
+     * @par Parameters
+     *  None.
+     * @return The threshold value.
+     */
+    priority_t
+    threshold (void);
+
+    /**
+     * @brief Enable an interrupt for the current target (hart).
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @par Returns
+     *  Nothing.
+     */
+    void
+    enable_interrupt (source_t global_interrupt_id);
+
+    /**
+     * @brief Disable an interrupt for the current target (hart).
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @par Returns
+     *  Nothing.
+     */
+    void
+    disable_interrupt (source_t global_interrupt_id);
+
+    /**
+     * @brief Check if an interrupt is enabled for the current target
+     *  (hart).
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @retval true The interrupt is enabled.
+     * @retval false The interrupt is disabled.
+     */
+    bool
+    is_interrupt_enabled (source_t global_interrupt_id);
+
+    /**
+     * @brief Set the priority of an interrupt.
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @param [in] priority The interrupt priority.
+     * @par Returns
+     *  Nothing.
+     */
+    void
+    priority (source_t global_interrupt_id, priority_t priority);
+
+    /**
+     * @brief Get the priority of an interrupt.
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @return The current priority.
+     */
+    priority_t
+    priority (source_t global_interrupt_id);
+
+    /**
+     * @brief Claim an interrupt for the current target (hart).
+     * @par Parameters
+     *  None.
+     * @return The highest priority pending interrupt or 0, if there
+     *  are no pending interrupts.
+     *
+     * @details
+     * Sometime after a target receives an interrupt notification, it
+     * might decide to service the interrupt. The target sends an
+     * interrupt claim message to the PLIC core, which will usually
+     * be implemented as a non-idempotent memory-mapped I/O control
+     * register read. On receiving a claim message, the PLIC core will
+     * atomically determine the ID of the highest-priority pending
+     * interrupt for the target and then clear down the corresponding
+     * source's IP bit. The PLIC core will then return the ID to the
+     * target. The PLIC core will return an ID of zero, if there were
+     * no pending interrupts for the target when the claim was serviced.
+     *
+     * After the highest-priority pending interrupt is claimed by a
+     * target and the corresponding IP bit is cleared, other
+     * lower-priority pending interrupts might then become visible
+     * to the target, and so the PLIC EIP bit might not be cleared
+     * after a claim. The interrupt handler can check the local
+     * `meip/seip/ueip` bits before exiting the handler, to allow
+     * more efficient service of other interrupts without first
+     * restoring the interrupted context and taking another interrupt
+     * trap.
+     *
+     * It is always legal for a hart to perform a claim even if the EIP
+     * is not set. In particular, a hart could set the threshold value
+     * to maximum to disable interrupt notifications and instead poll
+     * for active interrupts using periodic claim requests, though a
+     * simpler approach to implement polling would be to clear the
+     * external interrupt enable in the corresponding `xie` register
+     * for privilege mode `x`.
+     */
+    source_t
+    claim_interrupt (void);
+
+    /**
+     * @brief Send the completion message to the interrupt target (hart).
+     * @param [in] global_interrupt_id The id of the global interrupt
+     *  source.
+     * @par Returns
+     *  Nothing.
+     *
+     * @details
+     * After a handler has completed service of an interrupt, the
+     * associated gateway must be sent an interrupt completion message,
+     * usually as a write to a non-idempotent memory-mapped I/O control
+     * register. The gateway will only forward additional interrupts to
+     * the PLIC core after receiving the completion message.
+     */
+    void
+    complete_interrupt (source_t global_interrupt_id);
+
+    // ------------------------------------------------------------------------
+  } // namespace plic
+} // namespace riscv
+
+#endif // defined(__cplusplus)
+
+// ============================================================================
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif // defined(__cplusplus)
+
+  // --------------------------------------------------------------------------
+
+  void
+  riscv_plic_initialize (void);
+
+  void
+  riscv_plic_clear_priorities (void);
+
+  static riscv_plic_priority_t
+  riscv_plic_write_threshold (riscv_plic_priority_t priority);
+
+  static riscv_plic_priority_t
+  riscv_plic_read_threshold (void);
+
+  static void
+  riscv_plic_enable_interrupt (riscv_plic_source_t global_interrupt_id);
+
+  static void
+  riscv_plic_disable_interrupt (riscv_plic_source_t global_interrupt_id);
+
+  static bool
+  riscv_plic_is_interrupt_enabled (riscv_plic_source_t global_interrupt_id);
+
+  static void
+  riscv_plic_write_priority (riscv_plic_source_t global_interrupt_id,
+                             riscv_plic_priority_t priority);
+
+  static riscv_plic_priority_t
+  riscv_plic_read_priority (riscv_plic_source_t global_interrupt_id);
+
+  static riscv_plic_source_t
+  riscv_plic_claim_interrupt (void);
+
+  static void
+  riscv_plic_complete_interrupt (riscv_plic_source_t global_interrupt_id);
+
+  // --------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+}
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_PLIC_FUNCTIONS_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/semihosting-inlines.h

@@ -0,0 +1,79 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2015 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_SEMIHOSTING_INLINES_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_SEMIHOSTING_INLINES_H_
+
+// ----------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif // defined(__cplusplus)
+
+  // --------------------------------------------------------------------------
+
+// The hint that differentiates the semihosting call.
+#define RISCV_SEMIHOSTING_CALL_NUMBER 7
+
+  // --------------------------------------------------------------------------
+
+  // Type of each entry in a parameter block.
+  typedef micro_os_plus_architecture_register_t
+      micro_os_plus_semihosting_param_block_t;
+  // Type of result.
+  typedef micro_os_plus_architecture_signed_register_t
+      micro_os_plus_semihosting_response_t;
+
+  // --------------------------------------------------------------------------
+
+  static inline __attribute__ ((always_inline))
+  micro_os_plus_semihosting_response_t
+  micro_os_plus_semihosting_call_host (int reason, void* arg)
+  {
+    micro_os_plus_semihosting_response_t value;
+
+    __asm__ volatile(
+
+        " mv a0, %[rsn] \n"
+        " mv a1, %[arg] \n"
+
+        " .balign 16 \n"
+        // Workaround for RISC-V lack of multiple EBREAKs.
+        " .option push \n"
+        " .option norvc \n"
+        " slli x0, x0, 0x1f \n"
+        " ebreak \n"
+        " srai x0, x0, %[swi] \n"
+        " .option pop \n"
+        
+        " mv %[val], a0"
+
+        : [val] "=r"(value) /* Outputs */
+        : [rsn] "r"(reason), [arg] "r"(arg), [swi] "i"(RISCV_SEMIHOSTING_CALL_NUMBER) /* Inputs */
+        : "a0", "a1", "a2", "a3", "a4", "a5", "memory" /* Clobbers */
+    );
+
+    return value;
+  }
+
+  // --------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+}
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_SEMIHOSTING_INLINES_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/types.h

@@ -0,0 +1,135 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_TYPES_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_TYPES_H_
+
+// ----------------------------------------------------------------------------
+
+#include <stdint.h>
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif // defined(__cplusplus)
+
+#if __riscv_xlen == 32
+  typedef uint32_t riscv_architecture_register_t;
+  typedef int32_t riscv_architecture_signed_register_t;
+#elif __riscv_xlen == 64
+typedef uint64_t riscv_architecture_register_t;
+typedef int64_t riscv_architecture_signed_register_t;
+#endif // __riscv_xlen
+
+  typedef riscv_architecture_register_t micro_os_plus_architecture_register_t;
+  typedef riscv_architecture_signed_register_t
+      micro_os_plus_architecture_signed_register_t;
+
+  typedef void (*riscv_core_trap_handler_ptr_t) (void);
+
+  // --------------------------------------------------------------------------
+
+  typedef enum
+  {
+    riscv_exception_misaligned_fetch = 0,
+    riscv_exception_fault_fetch = 1,
+    riscv_exception_illegal_instruction = 2,
+    riscv_exception_breakpoint = 3,
+    riscv_exception_misaligned_load = 4,
+    riscv_exception_fault_load = 5,
+    riscv_exception_misaligned_store = 6,
+    riscv_exception_fault_store = 7,
+    riscv_exception_user_ecall = 8,
+    riscv_exception_supervisor_ecall = 9,
+    /* 10 */
+    riscv_exception_machine_ecall = 11,
+    riscv_exception_page_fetch = 12,
+    riscv_exception_page_load = 13,
+    /* 14 */
+    riscv_exception_page_store = 15
+  } riscv_exceptions_enum_t;
+
+#define RISCV_EXCEPTIONS_LAST_NUMBER (15u)
+
+  // --------------------------------------------------------------------------
+  // Values from Table 3.6.
+
+  typedef enum
+  {
+    riscv_interrupt_local_user_software = 0,
+    riscv_interrupt_local_supervisor_software = 1,
+    /* 2 reserved */
+    riscv_interrupt_local_machine_software = 3,
+    riscv_interrupt_local_user_timer = 4,
+    riscv_interrupt_local_supervisor_timer = 5,
+    /* 6 reserved */
+    riscv_interrupt_local_machine_timer = 7,
+    riscv_interrupt_local_user_ext = 8,
+    riscv_interrupt_local_supervisor_ext = 9,
+    /* 10 reserved */
+    riscv_interrupt_local_machine_ext = 11,
+    /* 12 reserved */
+    /* 13 reserved */
+    /* 14 reserved */
+    /* 15 reserved */
+  } riscv_interrupts_local_enum_t;
+
+  // --------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+}
+#endif // defined(__cplusplus)
+
+// ============================================================================
+
+#if defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+namespace riscv::architecture
+{
+  // --------------------------------------------------------------------------
+
+  using register_t = riscv_architecture_register_t;
+  using signed_register_t = riscv_architecture_signed_register_t;
+
+  // --------------------------------------------------------------------------
+} // namespace riscv::architecture
+
+namespace riscv::core
+{
+  // --------------------------------------------------------------------------
+
+  using trap_handler_ptr_t = riscv_core_trap_handler_ptr_t;
+
+  // --------------------------------------------------------------------------
+} // namespace riscv::core
+
+namespace micro_os_plus::architecture
+{
+  // --------------------------------------------------------------------------
+
+  using register_t = riscv_architecture_register_t;
+  using signed_register_t = riscv_architecture_signed_register_t;
+
+  // --------------------------------------------------------------------------
+} // namespace micro_os_plus::architecture
+
+// ----------------------------------------------------------------------------
+
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_TYPES_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture.h

@@ -0,0 +1,38 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_H_
+
+// ----------------------------------------------------------------------------
+
+#include <micro-os-plus/architecture-riscv/defines.h>
+
+#include <micro-os-plus/architecture-riscv/types.h>
+#include <micro-os-plus/architecture-riscv/declarations.h>
+
+#include <micro-os-plus/architecture-riscv/instructions.h>
+#include <micro-os-plus/architecture-riscv/instructions-inlines.h>
+
+#include <micro-os-plus/architecture-riscv/csr-functions.h>
+#include <micro-os-plus/architecture-riscv/csr-functions-inlines.h>
+
+#include <micro-os-plus/architecture-riscv/core-functions.h>
+#include <micro-os-plus/architecture-riscv/core-functions-inlines.h>
+
+#include <micro-os-plus/architecture-riscv/semihosting-inlines.h>
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_H_
+
+// ----------------------------------------------------------------------------

package/linker-scripts/README.md

@@ -0,0 +1,7 @@
+# linker-scripts
+
+Generic architecture scripts.
+
+The configuration running from RAM is intended for the QEMU `virt` machine.
+
+May be re-defined at specific device level.