@micro-os-plus/architecture-riscv 4.1.0

package/include/micro-os-plus/architecture-riscv/csr-functions.h

@@ -0,0 +1,241 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
+
+// ----------------------------------------------------------------------------
+
+#include <micro-os-plus/architecture-riscv/types.h>
+
+// ----------------------------------------------------------------------------
+// RISC-V CSR support functions.
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif // defined(__cplusplus)
+
+  // --------------------------------------------------------------------------
+
+#if 0
+  // Not available, due to ISA limitations.
+  // The workaround is to use distinct functions
+  // for each CSR. There are only 4096 of them.
+
+  riscv_architecture_register_t
+  riscv_csr_read (uint32_t reg);
+
+  void
+  riscv_csr_write (uint32_t reg, riscv_architecture_register_t value);
+#endif
+
+  // --------------------------------------------------------------------------
+  // `mstatus`
+
+  /**
+   * Read the `mstatus` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_read_mstatus (void);
+
+  /**
+   * Write the `mstatus` CSR.
+   */
+  static void
+  riscv_csr_write_mstatus (riscv_architecture_register_t value);
+
+  /**
+   * Clear bits in the `mstatus` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_clear_mstatus_bits (riscv_architecture_register_t mask);
+
+  /**
+   * Set bits in the `mstatus` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_set_mstatus_bits (riscv_architecture_register_t mask);
+
+  // --------------------------------------------------------------------------
+  // `mtvec`
+
+  /**
+   * Read the `mtvec` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_read_mtvec (void);
+
+  /**
+   * Write the `mtvec` CSR.
+   */
+  static void
+  riscv_csr_write_mtvec (riscv_architecture_register_t value);
+
+  // --------------------------------------------------------------------------
+  // `mcause`
+
+  /**
+   * Read the `mcause` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_read_mcause (void);
+
+  // --------------------------------------------------------------------------
+  // `mie`
+
+  /**
+   * Read the `mie` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_read_mie (void);
+
+  /**
+   * Write the `mie` CSR.
+   */
+  static void
+  riscv_csr_write_mie (riscv_architecture_register_t value);
+
+  /**
+   * Clear bits in the `mie` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_clear_mie_bits (riscv_architecture_register_t mask);
+
+  /**
+   * Set bits in the `mie` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_set_mie_bits (riscv_architecture_register_t mask);
+
+  // --------------------------------------------------------------------------
+  // `mcycle`
+
+  /**
+   * Read the `mcycle` CSR.
+   */
+#if __riscv_xlen == 64
+  static
+#endif // __riscv_xlen == 64
+      uint64_t
+      riscv_csr_read_mcycle (void);
+
+  static uint32_t
+  riscv_csr_read_mcycle_low (void);
+
+  static uint32_t
+  riscv_csr_read_mcycle_high (void);
+
+  // --------------------------------------------------------------------------
+  // `mhartid`
+
+  /**
+   * Read the `mhartid` CSR.
+   */
+  static riscv_architecture_register_t
+  riscv_csr_read_mhartid (void);
+
+  // --------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+}
+#endif // defined(__cplusplus)
+
+// ============================================================================
+
+#if defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+namespace riscv
+{
+  namespace csr
+  {
+    // ------------------------------------------------------------------------
+    // `mstatus`
+
+    architecture::register_t
+    mstatus (void);
+
+    void
+    mstatus (architecture::register_t value);
+
+    void
+    clear_mstatus_bits (architecture::register_t mask);
+
+    void
+    set_mstatus_bits (architecture::register_t mask);
+
+    // ------------------------------------------------------------------------
+    // `mtvec`
+
+    architecture::register_t
+    mtvec (void);
+
+    void
+    mtvec (architecture::register_t value);
+
+    // ------------------------------------------------------------------------
+    // `mcause`
+
+    architecture::register_t
+    mcause (void);
+
+    // ------------------------------------------------------------------------
+    // `mie`
+
+    architecture::register_t
+    mie (void);
+
+    void
+    mie (architecture::register_t value);
+
+    void
+    clear_mie_bits (architecture::register_t mask);
+
+    void
+    set_mie_bits (architecture::register_t mask);
+
+    // ------------------------------------------------------------------------
+    // `mcycle`
+
+    /**
+     * Read the mcycle counter.
+     */
+    uint64_t
+    mcycle (void);
+
+    uint32_t
+    mcycle_low (void);
+
+    uint32_t
+    mcycle_high (void);
+
+    // ------------------------------------------------------------------------
+    // `mhartid`
+
+    architecture::register_t
+    mhartid (void);
+
+    // ------------------------------------------------------------------------
+  } // namespace csr
+} // namespace riscv
+
+// ----------------------------------------------------------------------------
+
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/declarations.h

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DECLARATIONS_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DECLARATIONS_H_
+
+// ----------------------------------------------------------------------------
+
+#include <micro-os-plus/architecture-riscv/types.h>
+
+#include <stdint.h>
+
+// ----------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+namespace riscv
+{
+  namespace core
+  {
+    // ------------------------------------------------------------------------
+
+    extern riscv_core_trap_handler_ptr_t local_interrupt_handlers[];
+    extern riscv_core_trap_handler_ptr_t global_interrupt_handlers[];
+
+    // ------------------------------------------------------------------------
+  } // namespace core
+
+  namespace architecture
+  {
+    // ------------------------------------------------------------------------
+
+    // TODO: add C++ declarations here.
+
+    // ------------------------------------------------------------------------
+  } // namespace architecture
+} // namespace riscv
+
+// ----------------------------------------------------------------------------
+
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DECLARATIONS_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/defines.h

@@ -0,0 +1,185 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
+
+// ----------------------------------------------------------------------------
+
+#define MICRO_OS_PLUS_INTEGER_STARTUP_STACK_FILL_MAGIC (0xEFBEADDE)
+
+#if 0
+// TODO: check and possibly prefix them.
+
+// ----------------------------------------------------------------------------
+// Definitions from SiFive bsp/env/encoding.h.
+
+#define DCSR_XDEBUGVER (3U << 30)
+#define DCSR_NDRESET (1 << 29)
+#define DCSR_FULLRESET (1 << 28)
+#define DCSR_EBREAKM (1 << 15)
+#define DCSR_EBREAKH (1 << 14)
+#define DCSR_EBREAKS (1 << 13)
+#define DCSR_EBREAKU (1 << 12)
+#define DCSR_STOPCYCLE (1 << 10)
+#define DCSR_STOPTIME (1 << 9)
+#define DCSR_CAUSE (7 << 6)
+#define DCSR_DEBUGINT (1 << 5)
+#define DCSR_HALT (1 << 3)
+#define DCSR_STEP (1 << 2)
+#define DCSR_PRV (3 << 0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))
+
+#define MCONTROL_SELECT (1 << 19)
+#define MCONTROL_TIMING (1 << 18)
+#define MCONTROL_ACTION (0x3f << 12)
+#define MCONTROL_CHAIN (1 << 11)
+#define MCONTROL_MATCH (0xf << 7)
+#define MCONTROL_M (1 << 6)
+#define MCONTROL_H (1 << 5)
+#define MCONTROL_S (1 << 4)
+#define MCONTROL_U (1 << 3)
+#define MCONTROL_EXECUTE (1 << 2)
+#define MCONTROL_STORE (1 << 1)
+#define MCONTROL_LOAD (1 << 0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+// ----------------------------------------------------------------------------
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#if __riscv_xlen == 32
+#define MSTATUS_SD MSTATUS32_SD
+#define SSTATUS_SD SSTATUS32_SD
+#define RISCV_PGLEVEL_BITS 10
+#elif __riscv_xlen == 64
+#define MSTATUS_SD MSTATUS64_SD
+#define SSTATUS_SD SSTATUS64_SD
+#define RISCV_PGLEVEL_BITS 9
+#endif // __riscv_xlen
+
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+// End of SiFive definitions.
+// ----------------------------------------------------------------------------
+#endif
+
+#define RISCV_CSR_MSTATUS_UIE 0x00000001ul
+#define RISCV_CSR_MSTATUS_SIE 0x00000002ul
+#define RISCV_CSR_MSTATUS_MIE 0x00000008ul
+#define RISCV_CSR_MSTATUS_UPIE 0x00000010ul
+#define RISCV_CSR_MSTATUS_SPIE 0x00000020ul
+#define RISCV_CSR_MSTATUS_MPIE 0x00000080ul
+#define RISCV_CSR_MSTATUS_SPP 0x00000100ul
+#define RISCV_CSR_MSTATUS_MPP 0x00001800ul
+#define RISCV_CSR_MSTATUS_FS 0x00006000ul
+#define RISCV_CSR_MSTATUS_XS 0x00018000ul
+#define RISCV_CSR_MSTATUS_MPRV 0x00020000ul
+#define RISCV_CSR_MSTATUS_PUM 0x00040000ul
+#define RISCV_CSR_MSTATUS_MXR 0x00080000ul
+#define RISCV_CSR_MSTATUS_VM 0x1F000000ul
+#define RISCV_CSR_MSTATUS32_SD 0x80000000ul
+#define RISCV_CSR_MSTATUS64_SD 0x8000000000000000ul
+
+#define RISCV_CSR_SSTATUS_UIE 0x00000001ul
+#define RISCV_CSR_SSTATUS_SIE 0x00000002ul
+#define RISCV_CSR_SSTATUS_UPIE 0x00000010ul
+#define RISCV_CSR_SSTATUS_SPIE 0x00000020ul
+#define RISCV_CSR_SSTATUS_SPP 0x00000100ul
+#define RISCV_CSR_SSTATUS_FS 0x00006000ul
+#define RISCV_CSR_SSTATUS_XS 0x00018000ul
+#define RISCV_CSR_SSTATUS_PUM 0x00040000ul
+#define RISCV_CSR_SSTATUS32_SD 0x80000000ul
+#define RISCV_CSR_SSTATUS64_SD 0x8000000000000000ul
+
+#define RISCV_CSR_MIP_SSIP (1ul << riscv_interrupt_local_supervisor_software)
+#define RISCV_CSR_MIP_MSIP (1ul << riscv_interrupt_local_machine_software)
+#define RISCV_CSR_MIP_STIP (1ul << riscv_interrupt_local_supervisor_timer)
+#define RISCV_CSR_MIP_MTIP (1ul << riscv_interrupt_local_machine_timer)
+#define RISCV_CSR_MIP_SEIP (1ul << riscv_interrupt_local_supervisor_ext)
+#define RISCV_CSR_MIP_MEIP (1ul << riscv_interrupt_local_machine_ext)
+
+// ----------------------------------------------------------------------------
+
+#if __riscv_xlen == 32
+#define RISCV_CSR_MCAUSE_INTERRUPT (1ul << 31ul)
+#define RISCV_CSR_MCAUSE_CAUSE (0x7FFFFFFFul)
+#elif __riscv_xlen == 64
+#define RISCV_CSR_MCAUSE_INTERRUPT (1ul << 63ul)
+#define RISCV_CSR_MCAUSE_CAUSE (0x7FFFFFFFFFFFFFFFul)
+#else
+#error "Unsupported __riscv_xlen"
+#endif // __riscv_xlen
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
+
+// ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/device-functions-inlines.h

@@ -0,0 +1,235 @@
+/*
+ * This file is part of the µOS++ distribution.
+ *   (https://github.com/micro-os-plus/)
+ * Copyright (c) 2017 Liviu Ionescu.
+ *
+ * Permission to use, copy, modify, and/or distribute this software
+ * for any purpose is hereby granted, under the terms of the MIT license.
+ *
+ * If a copy of the license was not distributed with this file, it can
+ * be obtained from https://opensource.org/licenses/MIT/.
+ */
+
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEVICE_FUNCTIONS_INLINES_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEVICE_FUNCTIONS_INLINES_H_
+
+// ----------------------------------------------------------------------------
+
+#include <stdint.h>
+
+// ----------------------------------------------------------------------------
+
+// Inline implementations for the common device support functions.
+// Not included by architecture files, but by device files.
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif // defined(__cplusplus)
+
+  // --------------------------------------------------------------------------
+
+#if __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) uint64_t
+  riscv_device_read_mtime (void)
+  {
+    return *(volatile uint64_t*)(RISCV_MMIO_MTIME_ADDRESS);
+  }
+
+#endif // __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) uint32_t
+  riscv_device_read_mtime_low (void)
+  {
+    return *(volatile uint32_t*)(RISCV_MMIO_MTIME_ADDRESS);
+  }
+
+  static inline __attribute__ ((always_inline)) uint32_t
+  riscv_device_read_mtime_high (void)
+  {
+    return *(volatile uint32_t*)(RISCV_MMIO_MTIME_ADDRESS + 4);
+  }
+
+#if __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtime (uint64_t value)
+  {
+    *(volatile uint64_t*)(RISCV_MMIO_MTIME_ADDRESS) = value;
+  }
+
+#endif // __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtime_low (uint32_t value)
+  {
+    *(volatile uint32_t*)(RISCV_MMIO_MTIME_ADDRESS) = value;
+  }
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtime_high (uint32_t value)
+  {
+    *(volatile uint32_t*)(RISCV_MMIO_MTIME_ADDRESS + 4) = value;
+  }
+
+  // --------------------------------------------------------------------------
+
+  static inline __attribute__ ((always_inline)) uint64_t
+  riscv_device_read_mtimecmp (void)
+  {
+    // On RV32 the compiler generates two word accesses.
+    return *(uint64_t*)(RISCV_MMIO_MTIMECMP_ADDRESS);
+  }
+
+  static inline __attribute__ ((always_inline)) uint32_t
+  riscv_device_read_mtimecmp_low (void)
+  {
+    return *(uint32_t*)(RISCV_MMIO_MTIMECMP_ADDRESS);
+  }
+
+  static inline __attribute__ ((always_inline)) uint32_t
+  riscv_device_read_mtimecmp_high (void)
+  {
+    return *(uint32_t*)(RISCV_MMIO_MTIMECMP_ADDRESS + 4);
+  }
+
+#if __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtimecmp (uint64_t value)
+  {
+    *(uint64_t*)(RISCV_MMIO_MTIMECMP_ADDRESS) = value;
+  }
+
+#endif // __riscv_xlen == 64
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtimecmp_low (uint32_t value)
+  {
+    *(uint32_t*)(RISCV_MMIO_MTIMECMP_ADDRESS) = value;
+  }
+
+  static inline __attribute__ ((always_inline)) void
+  riscv_device_write_mtimecmp_high (uint32_t value)
+  {
+    *(uint32_t*)(RISCV_MMIO_MTIMECMP_ADDRESS + 4) = value;
+  }
+
+  // --------------------------------------------------------------------------
+
+#if defined(__cplusplus)
+}
+#endif // defined(__cplusplus)
+
+// ============================================================================
+
+#if defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+namespace riscv
+{
+  namespace device
+  {
+    // ------------------------------------------------------------------------
+
+#if __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) uint64_t
+    mtime (void)
+    {
+      return riscv_device_read_mtime ();
+    }
+
+#endif // __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) uint32_t
+    mtime_low (void)
+    {
+      return riscv_device_read_mtime_low ();
+    }
+
+    inline __attribute__ ((always_inline)) uint32_t
+    mtime_high (void)
+    {
+      return riscv_device_read_mtime_high ();
+    }
+
+#if __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) void
+    mtime (uint64_t value)
+    {
+      riscv_device_write_mtime (value);
+    }
+
+#endif // __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) void
+    mtime_low (uint32_t value)
+    {
+      riscv_device_write_mtime_low (value);
+    }
+
+    inline __attribute__ ((always_inline)) void
+    mtime_high (uint32_t value)
+    {
+      riscv_device_write_mtime_high (value);
+    }
+
+    // ------------------------------------------------------------------------
+
+    inline __attribute__ ((always_inline)) uint64_t
+    mtimecmp (void)
+    {
+      return riscv_device_read_mtimecmp ();
+    }
+
+    inline __attribute__ ((always_inline)) uint32_t
+    mtimecmp_low (void)
+    {
+      return riscv_device_read_mtimecmp_low ();
+    }
+
+    inline __attribute__ ((always_inline)) uint32_t
+    mtimecmp_high (void)
+    {
+      return riscv_device_read_mtimecmp_high ();
+    }
+
+#if __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) void
+    mtimecmp (uint64_t value)
+    {
+      riscv_device_write_mtimecmp (value);
+    }
+
+#endif // __riscv_xlen == 64
+
+    inline __attribute__ ((always_inline)) void
+    mtimecmp_low (uint32_t value)
+    {
+      riscv_device_write_mtimecmp_low (value);
+    }
+
+    inline __attribute__ ((always_inline)) void
+    mtimecmp_high (uint32_t value)
+    {
+      riscv_device_write_mtimecmp_high (value);
+    }
+
+    // ------------------------------------------------------------------------
+  } // namespace device
+} // namespace riscv
+
+// ----------------------------------------------------------------------------
+
+#endif // defined(__cplusplus)
+
+// ----------------------------------------------------------------------------
+
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEVICE_FUNCTIONS_INLINES_H_
+
+// ----------------------------------------------------------------------------