@fluffylabs/anan-as 1.2.0-e8a5af8 → 1.2.0-ef04361

package/dist/build/js/assembly/instructions/bit.js

@@ -0,0 +1,53 @@
+import { portable } from "../portable";
+import { ok } from "./outcome";
+import { reg, u8SignExtend, u16SignExtend } from "./utils";
+// COUNT_SET_BITS_64
+export const count_set_bits_64 = (r, args, regs) => {
+    regs[reg(args.b)] = portable.popcnt_u64(regs[reg(args.a)]);
+    return ok(r);
+};
+// COUNT_SET_BITS_32
+export const count_set_bits_32 = (r, args, regs) => {
+    regs[reg(args.b)] = u64(portable.popcnt_u32(u32(regs[reg(args.a)])));
+    return ok(r);
+};
+// LEADING_ZERO_BITS_64
+export const leading_zero_bits_64 = (r, args, regs) => {
+    regs[reg(args.b)] = portable.clz_u64(regs[reg(args.a)]);
+    return ok(r);
+};
+// LEADING_ZERO_BITS_32
+export const leading_zero_bits_32 = (r, args, regs) => {
+    regs[reg(args.b)] = u64(portable.clz_u32(u32(regs[reg(args.a)])));
+    return ok(r);
+};
+// TRAILING_ZERO_BITS_64
+export const trailing_zero_bits_64 = (r, args, regs) => {
+    regs[reg(args.b)] = portable.ctz_u64(regs[reg(args.a)]);
+    return ok(r);
+};
+// TRAILING_ZERO_BITS_32
+export const trailing_zero_bits_32 = (r, args, regs) => {
+    regs[reg(args.b)] = u64(portable.ctz_u32(u32(regs[reg(args.a)])));
+    return ok(r);
+};
+// SIGN_EXTEND_8
+export const sign_extend_8 = (r, args, regs) => {
+    regs[reg(args.b)] = u8SignExtend(u8(regs[reg(args.a)]));
+    return ok(r);
+};
+// SIGN_EXTEND_16
+export const sign_extend_16 = (r, args, regs) => {
+    regs[reg(args.b)] = u16SignExtend(u16(regs[reg(args.a)]));
+    return ok(r);
+};
+// ZERO_EXTEND_16
+export const zero_extend_16 = (r, args, regs) => {
+    regs[reg(args.b)] = u64(u16(regs[reg(args.a)]));
+    return ok(r);
+};
+// REVERSE_BYTES
+export const reverse_bytes = (r, args, regs) => {
+    regs[reg(args.b)] = portable.bswap_u64(regs[reg(args.a)]);
+    return ok(r);
+};

package/dist/build/js/assembly/instructions/branch.d.ts

@@ -0,0 +1,17 @@
+import { InstructionRun } from "./outcome";
+export declare const branch_eq_imm: InstructionRun;
+export declare const branch_ne_imm: InstructionRun;
+export declare const branch_lt_u_imm: InstructionRun;
+export declare const branch_le_u_imm: InstructionRun;
+export declare const branch_ge_u_imm: InstructionRun;
+export declare const branch_gt_u_imm: InstructionRun;
+export declare const branch_lt_s_imm: InstructionRun;
+export declare const branch_le_s_imm: InstructionRun;
+export declare const branch_ge_s_imm: InstructionRun;
+export declare const branch_gt_s_imm: InstructionRun;
+export declare const branch_eq: InstructionRun;
+export declare const branch_ne: InstructionRun;
+export declare const branch_lt_u: InstructionRun;
+export declare const branch_lt_s: InstructionRun;
+export declare const branch_ge_u: InstructionRun;
+export declare const branch_ge_s: InstructionRun;

package/dist/build/js/assembly/instructions/branch.js

@@ -0,0 +1,120 @@
+import { ok, staticJump } from "./outcome";
+import { reg, u32SignExtend } from "./utils";
+// BRANCH_EQ_IMM
+export const branch_eq_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] === b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_NE_IMM
+export const branch_ne_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] !== b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LT_U_IMM
+export const branch_lt_u_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] < b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LE_U_IMM
+export const branch_le_u_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] <= b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GE_U_IMM
+export const branch_ge_u_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] >= b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GT_U_IMM
+export const branch_gt_u_imm = (r, args, registers) => {
+    const b = u64(u32SignExtend(args.b));
+    if (registers[reg(args.a)] > b) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LT_S_IMM
+export const branch_lt_s_imm = (r, args, registers) => {
+    if (i64(registers[reg(args.a)]) < i64(u32SignExtend(args.b))) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LE_S_IMM
+export const branch_le_s_imm = (r, args, registers) => {
+    if (i64(registers[reg(args.a)]) <= i64(u32SignExtend(args.b))) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GE_S_IMM
+export const branch_ge_s_imm = (r, args, registers) => {
+    if (i64(registers[reg(args.a)]) >= i64(u32SignExtend(args.b))) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GT_S_IMM
+export const branch_gt_s_imm = (r, args, registers) => {
+    if (i64(registers[reg(args.a)]) > i64(u32SignExtend(args.b))) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_EQ
+export const branch_eq = (r, args, registers) => {
+    if (registers[reg(args.a)] === registers[reg(args.b)]) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_NE
+export const branch_ne = (r, args, registers) => {
+    if (registers[reg(args.a)] !== registers[reg(args.b)]) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LT_U
+export const branch_lt_u = (r, args, registers) => {
+    if (registers[reg(args.b)] < registers[reg(args.a)]) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_LT_S
+export const branch_lt_s = (r, args, registers) => {
+    if (i64(registers[reg(args.b)]) < i64(registers[reg(args.a)])) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GE_U
+export const branch_ge_u = (r, args, registers) => {
+    if (registers[reg(args.b)] >= registers[reg(args.a)]) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};
+// BRANCH_GE_S
+export const branch_ge_s = (r, args, registers) => {
+    if (i64(registers[reg(args.b)]) >= i64(registers[reg(args.a)])) {
+        return staticJump(r, args.c);
+    }
+    return ok(r);
+};

package/dist/build/js/assembly/instructions/jump.d.ts

@@ -0,0 +1,5 @@
+import { InstructionRun } from "./outcome";
+export declare const jump: InstructionRun;
+export declare const jump_ind: InstructionRun;
+export declare const load_imm_jump: InstructionRun;
+export declare const load_imm_jump_ind: InstructionRun;

package/dist/build/js/assembly/instructions/jump.js

@@ -0,0 +1,21 @@
+import { portable } from "../portable";
+import { dJump, staticJump } from "./outcome";
+import { reg, u32SignExtend } from "./utils";
+// JUMP
+export const jump = (r, args) => staticJump(r, args.a);
+// JUMP_IND
+export const jump_ind = (r, args, registers) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.b)));
+    return dJump(r, address);
+};
+// LOAD_IMM_JUMP
+export const load_imm_jump = (r, args, registers) => {
+    registers[reg(args.a)] = u32SignExtend(args.b);
+    return staticJump(r, args.c);
+};
+// LOAD_IMM_JUMP_IND
+export const load_imm_jump_ind = (r, args, registers) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.d)));
+    registers[reg(args.b)] = u32SignExtend(args.c);
+    return dJump(r, address);
+};

package/dist/build/js/assembly/instructions/load.d.ts

@@ -0,0 +1,17 @@
+import { InstructionRun } from "./outcome";
+export declare const load_imm_64: InstructionRun;
+export declare const load_imm: InstructionRun;
+export declare const load_u8: InstructionRun;
+export declare const load_i8: InstructionRun;
+export declare const load_u16: InstructionRun;
+export declare const load_i16: InstructionRun;
+export declare const load_u32: InstructionRun;
+export declare const load_i32: InstructionRun;
+export declare const load_u64: InstructionRun;
+export declare const load_ind_u8: InstructionRun;
+export declare const load_ind_i8: InstructionRun;
+export declare const load_ind_u16: InstructionRun;
+export declare const load_ind_i16: InstructionRun;
+export declare const load_ind_u32: InstructionRun;
+export declare const load_ind_i32: InstructionRun;
+export declare const load_ind_u64: InstructionRun;

package/dist/build/js/assembly/instructions/load.js

@@ -0,0 +1,134 @@
+import { MaybePageFault } from "../memory";
+import { portable } from "../portable";
+import { ok, okOrFault } from "./outcome";
+import { reg, u32SignExtend } from "./utils";
+const faultRes = new MaybePageFault();
+// LOAD_IMM_64
+export const load_imm_64 = (r, args, registers) => {
+    registers[reg(args.a)] = portable.u64_add(u64(args.b), u64(args.c) << u64(32));
+    return ok(r);
+};
+// LOAD_IMM
+export const load_imm = (r, args, registers) => {
+    registers[reg(args.a)] = u32SignExtend(args.b);
+    return ok(r);
+};
+// LOAD_U8
+export const load_u8 = (r, args, registers, memory) => {
+    const result = memory.getU8(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_I8
+export const load_i8 = (r, args, registers, memory) => {
+    const result = memory.getI8(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_U16
+export const load_u16 = (r, args, registers, memory) => {
+    const result = memory.getU16(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_I16
+export const load_i16 = (r, args, registers, memory) => {
+    const result = memory.getI16(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_U32
+export const load_u32 = (r, args, registers, memory) => {
+    const result = memory.getU32(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_I32
+export const load_i32 = (r, args, registers, memory) => {
+    const result = memory.getI32(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_U64
+export const load_u64 = (r, args, registers, memory) => {
+    const result = memory.getU64(faultRes, args.b);
+    if (!faultRes.isFault) {
+        registers[reg(args.a)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_U8
+export const load_ind_u8 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getU8(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_I8
+export const load_ind_i8 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getI8(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_U16
+export const load_ind_u16 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getU16(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_I16
+export const load_ind_i16 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getI16(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_U32
+export const load_ind_u32 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getU32(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_I32
+export const load_ind_i32 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getI32(faultRes, address);
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};
+// LOAD_IND_U64
+export const load_ind_u64 = (r, args, registers, memory) => {
+    const address = u32(portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c)));
+    const result = memory.getU64(faultRes, u32(address));
+    if (!faultRes.isFault) {
+        registers[reg(args.b)] = result;
+    }
+    return okOrFault(r, faultRes);
+};

package/dist/build/js/assembly/instructions/logic.d.ts

@@ -0,0 +1,10 @@
+import { InstructionRun } from "./outcome";
+export declare const and_imm: InstructionRun;
+export declare const xor_imm: InstructionRun;
+export declare const or_imm: InstructionRun;
+export declare const and: InstructionRun;
+export declare const xor: InstructionRun;
+export declare const or: InstructionRun;
+export declare const and_inv: InstructionRun;
+export declare const or_inv: InstructionRun;
+export declare const xnor: InstructionRun;

package/dist/build/js/assembly/instructions/logic.js

@@ -0,0 +1,47 @@
+import { ok } from "./outcome";
+import { reg, u32SignExtend } from "./utils";
+// AND_IMM
+export const and_imm = (r, args, registers) => {
+    registers[reg(args.b)] = registers[reg(args.a)] & u32SignExtend(args.c);
+    return ok(r);
+};
+// XOR_IMM
+export const xor_imm = (r, args, registers) => {
+    registers[reg(args.b)] = registers[reg(args.a)] ^ u32SignExtend(args.c);
+    return ok(r);
+};
+// OR_IMM
+export const or_imm = (r, args, registers) => {
+    registers[reg(args.b)] = registers[reg(args.a)] | u32SignExtend(args.c);
+    return ok(r);
+};
+// AND
+export const and = (r, args, registers) => {
+    registers[reg(args.c)] = registers[reg(args.b)] & registers[reg(args.a)];
+    return ok(r);
+};
+// XOR
+export const xor = (r, args, registers) => {
+    registers[reg(args.c)] = registers[reg(args.b)] ^ registers[reg(args.a)];
+    return ok(r);
+};
+// OR
+export const or = (r, args, registers) => {
+    registers[reg(args.c)] = registers[reg(args.b)] | registers[reg(args.a)];
+    return ok(r);
+};
+// AND_INV
+export const and_inv = (r, args, registers) => {
+    registers[reg(args.c)] = registers[reg(args.b)] & ~registers[reg(args.a)];
+    return ok(r);
+};
+// OR_INV
+export const or_inv = (r, args, registers) => {
+    registers[reg(args.c)] = u64(registers[reg(args.b)] | ~registers[reg(args.a)]);
+    return ok(r);
+};
+// XNOR
+export const xnor = (r, args, registers) => {
+    registers[reg(args.c)] = u64(~(registers[reg(args.b)] ^ registers[reg(args.a)]));
+    return ok(r);
+};

package/dist/build/js/assembly/instructions/math.d.ts

@@ -0,0 +1,28 @@
+import { InstructionRun } from "./outcome";
+export declare const add_imm_32: InstructionRun;
+export declare const mul_imm_32: InstructionRun;
+export declare const neg_add_imm_32: InstructionRun;
+export declare const add_imm: InstructionRun;
+export declare const mul_imm: InstructionRun;
+export declare const neg_add_imm: InstructionRun;
+export declare const add_32: InstructionRun;
+export declare const sub_32: InstructionRun;
+export declare const mul_32: InstructionRun;
+export declare const div_u_32: InstructionRun;
+export declare const div_s_32: InstructionRun;
+export declare const rem_u_32: InstructionRun;
+export declare const rem_s_32: InstructionRun;
+export declare const add_64: InstructionRun;
+export declare const sub: InstructionRun;
+export declare const mul: InstructionRun;
+export declare const div_u: InstructionRun;
+export declare const div_s: InstructionRun;
+export declare const rem_u: InstructionRun;
+export declare const rem_s: InstructionRun;
+export declare const mul_upper_s_s: InstructionRun;
+export declare const mul_upper_u_u: InstructionRun;
+export declare const mul_upper_s_u: InstructionRun;
+export declare const max: InstructionRun;
+export declare const max_u: InstructionRun;
+export declare const min: InstructionRun;
+export declare const min_u: InstructionRun;

package/dist/build/js/assembly/instructions/math.js

@@ -0,0 +1,225 @@
+import { portable } from "../portable";
+import { ok } from "./outcome";
+import { mulUpperSigned, mulUpperSignedUnsigned, mulUpperUnsigned, reg, u32SignExtend } from "./utils";
+// ADD_IMM_32
+export const add_imm_32 = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const c = u32SignExtend(args.c);
+    registers[reg(args.b)] = u32SignExtend(u32(portable.u64_add(a, c)));
+    return ok(r);
+};
+// MUL_IMM_32
+export const mul_imm_32 = (r, args, registers) => {
+    registers[reg(args.b)] = u32SignExtend(u32(portable.u64_mul(registers[reg(args.a)], u64(args.c))));
+    return ok(r);
+};
+// NEG_ADD_IMM_32
+export const neg_add_imm_32 = (r, args, registers) => {
+    const sum = portable.u64_sub(u64(args.c) | u64(4294967296), registers[reg(args.a)]);
+    registers[reg(args.b)] = u32SignExtend(u32(sum));
+    return ok(r);
+};
+// ADD_IMM
+export const add_imm = (r, args, registers) => {
+    const sum = portable.u64_add(registers[reg(args.a)], u32SignExtend(args.c));
+    registers[reg(args.b)] = sum;
+    return ok(r);
+};
+// MUL_IMM
+export const mul_imm = (r, args, registers) => {
+    registers[reg(args.b)] = portable.u64_mul(registers[reg(args.a)], u32SignExtend(args.c));
+    return ok(r);
+};
+// NEG_ADD_IMM
+export const neg_add_imm = (r, args, registers) => {
+    const sum = portable.u64_sub(u32SignExtend(args.c), registers[reg(args.a)]);
+    registers[reg(args.b)] = sum;
+    return ok(r);
+};
+// ADD_32
+export const add_32 = (r, args, registers) => {
+    const a = u32(registers[reg(args.a)]);
+    const b = u32(registers[reg(args.b)]);
+    registers[reg(args.c)] = u32SignExtend(a + b);
+    return ok(r);
+};
+// SUB_32
+export const sub_32 = (r, args, registers) => {
+    const a = registers[reg(args.b)];
+    const b = u64(4294967296 - u32(registers[reg(args.a)]));
+    registers[reg(args.c)] = u32SignExtend(u32(portable.u64_add(a, b)));
+    return ok(r);
+};
+// MUL_32
+export const mul_32 = (r, args, registers) => {
+    registers[reg(args.c)] = u32SignExtend(u32(portable.u64_mul(registers[reg(args.a)], registers[reg(args.b)])));
+    return ok(r);
+};
+// DIV_U_32
+export const div_u_32 = (r, args, registers) => {
+    const a = u32(registers[reg(args.a)]);
+    if (a === 0) {
+        registers[reg(args.c)] = u64.MAX_VALUE;
+    }
+    else {
+        const b = u32(registers[reg(args.b)]);
+        registers[reg(args.c)] = u32SignExtend(b / a);
+    }
+    return ok(r);
+};
+// DIV_S_32
+export const div_s_32 = (r, args, registers) => {
+    const b = i64(u32SignExtend(u32(registers[reg(args.b)])));
+    const a = i64(u32SignExtend(u32(registers[reg(args.a)])));
+    if (a === i64(0)) {
+        registers[reg(args.c)] = u64.MAX_VALUE;
+    }
+    else if (a === i64(-1) && b === i64(i32.MIN_VALUE)) {
+        registers[reg(args.c)] = u64(b);
+    }
+    else {
+        registers[reg(args.c)] = u64(b / a);
+    }
+    return ok(r);
+};
+// REM_U_32
+export const rem_u_32 = (r, args, registers) => {
+    const a = u32(registers[reg(args.a)]);
+    const b = u32(registers[reg(args.b)]);
+    if (a === 0) {
+        registers[reg(args.c)] = u32SignExtend(b);
+    }
+    else {
+        registers[reg(args.c)] = u32SignExtend(b % a);
+    }
+    return ok(r);
+};
+// REM_S_32
+export const rem_s_32 = (r, args, registers) => {
+    const b = i32(registers[reg(args.b)]);
+    const a = i32(registers[reg(args.a)]);
+    if (a === 0) {
+        registers[reg(args.c)] = u64(i64(b));
+    }
+    else if (a === -1 && b === i32.MIN_VALUE) {
+        registers[reg(args.c)] = u64(0);
+    }
+    else {
+        registers[reg(args.c)] = u64(i64(b) % i64(a));
+    }
+    return ok(r);
+};
+// ADD_64
+export const add_64 = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const b = registers[reg(args.b)];
+    registers[reg(args.c)] = portable.u64_add(a, b);
+    return ok(r);
+};
+// SUB
+export const sub = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const b = registers[reg(args.b)];
+    registers[reg(args.c)] = portable.u64_sub(b, a);
+    return ok(r);
+};
+// MUL
+export const mul = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const b = registers[reg(args.b)];
+    registers[reg(args.c)] = portable.u64_mul(a, b);
+    return ok(r);
+};
+// DIV_U
+export const div_u = (r, args, registers) => {
+    if (registers[reg(args.a)] === u64(0)) {
+        registers[reg(args.c)] = u64.MAX_VALUE;
+    }
+    else {
+        registers[reg(args.c)] = registers[reg(args.b)] / registers[reg(args.a)];
+    }
+    return ok(r);
+};
+// DIV_S
+export const div_s = (r, args, registers) => {
+    const b = i64(registers[reg(args.b)]);
+    const a = i64(registers[reg(args.a)]);
+    if (a === i64(0)) {
+        registers[reg(args.c)] = u64.MAX_VALUE;
+    }
+    else if (a === i64(-1) && b === i64.MIN_VALUE) {
+        registers[reg(args.c)] = u64(b);
+    }
+    else {
+        registers[reg(args.c)] = u64(b / a);
+    }
+    return ok(r);
+};
+// REM_U
+export const rem_u = (r, args, registers) => {
+    if (registers[reg(args.a)] === u64(0)) {
+        registers[reg(args.c)] = registers[reg(args.b)];
+    }
+    else {
+        registers[reg(args.c)] = registers[reg(args.b)] % registers[reg(args.a)];
+    }
+    return ok(r);
+};
+// REM_S
+export const rem_s = (r, args, registers) => {
+    const b = i64(registers[reg(args.b)]);
+    const a = i64(registers[reg(args.a)]);
+    if (a === i64(0)) {
+        registers[reg(args.c)] = u64(b);
+    }
+    else if (a === i64(-1) && b === i64.MIN_VALUE) {
+        registers[reg(args.c)] = u64(0);
+    }
+    else {
+        registers[reg(args.c)] = u64(b % a);
+    }
+    return ok(r);
+};
+// MUL_UPPER_S_S
+export const mul_upper_s_s = (r, args, registers) => {
+    registers[reg(args.c)] = mulUpperSigned(i64(registers[reg(args.b)]), i64(registers[reg(args.a)]));
+    return ok(r);
+};
+// MUL_UPPER_U_U
+export const mul_upper_u_u = (r, args, registers) => {
+    registers[reg(args.c)] = mulUpperUnsigned(registers[reg(args.b)], registers[reg(args.a)]);
+    return ok(r);
+};
+// MUL_UPPER_S_U
+export const mul_upper_s_u = (r, args, registers) => {
+    registers[reg(args.c)] = mulUpperSignedUnsigned(i64(registers[reg(args.b)]), registers[reg(args.a)]);
+    return ok(r);
+};
+// MAX
+export const max = (r, args, registers) => {
+    const a = i64(registers[reg(args.a)]);
+    const b = i64(registers[reg(args.b)]);
+    registers[reg(args.c)] = u64(a < b ? b : a);
+    return ok(r);
+};
+// MAX_U
+export const max_u = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const b = registers[reg(args.b)];
+    registers[reg(args.c)] = a < b ? b : a;
+    return ok(r);
+};
+// MIN
+export const min = (r, args, registers) => {
+    const a = i64(registers[reg(args.a)]);
+    const b = i64(registers[reg(args.b)]);
+    registers[reg(args.c)] = u64(a > b ? b : a);
+    return ok(r);
+};
+// MIN_U
+export const min_u = (r, args, registers) => {
+    const a = registers[reg(args.a)];
+    const b = registers[reg(args.b)];
+    registers[reg(args.c)] = a > b ? b : a;
+    return ok(r);
+};

package/dist/build/js/assembly/instructions/misc.d.ts

@@ -0,0 +1,6 @@
+import { InstructionRun } from "./outcome";
+export declare const INVALID: InstructionRun;
+export declare const trap: InstructionRun;
+export declare const fallthrough: InstructionRun;
+export declare const ecalli: InstructionRun;
+export declare const sbrk: InstructionRun;