@fluffylabs/anan-as 1.2.0-e8a5af8 → 1.2.0-ef04361

package/dist/build/js/assembly/instructions-exe.js

@@ -0,0 +1,245 @@
+import * as bit from "./instructions/bit";
+import * as branch from "./instructions/branch";
+import * as jump from "./instructions/jump";
+import * as load from "./instructions/load";
+import * as logic from "./instructions/logic";
+import * as math from "./instructions/math";
+import { ecalli, fallthrough, INVALID, sbrk, trap } from "./instructions/misc";
+import * as mov from "./instructions/mov";
+import * as rot from "./instructions/rot";
+import * as set from "./instructions/set";
+import * as shift from "./instructions/shift";
+import * as store from "./instructions/store";
+export const RUN = [
+    /* 000 */ trap,
+    /* 001 */ fallthrough,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 010 */ ecalli,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 020 */ load.load_imm_64,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 030 */ store.store_imm_u8,
+    /* 031 */ store.store_imm_u16,
+    /* 032 */ store.store_imm_u32,
+    /* 033 */ store.store_imm_u64,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 040 */ jump.jump,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 050 */ jump.jump_ind,
+    /* 051 */ load.load_imm,
+    /* 052 */ load.load_u8,
+    /* 053 */ load.load_i8,
+    /* 054 */ load.load_u16,
+    /* 055 */ load.load_i16,
+    /* 056 */ load.load_u32,
+    /* 057 */ load.load_i32,
+    /* 058 */ load.load_u64,
+    /* 059 */ store.store_u8,
+    /* 060 */ store.store_u16,
+    /* 061 */ store.store_u32,
+    /* 062 */ store.store_u64,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 070 */ store.store_imm_ind_u8,
+    /* 071 */ store.store_imm_ind_u16,
+    /* 072 */ store.store_imm_ind_u32,
+    /* 073 */ store.store_imm_ind_u64,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 080 */ jump.load_imm_jump,
+    /* 081 */ branch.branch_eq_imm,
+    /* 082 */ branch.branch_ne_imm,
+    /* 083 */ branch.branch_lt_u_imm,
+    /* 084 */ branch.branch_le_u_imm,
+    /* 085 */ branch.branch_ge_u_imm,
+    /* 086 */ branch.branch_gt_u_imm,
+    /* 087 */ branch.branch_lt_s_imm,
+    /* 088 */ branch.branch_le_s_imm,
+    /* 089 */ branch.branch_ge_s_imm,
+    /* 090 */ branch.branch_gt_s_imm,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 100 */ mov.move_reg,
+    /* 101 */ sbrk,
+    /* 102 */ bit.count_set_bits_64,
+    /* 103 */ bit.count_set_bits_32,
+    /* 104 */ bit.leading_zero_bits_64,
+    /* 105 */ bit.leading_zero_bits_32,
+    /* 106 */ bit.trailing_zero_bits_64,
+    /* 107 */ bit.trailing_zero_bits_32,
+    /* 108 */ bit.sign_extend_8,
+    /* 109 */ bit.sign_extend_16,
+    /* 110 */ bit.zero_extend_16,
+    /* 111 */ bit.reverse_bytes,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 120 */ store.store_ind_u8,
+    /* 121 */ store.store_ind_u16,
+    /* 122 */ store.store_ind_u32,
+    /* 123 */ store.store_ind_u64,
+    /* 124 */ load.load_ind_u8,
+    /* 125 */ load.load_ind_i8,
+    /* 126 */ load.load_ind_u16,
+    /* 127 */ load.load_ind_i16,
+    /* 128 */ load.load_ind_u32,
+    /* 129 */ load.load_ind_i32,
+    /* 130 */ load.load_ind_u64,
+    /* 131 */ math.add_imm_32,
+    /* 132 */ logic.and_imm,
+    /* 133 */ logic.xor_imm,
+    /* 134 */ logic.or_imm,
+    /* 135 */ math.mul_imm_32,
+    /* 136 */ set.set_lt_u_imm,
+    /* 137 */ set.set_lt_s_imm,
+    /* 138 */ shift.shlo_l_imm_32,
+    /* 139 */ shift.shlo_r_imm_32,
+    /* 140 */ shift.shar_r_imm_32,
+    /* 141 */ math.neg_add_imm_32,
+    /* 142 */ set.set_gt_u_imm,
+    /* 143 */ set.set_gt_s_imm,
+    /* 144 */ shift.shlo_l_imm_alt_32,
+    /* 145 */ shift.shlo_r_imm_alt_32,
+    /* 146 */ shift.shar_r_imm_alt_32,
+    /* 147 */ mov.cmov_iz_imm,
+    /* 148 */ mov.cmov_nz_imm,
+    /* 149 */ math.add_imm,
+    /* 150 */ math.mul_imm,
+    /* 151 */ shift.shlo_l_imm,
+    /* 152 */ shift.shlo_r_imm,
+    /* 153 */ shift.shar_r_imm,
+    /* 154 */ math.neg_add_imm,
+    /* 155 */ shift.shlo_l_imm_alt,
+    /* 156 */ shift.shlo_r_imm_alt,
+    /* 157 */ shift.shar_r_imm_alt,
+    /* 158 */ rot.rot_r_64_imm,
+    /* 159 */ rot.rot_r_64_imm_alt,
+    /* 160 */ rot.rot_r_32_imm,
+    /* 161 */ rot.rot_r_32_imm_alt,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 170 */ branch.branch_eq,
+    /* 171 */ branch.branch_ne,
+    /* 172 */ branch.branch_lt_u,
+    /* 173 */ branch.branch_lt_s,
+    /* 174 */ branch.branch_ge_u,
+    /* 175 */ branch.branch_ge_s,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 180 */ jump.load_imm_jump_ind,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    INVALID,
+    /* 190 */ math.add_32,
+    /* 191 */ math.sub_32,
+    /* 192 */ math.mul_32,
+    /* 193 */ math.div_u_32,
+    /* 194 */ math.div_s_32,
+    /* 195 */ math.rem_u_32,
+    /* 196 */ math.rem_s_32,
+    /* 197 */ shift.shlo_l_32,
+    /* 198 */ shift.shlo_r_32,
+    /* 199 */ shift.shar_r_32,
+    /* 200 */ math.add_64,
+    /* 201 */ math.sub,
+    /* 202 */ math.mul,
+    /* 203 */ math.div_u,
+    /* 204 */ math.div_s,
+    /* 205 */ math.rem_u,
+    /* 206 */ math.rem_s,
+    /* 207 */ shift.shlo_l,
+    /* 208 */ shift.shlo_r,
+    /* 209 */ shift.shar_r,
+    /* 210 */ logic.and,
+    /* 211 */ logic.xor,
+    /* 212 */ logic.or,
+    /* 213 */ math.mul_upper_s_s,
+    /* 214 */ math.mul_upper_u_u,
+    /* 215 */ math.mul_upper_s_u,
+    /* 216 */ set.set_lt_u,
+    /* 217 */ set.set_lt_s,
+    /* 218 */ mov.cmov_iz,
+    /* 219 */ mov.cmov_nz,
+    /* 220 */ rot.rot_l_64,
+    /* 221 */ rot.rot_l_32,
+    /* 222 */ rot.rot_r_64,
+    /* 223 */ rot.rot_r_32,
+    /* 224 */ logic.and_inv,
+    /* 225 */ logic.or_inv,
+    /* 226 */ logic.xnor,
+    /* 227 */ math.max,
+    /* 228 */ math.max_u,
+    /* 229 */ math.min,
+    /* 230 */ math.min_u,
+];

package/dist/build/js/assembly/instructions.d.ts

@@ -0,0 +1,11 @@
+import { Arguments } from "./arguments";
+import { Gas } from "./gas";
+export declare class Instruction {
+    name: string;
+    kind: Arguments;
+    gas: Gas;
+    isTerminating: boolean;
+}
+export declare const MISSING_INSTRUCTION: Instruction;
+export declare const SBRK: Instruction;
+export declare const INSTRUCTIONS: Instruction[];

package/dist/build/js/assembly/instructions.js

@@ -0,0 +1,252 @@
+import { Arguments } from "./arguments";
+export class Instruction {
+    constructor() {
+        this.name = "";
+        this.kind = Arguments.Zero;
+        this.gas = i64(0);
+        this.isTerminating = false;
+    }
+}
+function instruction(name, kind, gas, isTerminating = false) {
+    const i = new Instruction();
+    i.name = name;
+    i.kind = kind;
+    i.gas = i64(gas);
+    i.isTerminating = isTerminating;
+    return i;
+}
+export const MISSING_INSTRUCTION = instruction("INVALID", Arguments.Zero, 1, false);
+export const SBRK = instruction("SBRK", Arguments.TwoReg, 1);
+export const INSTRUCTIONS = [
+    /* 000 */ instruction("TRAP", Arguments.Zero, 1, true),
+    /* 001 */ instruction("FALLTHROUGH", Arguments.Zero, 1, true),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 010 */ instruction("ECALLI", Arguments.OneImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 020 */ instruction("LOAD_IMM_64", Arguments.OneRegOneExtImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 030 */ instruction("STORE_IMM_U8", Arguments.TwoImm, 1),
+    /* 031 */ instruction("STORE_IMM_U16", Arguments.TwoImm, 1),
+    /* 032 */ instruction("STORE_IMM_U32", Arguments.TwoImm, 1),
+    /* 033 */ instruction("STORE_IMM_U64", Arguments.TwoImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 040 */ instruction("JUMP", Arguments.OneOff, 1, true),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 050 */ instruction("JUMP_IND", Arguments.OneRegOneImm, 1, true),
+    /* 051 */ instruction("LOAD_IMM", Arguments.OneRegOneImm, 1),
+    /* 052 */ instruction("LOAD_U8", Arguments.OneRegOneImm, 1),
+    /* 053 */ instruction("LOAD_I8", Arguments.OneRegOneImm, 1),
+    /* 054 */ instruction("LOAD_U16", Arguments.OneRegOneImm, 1),
+    /* 055 */ instruction("LOAD_I16", Arguments.OneRegOneImm, 1),
+    /* 056 */ instruction("LOAD_U32", Arguments.OneRegOneImm, 1),
+    /* 057 */ instruction("LOAD_I32", Arguments.OneRegOneImm, 1),
+    /* 058 */ instruction("LOAD_U64", Arguments.OneRegOneImm, 1),
+    /* 059 */ instruction("STORE_U8", Arguments.OneRegOneImm, 1),
+    /* 060 */ instruction("STORE_U16", Arguments.OneRegOneImm, 1),
+    /* 061 */ instruction("STORE_U32", Arguments.OneRegOneImm, 1),
+    /* 062 */ instruction("STORE_U64", Arguments.OneRegOneImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 070 */ instruction("STORE_IMM_IND_U8", Arguments.OneRegTwoImm, 1),
+    /* 071 */ instruction("STORE_IMM_IND_U16", Arguments.OneRegTwoImm, 1),
+    /* 072 */ instruction("STORE_IMM_IND_U32", Arguments.OneRegTwoImm, 1),
+    /* 073 */ instruction("STORE_IMM_IND_U64", Arguments.OneRegTwoImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 080 */ instruction("LOAD_IMM_JUMP", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 081 */ instruction("BRANCH_EQ_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 082 */ instruction("BRANCH_NE_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 083 */ instruction("BRANCH_LT_U_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 084 */ instruction("BRANCH_LE_U_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 085 */ instruction("BRANCH_GE_U_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 086 */ instruction("BRANCH_GT_U_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 087 */ instruction("BRANCH_LT_S_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 088 */ instruction("BRANCH_LE_S_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 089 */ instruction("BRANCH_GE_S_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    /* 090 */ instruction("BRANCH_GT_S_IMM", Arguments.OneRegOneImmOneOff, 1, true),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 100 */ instruction("MOVE_REG", Arguments.TwoReg, 1),
+    /* 101 */ SBRK,
+    /* 102 */ instruction("COUNT_SET_BITS_64", Arguments.TwoReg, 1),
+    /* 103 */ instruction("COUNT_SET_BITS_32", Arguments.TwoReg, 1),
+    /* 104 */ instruction("LEADING_ZERO_BITS_64", Arguments.TwoReg, 1),
+    /* 105 */ instruction("LEADING_ZERO_BITS_32", Arguments.TwoReg, 1),
+    /* 106 */ instruction("TRAILING_ZERO_BITS_64", Arguments.TwoReg, 1),
+    /* 107 */ instruction("TRAILING_ZERO_BITS_32", Arguments.TwoReg, 1),
+    /* 108 */ instruction("SIGN_EXTEND_8", Arguments.TwoReg, 1),
+    /* 109 */ instruction("SIGN_EXTEND_16", Arguments.TwoReg, 1),
+    /* 110 */ instruction("ZERO_EXTEND_16", Arguments.TwoReg, 1),
+    /* 111 */ instruction("REVERSE_BYTES", Arguments.TwoReg, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 120 */ instruction("STORE_IND_U8", Arguments.TwoRegOneImm, 1),
+    /* 121 */ instruction("STORE_IND_U16", Arguments.TwoRegOneImm, 1),
+    /* 122 */ instruction("STORE_IND_U32", Arguments.TwoRegOneImm, 1),
+    /* 123 */ instruction("STORE_IND_U64", Arguments.TwoRegOneImm, 1),
+    /* 124 */ instruction("LOAD_IND_U8", Arguments.TwoRegOneImm, 1),
+    /* 125 */ instruction("LOAD_IND_I8", Arguments.TwoRegOneImm, 1),
+    /* 126 */ instruction("LOAD_IND_U16", Arguments.TwoRegOneImm, 1),
+    /* 127 */ instruction("LOAD_IND_I16", Arguments.TwoRegOneImm, 1),
+    /* 128 */ instruction("LOAD_IND_U32", Arguments.TwoRegOneImm, 1),
+    /* 129 */ instruction("LOAD_IND_I32", Arguments.TwoRegOneImm, 1),
+    /* 130 */ instruction("LOAD_IND_U64", Arguments.TwoRegOneImm, 1),
+    /* 131 */ instruction("ADD_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 132 */ instruction("AND_IMM", Arguments.TwoRegOneImm, 1),
+    /* 133 */ instruction("XOR_IMM", Arguments.TwoRegOneImm, 1),
+    /* 134 */ instruction("OR_IMM", Arguments.TwoRegOneImm, 1),
+    /* 135 */ instruction("MUL_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 136 */ instruction("SET_LT_U_IMM", Arguments.TwoRegOneImm, 1),
+    /* 137 */ instruction("SET_LT_S_IMM", Arguments.TwoRegOneImm, 1),
+    /* 138 */ instruction("SHLO_L_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 139 */ instruction("SHLO_R_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 140 */ instruction("SHAR_R_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 141 */ instruction("NEG_ADD_IMM_32", Arguments.TwoRegOneImm, 1),
+    /* 142 */ instruction("SET_GT_U_IMM", Arguments.TwoRegOneImm, 1),
+    /* 143 */ instruction("SET_GT_S_IMM", Arguments.TwoRegOneImm, 1),
+    /* 144 */ instruction("SHLO_L_IMM_ALT_32", Arguments.TwoRegOneImm, 1),
+    /* 145 */ instruction("SHLO_R_IMM_ALT_32", Arguments.TwoRegOneImm, 1),
+    /* 146 */ instruction("SHAR_R_IMM_ALT_32", Arguments.TwoRegOneImm, 1),
+    /* 147 */ instruction("CMOV_IZ_IMM", Arguments.TwoRegOneImm, 1),
+    /* 148 */ instruction("CMOV_NZ_IMM", Arguments.TwoRegOneImm, 1),
+    /* 149 */ instruction("ADD_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 150 */ instruction("MUL_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 151 */ instruction("SHLO_L_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 152 */ instruction("SHLO_R_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 153 */ instruction("SHAR_R_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 154 */ instruction("NEG_ADD_IMM_64", Arguments.TwoRegOneImm, 1),
+    /* 155 */ instruction("SHLO_L_IMM_ALT_64", Arguments.TwoRegOneImm, 1),
+    /* 156 */ instruction("SHLO_R_IMM_ALT_64", Arguments.TwoRegOneImm, 1),
+    /* 157 */ instruction("SHAR_R_IMM_ALT_64", Arguments.TwoRegOneImm, 1),
+    /* 158 */ instruction("ROT_R_64_IMM", Arguments.TwoRegOneImm, 1),
+    /* 159 */ instruction("ROT_R_64_IMM_ALT", Arguments.TwoRegOneImm, 1),
+    /* 160 */ instruction("ROT_R_32_IMM", Arguments.TwoRegOneImm, 1),
+    /* 161 */ instruction("ROT_R_32_IMM_ALT", Arguments.TwoRegOneImm, 1),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 170 */ instruction("BRANCH_EQ", Arguments.TwoRegOneOff, 1, true),
+    /* 171 */ instruction("BRANCH_NE", Arguments.TwoRegOneOff, 1, true),
+    /* 172 */ instruction("BRANCH_LT_U", Arguments.TwoRegOneOff, 1, true),
+    /* 173 */ instruction("BRANCH_LT_S", Arguments.TwoRegOneOff, 1, true),
+    /* 174 */ instruction("BRANCH_GE_U", Arguments.TwoRegOneOff, 1, true),
+    /* 175 */ instruction("BRANCH_GE_S", Arguments.TwoRegOneOff, 1, true),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 180 */ instruction("LOAD_IMM_JUMP_IND", Arguments.TwoRegTwoImm, 1, true),
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    MISSING_INSTRUCTION,
+    /* 190 */ instruction("ADD_32", Arguments.ThreeReg, 1),
+    /* 191 */ instruction("SUB_32", Arguments.ThreeReg, 1),
+    /* 192 */ instruction("MUL_32", Arguments.ThreeReg, 1),
+    /* 193 */ instruction("DIV_U_32", Arguments.ThreeReg, 1),
+    /* 194 */ instruction("DIV_S_32", Arguments.ThreeReg, 1),
+    /* 195 */ instruction("REM_U_32", Arguments.ThreeReg, 1),
+    /* 196 */ instruction("REM_S_32", Arguments.ThreeReg, 1),
+    /* 197 */ instruction("SHLO_L_32", Arguments.ThreeReg, 1),
+    /* 198 */ instruction("SHLO_R_32", Arguments.ThreeReg, 1),
+    /* 199 */ instruction("SHAR_R_32", Arguments.ThreeReg, 1),
+    /* 200 */ instruction("ADD_64", Arguments.ThreeReg, 1),
+    /* 201 */ instruction("SUB_64", Arguments.ThreeReg, 1),
+    /* 202 */ instruction("MUL_64", Arguments.ThreeReg, 1),
+    /* 203 */ instruction("DIV_U_64", Arguments.ThreeReg, 1),
+    /* 204 */ instruction("DIV_S_64", Arguments.ThreeReg, 1),
+    /* 205 */ instruction("REM_U_64", Arguments.ThreeReg, 1),
+    /* 206 */ instruction("REM_S_64", Arguments.ThreeReg, 1),
+    /* 207 */ instruction("SHLO_L_64", Arguments.ThreeReg, 1),
+    /* 208 */ instruction("SHLO_R_64", Arguments.ThreeReg, 1),
+    /* 209 */ instruction("SHAR_R_64", Arguments.ThreeReg, 1),
+    /* 210 */ instruction("AND", Arguments.ThreeReg, 1),
+    /* 211 */ instruction("XOR", Arguments.ThreeReg, 1),
+    /* 212 */ instruction("OR", Arguments.ThreeReg, 1),
+    /* 213 */ instruction("MUL_UPPER_S_S", Arguments.ThreeReg, 1),
+    /* 214 */ instruction("MUL_UPPER_U_U", Arguments.ThreeReg, 1),
+    /* 215 */ instruction("MUL_UPPER_S_U", Arguments.ThreeReg, 1),
+    /* 216 */ instruction("SET_LT_U", Arguments.ThreeReg, 1),
+    /* 217 */ instruction("SET_LT_S", Arguments.ThreeReg, 1),
+    /* 218 */ instruction("CMOV_IZ", Arguments.ThreeReg, 1),
+    /* 219 */ instruction("CMOV_NZ", Arguments.ThreeReg, 1),
+    /* 220 */ instruction("ROT_L_64", Arguments.ThreeReg, 1),
+    /* 221 */ instruction("ROT_L_32", Arguments.ThreeReg, 1),
+    /* 222 */ instruction("ROT_R_64", Arguments.ThreeReg, 1),
+    /* 223 */ instruction("ROT_R_32", Arguments.ThreeReg, 1),
+    /* 224 */ instruction("AND_INV", Arguments.ThreeReg, 1),
+    /* 225 */ instruction("OR_INV", Arguments.ThreeReg, 1),
+    /* 226 */ instruction("XNOR", Arguments.ThreeReg, 1),
+    /* 227 */ instruction("MAX", Arguments.ThreeReg, 1),
+    /* 228 */ instruction("MAX_U", Arguments.ThreeReg, 1),
+    /* 229 */ instruction("MIN", Arguments.ThreeReg, 1),
+    /* 230 */ instruction("MIN_U", Arguments.ThreeReg, 1),
+];

package/dist/build/js/assembly/interpreter.d.ts

@@ -0,0 +1,29 @@
+import { GasCounter } from "./gas";
+import { Memory } from "./memory";
+import { Program } from "./program";
+import { Registers } from "./registers";
+export declare enum Status {
+    OK = -1,
+    HALT = 0,
+    PANIC = 1,
+    FAULT = 2,
+    HOST = 3,
+    OOG = 4
+}
+export declare class Interpreter {
+    readonly program: Program;
+    readonly registers: Registers;
+    readonly memory: Memory;
+    readonly gas: GasCounter;
+    pc: u32;
+    status: Status;
+    exitCode: u32;
+    nextPc: u32;
+    useSbrkGas: boolean;
+    private djumpRes;
+    private argsRes;
+    private outcomeRes;
+    private branchRes;
+    constructor(program: Program, registers: Registers, memory?: Memory);
+    nextSteps(nSteps?: u32): boolean;
+}