@fjader/svelte 0.2.1 → 0.2.3

package/dist/gpu/ScaleTemplateSystem.js

@@ -1,6 +1,9 @@
 // src/lib/gpu/ScaleTemplateSystem.ts
 import { COLOR_SCALE_STRUCTS, COLOR_SCALE_BINDINGS, COLOR_SCALE_FUNCTIONS } from './ColorScaleShaderLib';
 import { SIZE_SCALE_STRUCTS, SIZE_SCALE_BINDINGS, SIZE_SCALE_FUNCTIONS } from './SizeScaleShaderLib';
+import { NO_GROUP } from './identity-slot-packing';
+import { isNanExpr } from './NanShaderLib';
+import { DEFAULT_INACTIVE_OPACITY } from '../scales/ActivityTable';
 /**
  * Scale fragment definitions
  * Each scale type provides: declaration, function call, and implementation
@@ -280,6 +283,9 @@ function _scaleFunctionName(scaleType, axis) {
  * `ScaleParam`, 16 bytes each. Every layout declares the same size because a
  * draw requires every declared byte to have been set, and the pass sets them
  * once, before its first draw.
+ *
+ * Immediates carry state shared across the pass and read by several marks: the
+ * chart's scales and settings. 64 bytes are available on M-series Macs.
  */
 export const CHART_SCALE_IMMEDIATE_SIZE = 32;
 /**
@@ -370,6 +376,7 @@ export class ScaleTemplateSystem {
       // ===== 3. HELPER FUNCTIONS =====
       
       ${this._buildSlotTableHelpers()}
+      ${this._buildBandActivityHelpers(scaleTypes)}
       ${bandHelpers}
       ${implementations}
       ${scaleFunctions}
@@ -409,6 +416,24 @@ export class ScaleTemplateSystem {
       };
       var<immediate> chartScales: ChartScales;
 
+      // Selection dimming: a mark's activity mapped to an opacity, with
+      // inactive categories at DEFAULT_INACTIVE_OPACITY. selectionOpacity in
+      // ActivityTable.ts is its CPU twin, for band labels and legend entries,
+      // and both read the same constant so they cannot drift apart.
+      const SELECTION_DIM_STRENGTH: f32 = ${(1 - DEFAULT_INACTIVE_OPACITY).toFixed(6)};
+      fn selectionDim(activity: f32) -> f32 {
+        return 1.0 - SELECTION_DIM_STRENGTH * (1.0 - activity);
+      }
+
+      // A mark's activities combined: colour, and band for marks on band axes.
+      // The least active wins rather than the product, so a bar whose colour
+      // and band are the same field fades on the same curve as its label
+      // instead of twice as fast. At rest every activity is 0 or 1, where the
+      // two agree.
+      fn markActivity(color: f32, bandX: f32, bandY: f32) -> f32 {
+        return min(color, min(bandX, bandY));
+      }
+
       // The ONE place that says where a chart's scales come from. Every
       // consumer reads through these — scaleX/scaleY, the bandwidth helpers,
       // and mark code that needs the raw params. A mark with scales of its own
@@ -423,6 +448,39 @@ export class ScaleTemplateSystem {
     `;
         return `${structDef}\n${chartScaleDeclaration}`;
     }
+    /**
+     * `bandActivityX(value, group)` and `bandActivityY(value, group)`: how
+     * selected a band or point axis's category is in the mark's filter group,
+     * 0..1, for selection dimming.
+     *
+     * Emitted for every shader, so a renderer can call both without knowing its
+     * scale types: an axis that is not band or point returns 1.0. On a band or
+     * point axis the value is an identity id and the chart's scale carries its
+     * block base in p4, as for the slot lookup. A missing category (-1) or a NaN
+     * is fully active, checked before the cast, since u32() of a negative or NaN
+     * float is indeterminate in WGSL.
+     */
+    _buildBandActivityHelpers(scaleTypes) {
+        const helper = (axis, type) => {
+            if (type !== 'band' && type !== 'point') {
+                return `fn bandActivity${axis}(value: f32, group: u32) -> f32 {
+      return 1.0;
+    }`;
+            }
+            return `fn bandActivity${axis}(value: f32, group: u32) -> f32 {
+      if (value < 0.0 || ${isNanExpr('value')}) {
+        return 1.0;
+      }
+      return identityActivity(u32(chartScale${axis}().p4), group, u32(value));
+    }`;
+        };
+        return `
+    // ===== BAND SELECTION ACTIVITY =====
+    ${helper('X', scaleTypes.x)}
+
+    ${helper('Y', scaleTypes.y)}
+    `;
+    }
     /**
      * The shared slot table, and the lookup into it.
      *
@@ -459,12 +517,12 @@ export class ScaleTemplateSystem {
     }
 
     fn identitySlot(base: u32, id: u32) -> f32 {
-      // Block layout: [count, slot0, slot1, ...]. The count is what makes a
-      // block self-describing, so an id past this scale's end is discarded
-      // instead of reading into the next scale's slots. It survives the resolve
-      // exactly because it holds the same value in both halves, and the kernel
-      // returns equal ends as they are — u32() truncates, so an inexact mix
-      // would drop the last id.
+      // Block layout: [count, actRef, n, slot0, slot1, ...]. The count is what
+      // makes a block self-describing, so an id past this scale's end is
+      // discarded instead of reading into the next scale's slots. It survives
+      // the resolve exactly because it holds the same value in both halves, and
+      // the kernel returns equal ends as they are — u32() truncates, so an
+      // inexact mix would drop the last id.
       let count = u32(identitySlots[base]);
       if (id >= count) {
         return -1.0;
@@ -473,7 +531,28 @@ export class ScaleTemplateSystem {
       // both halves, so the resolve wrote -1 without a branch; one that is
       // leaving holds a real slot in both, which is what lets it travel. The
       // scale normalises that before packing, so nothing here re-derives it.
-      return identitySlots[base + 1u + id];
+      return identitySlots[base + 3u + id];
+    }
+
+    fn identityActivity(base: u32, group: u32, id: u32) -> f32 {
+      // How selected this id is in the mark's filter group, 1 active and 0
+      // inactive, already resolved at that group's selection clock. The scale
+      // block's header points at its field's activity block (actRef) and says
+      // how many ids it covers (n); the block holds one run of n per group.
+      // Header first, so this is two dependent reads. Past n, or in the empty
+      // block where n is 0, an id is fully active.
+      //
+      // NO_GROUP (a mark whose selectionResponse is 'filter') is fully active,
+      // checked before anything is read, so it never becomes an offset.
+      if (group == ${NO_GROUP}u) {
+        return 1.0;
+      }
+      let actRef = u32(identitySlots[base + 1u]);
+      let n = u32(identitySlots[base + 2u]);
+      if (id >= n) {
+        return 1.0;
+      }
+      return identitySlots[actRef + n * group + id];
     }
     `;
     }

package/dist/gpu/SizeScaleShaderLib.d.ts

@@ -19,13 +19,13 @@ export declare const MAX_SIZE_SLOTS = 64;
  * changes rather than per frame. Every property that makes a uniform buffer the
  * right container was already true of it.
  *
- * What it buys: the vertex stage sits at the default
- * maxStorageBuffersPerShaderStage of 8 (six mark channels, scale params, and
- * this), and animating a value channel needs a `from` and a `to` where there is
- * now one buffer. Uniform buffers are nowhere near their own default of 12.
+ * What it buys: a slot in the vertex stage's storage budget, the default
+ * maxStorageBuffersPerShaderStage of 8, of which Rects uses 7 (six mark
+ * channels and the identity slot table). Uniform buffers are nowhere near
+ * their own default of 12.
  *
  * Dynamic indexing — `sizeConfigs[scaleIndex]` — is permitted on uniform arrays
  * in WGSL, and the shared slot table already relies on the same thing.
  */
 export declare const SIZE_SCALE_BINDINGS = "\n@group(2) @binding(4) var<uniform> sizeConfigs: array<SizeConfig, 64>;\n";
-export declare const SIZE_SCALE_FUNCTIONS = "\nfn getSizeFromScale(scaleIndex: u32, value: f32) -> f32 {\n    let config = sizeConfigs[scaleIndex];\n\n    // Handle NaN \u2192 rangeMin\n    if (value != value) {\n        return config.rangeMin;\n    }\n\n    let range = config.domainMax - config.domainMin;\n\n    // Degenerate domain \u2192 midpoint of range\n    if (abs(range) < 0.0001) {\n        return (config.rangeMin + config.rangeMax) * 0.5;\n    }\n\n    // Normalize to [0, 1]\n    let t = clamp((value - config.domainMin) / range, 0.0, 1.0);\n\n    // Sqrt for area-proportional scaling\n    let s = sqrt(t);\n\n    // Interpolate to pixel range\n    return config.rangeMin + s * (config.rangeMax - config.rangeMin);\n}\n";
+export declare const SIZE_SCALE_FUNCTIONS: string;

package/dist/gpu/SizeScaleShaderLib.js

@@ -1,3 +1,4 @@
+import { isNanExpr } from './NanShaderLib';
 // src/lib/gpu/SizeScaleShaderLib.js
 export const SIZE_SCALE_STRUCTS = /* wgsl */ `
 struct SizeConfig {
@@ -27,10 +28,10 @@ export const MAX_SIZE_SLOTS = 64;
  * changes rather than per frame. Every property that makes a uniform buffer the
  * right container was already true of it.
  *
- * What it buys: the vertex stage sits at the default
- * maxStorageBuffersPerShaderStage of 8 (six mark channels, scale params, and
- * this), and animating a value channel needs a `from` and a `to` where there is
- * now one buffer. Uniform buffers are nowhere near their own default of 12.
+ * What it buys: a slot in the vertex stage's storage budget, the default
+ * maxStorageBuffersPerShaderStage of 8, of which Rects uses 7 (six mark
+ * channels and the identity slot table). Uniform buffers are nowhere near
+ * their own default of 12.
  *
  * Dynamic indexing — `sizeConfigs[scaleIndex]` — is permitted on uniform arrays
  * in WGSL, and the shared slot table already relies on the same thing.
@@ -43,7 +44,7 @@ fn getSizeFromScale(scaleIndex: u32, value: f32) -> f32 {
     let config = sizeConfigs[scaleIndex];
 
     // Handle NaN → rangeMin
-    if (value != value) {
+    if (${isNanExpr('value')}) {
         return config.rangeMin;
     }
 

package/dist/gpu/decimation/M4Shader.d.ts

@@ -27,6 +27,12 @@
  *
  * The x scale's params reach passes 1 and 2 as immediates, pushed before each
  * dispatch, rather than as an index into the global scale table.
+ *
+ * Every pass reads and writes the data through u32 views. NaN (a null, or an
+ * empty bin) is found by its bit pattern and moved as bits, never compared as
+ * a float: Metal compilers may fold `x != x` to false (see NanShaderLib), and
+ * where they do, compaction keeps the empty bins and the line loses every
+ * segment that touches one.
  */
 declare const WORKGROUP_SIZE = 256;
 /** Bytes of immediate data passes 1 and 2 read: one ScaleParam. */
@@ -44,7 +50,7 @@ declare const X_SCALE_IMMEDIATE_SIZE = 16;
  * Group 0: inputLayout (data dummies + config + bins)
  * Group 1: controlLayout (control)
  */
-declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\n\t// Thread 0: read JS decision, set instance count\n\tif (binKey == 0u) {\n\t\tlet outputSize = config.numBins * config.numSeries * 4u;\n\t\t// JS sets _pad: 1 = decimate, 2 = passthrough\n\t\tlet shouldDec = config.decimationMode == 1u;\n\t\tatomicStore(&control[4], select(0u, 1u, shouldDec));\n\t\tatomicStore(&control[1], select(0u, outputSize, shouldDec));\n\t}\n\n\t// Always init bins \u2014 cheap and ensures clean state for potential decimation.\n\tif (binKey >= totalBins) { return; }\n\n\tatomicStore(&bins[binKey].firstIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].lastIdx, 0u);\n\tatomicStore(&bins[binKey].minYSortable, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYSortable, 0u);\n\tatomicStore(&bins[binKey].minYIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYIdx, 0xFFFFFFFFu);\n}\n";
+declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\n\t// Thread 0: read JS decision, set instance count\n\tif (binKey == 0u) {\n\t\tlet outputSize = config.numBins * config.numSeries * 4u;\n\t\t// JS sets _pad: 1 = decimate, 2 = passthrough\n\t\tlet shouldDec = config.decimationMode == 1u;\n\t\tatomicStore(&control[4], select(0u, 1u, shouldDec));\n\t\tatomicStore(&control[1], select(0u, outputSize, shouldDec));\n\t}\n\n\t// Always init bins \u2014 cheap and ensures clean state for potential decimation.\n\tif (binKey >= totalBins) { return; }\n\n\tatomicStore(&bins[binKey].firstIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].lastIdx, 0u);\n\tatomicStore(&bins[binKey].minYSortable, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYSortable, 0u);\n\tatomicStore(&bins[binKey].minYIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYIdx, 0xFFFFFFFFu);\n}\n";
 /**
  * Pass 1: Bin each point by scaled x position.
  *
@@ -55,7 +61,7 @@ declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tn
  * Group 1: controlLayout (control)
  * Immediates: the x scale (ScaleParam)
  */
-declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only bin if decimating\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tlet x = xValues[idx];\n\tlet y = yValues[idx];\n\n\t// Skip NaN points\n\tif (x != x || y != y) { return; }\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)\n\tlet seriesF = seriesValues[idx];\n\tif (seriesF < 0.0 || seriesF != seriesF) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Bin assignment: boundary bins capture off-screen points for line connectivity.\n\t// Bins 0 and numBins-1 are boundary bins; bins 1..numBins-2 map to viewport pixels.\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tatomicMin(&bins[binKey].firstIdx, idx);\n\tatomicMax(&bins[binKey].lastIdx, idx);\n\n\tlet ySortable = floatToSortableUint(y);\n\tatomicMin(&bins[binKey].minYSortable, ySortable);\n\tatomicMax(&bins[binKey].maxYSortable, ySortable);\n}\n";
+declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only bin if decimating\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\t// Skip NaN points, tested on the bits before either becomes a float\n\tlet xb = xBits[idx];\n\tlet yb = yBits[idx];\n\tif (isNanBits(xb) || isNanBits(yb)) { return; }\n\tlet x = bitcast<f32>(xb);\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)\n\tlet seriesB = seriesBits[idx];\n\tif (isNanBits(seriesB)) { return; }\n\tlet seriesF = bitcast<f32>(seriesB);\n\tif (seriesF < 0.0) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Bin assignment: boundary bins capture off-screen points for line connectivity.\n\t// Bins 0 and numBins-1 are boundary bins; bins 1..numBins-2 map to viewport pixels.\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tatomicMin(&bins[binKey].firstIdx, idx);\n\tatomicMax(&bins[binKey].lastIdx, idx);\n\n\tlet ySortable = sortableFromBits(yb);\n\tatomicMin(&bins[binKey].minYSortable, ySortable);\n\tatomicMax(&bins[binKey].maxYSortable, ySortable);\n}\n";
 /**
  * Pass 2: Find indices of min/max Y points.
  * Each thread re-checks if its Y value matches the bin's min/max.
@@ -67,7 +73,7 @@ declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct
  * Group 1: controlLayout (control — only reads shouldDecimate)
  * Immediates: the x scale (ScaleParam)
  */
-declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tlet x = xValues[idx];\n\tlet y = yValues[idx];\n\n\tif (x != x || y != y) { return; }\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed (matches binPoints pass)\n\tlet seriesF = seriesValues[idx];\n\tif (seriesF < 0.0 || seriesF != seriesF) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Boundary bin clamping (matches binPoints pass)\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tlet ySortable = floatToSortableUint(y);\n\n\tif (ySortable == atomicLoad(&bins[binKey].minYSortable)) {\n\t\tatomicMin(&bins[binKey].minYIdx, idx);\n\t}\n\tif (ySortable == atomicLoad(&bins[binKey].maxYSortable)) {\n\t\tatomicMin(&bins[binKey].maxYIdx, idx);\n\t}\n}\n";
+declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\t// NaN skip on the bits (matches binPoints pass)\n\tlet xb = xBits[idx];\n\tlet yb = yBits[idx];\n\tif (isNanBits(xb) || isNanBits(yb)) { return; }\n\tlet x = bitcast<f32>(xb);\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed (matches binPoints pass)\n\tlet seriesB = seriesBits[idx];\n\tif (isNanBits(seriesB)) { return; }\n\tlet seriesF = bitcast<f32>(seriesB);\n\tif (seriesF < 0.0) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Boundary bin clamping (matches binPoints pass)\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tlet ySortable = sortableFromBits(yb);\n\n\tif (ySortable == atomicLoad(&bins[binKey].minYSortable)) {\n\t\tatomicMin(&bins[binKey].minYIdx, idx);\n\t}\n\tif (ySortable == atomicLoad(&bins[binKey].maxYSortable)) {\n\t\tatomicMin(&bins[binKey].maxYIdx, idx);\n\t}\n}\n";
 /**
  * Pass 3: Emit decimated output arrays.
  * Each thread processes one bin, collecting up to 4 unique indices
@@ -82,7 +88,7 @@ declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruc
  * Group 0: emitInputLayout (x, y, color, config, bins)
  * Group 1: outputLayout (xOut, yOut, seriesOut, colorOut)
  */
-declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\n// Note: seriesValues not bound here \u2014 series is derived from binKey / numBins.\n// This keeps total storage buffers within WebGPU default limit.\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> colorValues: array<f32>;\n@group(0) @binding(3) var<uniform> config: M4Config;\n@group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;\n@group(1) @binding(2) var<storage, read_write> seriesOut: array<f32>;\n@group(1) @binding(3) var<storage, read_write> colorOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\tif (binKey >= totalBins) { return; }\n\n\tlet outBase = binKey * 4u;\n\tlet firstIdx = atomicLoad(&bins[binKey].firstIdx);\n\n\t// Empty bin: write NaN to all 4 output slots\n\t// Use var to avoid const-expression NaN (WGSL disallows NaN in const context)\n\tif (firstIdx == 0xFFFFFFFFu) {\n\t\tvar nanBits = 0x7FC00000u;\n\t\tlet nan = bitcast<f32>(nanBits);\n\t\tfor (var i = 0u; i < 4u; i++) {\n\t\t\txOut[outBase + i] = nan;\n\t\t\tyOut[outBase + i] = nan;\n\t\t\tseriesOut[outBase + i] = nan;\n\t\t\tcolorOut[outBase + i] = nan;\n\t\t}\n\t\treturn;\n\t}\n\n\tlet lastIdx = atomicLoad(&bins[binKey].lastIdx);\n\tlet minYIdx = atomicLoad(&bins[binKey].minYIdx);\n\tlet maxYIdx = atomicLoad(&bins[binKey].maxYIdx);\n\n\t// Collect up to 4 unique indices, sorted by original index (= x-order)\n\tvar indices: array<u32, 4>;\n\tvar count = 0u;\n\n\t// Insert in sorted order, skip duplicates\n\tvar candidates = array<u32, 4>(firstIdx, lastIdx, minYIdx, maxYIdx);\n\n\t// Simple insertion sort for up to 4 candidates\n\tfor (var c = 0u; c < 4u; c++) {\n\t\tlet candidate = candidates[c];\n\t\t// Check if already present\n\t\tvar isDuplicate = false;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (indices[k] == candidate) {\n\t\t\t\tisDuplicate = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (isDuplicate) { continue; }\n\n\t\t// Insert in sorted position\n\t\tvar insertPos = count;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (candidate < indices[k]) {\n\t\t\t\tinsertPos = k;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t// Shift elements right\n\t\tfor (var k = count; k > insertPos; k--) {\n\t\t\tindices[k] = indices[k - 1u];\n\t\t}\n\t\tindices[insertPos] = candidate;\n\t\tcount++;\n\t}\n\n\t// Derive series value from bin key (0-indexed, matching ViewManager convention).\n\t// Vertex shader uses != comparison for series breaks, so any distinct values work.\n\tlet seriesVal = f32(binKey / config.numBins);\n\n\t// Write unique points, fill remaining slots with last unique point\n\tfor (var i = 0u; i < 4u; i++) {\n\t\tlet srcIdx = indices[min(i, count - 1u)];\n\t\txOut[outBase + i] = xValues[srcIdx];\n\t\tyOut[outBase + i] = yValues[srcIdx];\n\t\tseriesOut[outBase + i] = seriesVal;\n\t\tcolorOut[outBase + i] = colorValues[srcIdx];\n\t}\n}\n";
+declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\n// Note: seriesValues not bound here \u2014 series is derived from binKey / numBins.\n// This keeps total storage buffers within WebGPU default limit.\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> colorBits: array<u32>;\n@group(0) @binding(3) var<uniform> config: M4Config;\n@group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;\n@group(1) @binding(2) var<storage, read_write> seriesOut: array<u32>;\n@group(1) @binding(3) var<storage, read_write> colorOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\tif (binKey >= totalBins) { return; }\n\n\tlet outBase = binKey * 4u;\n\tlet firstIdx = atomicLoad(&bins[binKey].firstIdx);\n\n\t// Empty bin: NaN in all 4 output slots, written as bits\n\tif (firstIdx == 0xFFFFFFFFu) {\n\t\tfor (var i = 0u; i < 4u; i++) {\n\t\t\txOut[outBase + i] = NAN_BITS;\n\t\t\tyOut[outBase + i] = NAN_BITS;\n\t\t\tseriesOut[outBase + i] = NAN_BITS;\n\t\t\tcolorOut[outBase + i] = NAN_BITS;\n\t\t}\n\t\treturn;\n\t}\n\n\tlet lastIdx = atomicLoad(&bins[binKey].lastIdx);\n\tlet minYIdx = atomicLoad(&bins[binKey].minYIdx);\n\tlet maxYIdx = atomicLoad(&bins[binKey].maxYIdx);\n\n\t// Collect up to 4 unique indices, sorted by original index (= x-order)\n\tvar indices: array<u32, 4>;\n\tvar count = 0u;\n\n\t// Insert in sorted order, skip duplicates\n\tvar candidates = array<u32, 4>(firstIdx, lastIdx, minYIdx, maxYIdx);\n\n\t// Simple insertion sort for up to 4 candidates\n\tfor (var c = 0u; c < 4u; c++) {\n\t\tlet candidate = candidates[c];\n\t\t// Check if already present\n\t\tvar isDuplicate = false;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (indices[k] == candidate) {\n\t\t\t\tisDuplicate = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (isDuplicate) { continue; }\n\n\t\t// Insert in sorted position\n\t\tvar insertPos = count;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (candidate < indices[k]) {\n\t\t\t\tinsertPos = k;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t// Shift elements right\n\t\tfor (var k = count; k > insertPos; k--) {\n\t\t\tindices[k] = indices[k - 1u];\n\t\t}\n\t\tindices[insertPos] = candidate;\n\t\tcount++;\n\t}\n\n\t// Derive series value from bin key (0-indexed, matching ViewManager convention).\n\t// Vertex shader uses != comparison for series breaks, so any distinct values work.\n\tlet seriesVal = bitcast<u32>(f32(binKey / config.numBins));\n\n\t// Write unique points, fill remaining slots with last unique point.\n\t// Copied as bits, so a value arrives exactly as it left.\n\tfor (var i = 0u; i < 4u; i++) {\n\t\tlet srcIdx = indices[min(i, count - 1u)];\n\t\txOut[outBase + i] = xBits[srcIdx];\n\t\tyOut[outBase + i] = yBits[srcIdx];\n\t\tseriesOut[outBase + i] = seriesVal;\n\t\tcolorOut[outBase + i] = colorBits[srcIdx];\n\t}\n}\n";
 /**
  * Pass 4: Compact non-NaN output points and deduplicate.
  * After the emit pass, empty bins contain NaN. This pass packs real data
@@ -100,7 +106,7 @@ declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\
  * Group 0: fillLayout (config + output arrays)
  * Group 1: controlLayout (control)
  */
-declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<uniform> config: M4Config;\n@group(0) @binding(1) var<storage, read_write> xOut: array<f32>;\n@group(0) @binding(2) var<storage, read_write> yOut: array<f32>;\n@group(0) @binding(3) var<storage, read_write> seriesOut: array<f32>;\n@group(0) @binding(4) var<storage, read_write> colorOut: array<f32>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(1)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet series = gid.x;\n\tif (series >= config.numSeries) { return; }\n\n\tlet start = series * 4u * config.numBins;\n\tlet end = start + 4u * config.numBins;\n\n\t// Pack non-NaN points to the front, skipping consecutive duplicates.\n\tvar writeIdx = start;\n\tvar nanBits = 0x7FC00000u;\n\tvar lastX: f32 = bitcast<f32>(nanBits);\n\tvar lastY: f32 = bitcast<f32>(nanBits);\n\n\tfor (var i = start; i < end; i++) {\n\t\tlet x = xOut[i];\n\t\tif (x != x) { continue; }\n\t\tlet y = yOut[i];\n\t\tif (x == lastX && y == lastY) { continue; }\n\n\t\tif (writeIdx != i) {\n\t\t\txOut[writeIdx] = x;\n\t\t\tyOut[writeIdx] = y;\n\t\t\tseriesOut[writeIdx] = seriesOut[i];\n\t\t\tcolorOut[writeIdx] = colorOut[i];\n\t\t}\n\t\tlastX = x;\n\t\tlastY = y;\n\t\twriteIdx++;\n\t}\n\n\t// NaN-pad remaining slots\n\tlet nan = bitcast<f32>(nanBits);\n\tfor (var i = writeIdx; i < end; i++) {\n\t\txOut[i] = nan;\n\t\tyOut[i] = nan;\n\t\tseriesOut[i] = nan;\n\t\tcolorOut[i] = nan;\n\t}\n\n\t// Instance count is set by pass 0 (outputSize) \u2014 compact only reorganizes\n\t// data within each series block, it doesn't change the total count.\n\t// The vertex shader discards NaN-padded entries at the end of each block.\n}\n";
+declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n@group(0) @binding(0) var<uniform> config: M4Config;\n@group(0) @binding(1) var<storage, read_write> xOut: array<u32>;\n@group(0) @binding(2) var<storage, read_write> yOut: array<u32>;\n@group(0) @binding(3) var<storage, read_write> seriesOut: array<u32>;\n@group(0) @binding(4) var<storage, read_write> colorOut: array<u32>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(1)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet series = gid.x;\n\tif (series >= config.numSeries) { return; }\n\n\tlet start = series * 4u * config.numBins;\n\tlet end = start + 4u * config.numBins;\n\n\t// Pack non-NaN points to the front, skipping consecutive duplicates.\n\t// All on bits: NaN by its pattern, duplicates by identical bits. lastX\n\t// starts as NaN, which no kept x can equal.\n\tvar writeIdx = start;\n\tvar lastX = NAN_BITS;\n\tvar lastY = NAN_BITS;\n\n\tfor (var i = start; i < end; i++) {\n\t\tlet x = xOut[i];\n\t\tif (isNanBits(x)) { continue; }\n\t\tlet y = yOut[i];\n\t\tif (x == lastX && y == lastY) { continue; }\n\n\t\tif (writeIdx != i) {\n\t\t\txOut[writeIdx] = x;\n\t\t\tyOut[writeIdx] = y;\n\t\t\tseriesOut[writeIdx] = seriesOut[i];\n\t\t\tcolorOut[writeIdx] = colorOut[i];\n\t\t}\n\t\tlastX = x;\n\t\tlastY = y;\n\t\twriteIdx++;\n\t}\n\n\t// NaN-pad remaining slots\n\tfor (var i = writeIdx; i < end; i++) {\n\t\txOut[i] = NAN_BITS;\n\t\tyOut[i] = NAN_BITS;\n\t\tseriesOut[i] = NAN_BITS;\n\t\tcolorOut[i] = NAN_BITS;\n\t}\n\n\t// Instance count is set by pass 0 (outputSize) \u2014 compact only reorganizes\n\t// data within each series block, it doesn't change the total count.\n\t// The vertex shader discards NaN-padded entries at the end of each block.\n}\n";
 /**
  * Pass 5a: Passthrough copy — raw x,y → output + set indirect count.
  *
@@ -113,7 +119,7 @@ declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBi
  * Group 0: passthroughInputLayout (data0, data1, config, control)
  * Group 1: halfOutputLayout (out0, out1)
  */
-declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<storage, read> xIn: array<f32>;\n@group(0) @binding(1) var<storage, read> yIn: array<f32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\n\t// Thread 0 sets instance count to raw point count\n\tif (idx == 0u) {\n\t\tatomicStore(&control[1], config.pointCount);\n\t}\n\n\tif (idx >= config.pointCount) { return; }\n\n\txOut[idx] = xIn[idx];\n\tyOut[idx] = yIn[idx];\n}\n";
+declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n// Copied as bits, so a null's NaN arrives exactly as it left.\n@group(0) @binding(0) var<storage, read> xIn: array<u32>;\n@group(0) @binding(1) var<storage, read> yIn: array<u32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\n\t// Thread 0 sets instance count to raw point count\n\tif (idx == 0u) {\n\t\tatomicStore(&control[1], config.pointCount);\n\t}\n\n\tif (idx >= config.pointCount) { return; }\n\n\txOut[idx] = xIn[idx];\n\tyOut[idx] = yIn[idx];\n}\n";
 /**
  * Pass 5b: Passthrough copy — raw series,color → output.
  *
@@ -125,5 +131,5 @@ declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n
  * Group 0: passthroughInputLayout (data0, data1, config, control)
  * Group 1: halfOutputLayout (out0, out1)
  */
-declare const PASSTHROUGH_SC_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<storage, read> seriesIn: array<f32>;\n@group(0) @binding(1) var<storage, read> colorIn: array<f32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> seriesOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> colorOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tseriesOut[idx] = seriesIn[idx];\n\tcolorOut[idx] = colorIn[idx];\n}\n";
+declare const PASSTHROUGH_SC_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n// Copied as bits, like pass 5a.\n@group(0) @binding(0) var<storage, read> seriesIn: array<u32>;\n@group(0) @binding(1) var<storage, read> colorIn: array<u32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> seriesOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> colorOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tseriesOut[idx] = seriesIn[idx];\n\tcolorOut[idx] = colorIn[idx];\n}\n";
 export { WORKGROUP_SIZE, X_SCALE_IMMEDIATE_SIZE, INIT_BINS_SHADER, BIN_POINTS_SHADER, FIND_MINMAX_SHADER, EMIT_OUTPUT_SHADER, COMPACT_SHADER, PASSTHROUGH_XY_SHADER, PASSTHROUGH_SC_SHADER };

package/dist/gpu/decimation/M4Shader.js

@@ -27,7 +27,14 @@
  *
  * The x scale's params reach passes 1 and 2 as immediates, pushed before each
  * dispatch, rather than as an index into the global scale table.
+ *
+ * Every pass reads and writes the data through u32 views. NaN (a null, or an
+ * empty bin) is found by its bit pattern and moved as bits, never compared as
+ * a float: Metal compilers may fold `x != x` to false (see NanShaderLib), and
+ * where they do, compaction keeps the empty bins and the line loses every
+ * segment that touches one.
  */
+import { NAN_WGSL } from '../NanShaderLib';
 const WORKGROUP_SIZE = 256;
 /**
  * Shared type definitions used across all kernels.
@@ -53,10 +60,11 @@ struct M4Bin {
 	maxYIdx: atomic<u32>,
 };
 
-fn floatToSortableUint(f: f32) -> u32 {
-	let bits = bitcast<u32>(f);
+fn sortableFromBits(bits: u32) -> u32 {
 	return select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);
 }
+
+${NAN_WGSL}
 `;
 /** Bytes of immediate data passes 1 and 2 read: one ScaleParam. */
 const X_SCALE_IMMEDIATE_SIZE = 16;
@@ -135,9 +143,9 @@ requires immediate_address_space;
 ${SHARED_TYPES}
 ${X_SCALE_IMMEDIATE}
 
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;
 @group(0) @binding(4) var<uniform> config: M4Config;
 @group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
@@ -150,11 +158,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let idx = gid.x;
 	if (idx >= config.pointCount) { return; }
 
-	let x = xValues[idx];
-	let y = yValues[idx];
-
-	// Skip NaN points
-	if (x != x || y != y) { return; }
+	// Skip NaN points, tested on the bits before either becomes a float
+	let xb = xBits[idx];
+	let yb = yBits[idx];
+	if (isNanBits(xb) || isNanBits(yb)) { return; }
+	let x = bitcast<f32>(xb);
 
 	let domainMin = xScale.p1;
 	let domainMax = xScale.p2;
@@ -162,8 +170,10 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let t = (x - domainMin) / (domainMax - domainMin);
 
 	// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)
-	let seriesF = seriesValues[idx];
-	if (seriesF < 0.0 || seriesF != seriesF) { return; }
+	let seriesB = seriesBits[idx];
+	if (isNanBits(seriesB)) { return; }
+	let seriesF = bitcast<f32>(seriesB);
+	if (seriesF < 0.0) { return; }
 	let series = u32(seriesF);
 	if (series >= config.numSeries) { return; }
 
@@ -183,7 +193,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	atomicMin(&bins[binKey].firstIdx, idx);
 	atomicMax(&bins[binKey].lastIdx, idx);
 
-	let ySortable = floatToSortableUint(y);
+	let ySortable = sortableFromBits(yb);
 	atomicMin(&bins[binKey].minYSortable, ySortable);
 	atomicMax(&bins[binKey].maxYSortable, ySortable);
 }
@@ -204,9 +214,9 @@ requires immediate_address_space;
 ${SHARED_TYPES}
 ${X_SCALE_IMMEDIATE}
 
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;
 @group(0) @binding(4) var<uniform> config: M4Config;
 @group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
@@ -218,10 +228,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let idx = gid.x;
 	if (idx >= config.pointCount) { return; }
 
-	let x = xValues[idx];
-	let y = yValues[idx];
-
-	if (x != x || y != y) { return; }
+	// NaN skip on the bits (matches binPoints pass)
+	let xb = xBits[idx];
+	let yb = yBits[idx];
+	if (isNanBits(xb) || isNanBits(yb)) { return; }
+	let x = bitcast<f32>(xb);
 
 	let domainMin = xScale.p1;
 	let domainMax = xScale.p2;
@@ -229,8 +240,10 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let t = (x - domainMin) / (domainMax - domainMin);
 
 	// Series: 0-indexed (matches binPoints pass)
-	let seriesF = seriesValues[idx];
-	if (seriesF < 0.0 || seriesF != seriesF) { return; }
+	let seriesB = seriesBits[idx];
+	if (isNanBits(seriesB)) { return; }
+	let seriesF = bitcast<f32>(seriesB);
+	if (seriesF < 0.0) { return; }
 	let series = u32(seriesF);
 	if (series >= config.numSeries) { return; }
 
@@ -246,7 +259,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	}
 	let binKey = series * config.numBins + bin;
 
-	let ySortable = floatToSortableUint(y);
+	let ySortable = sortableFromBits(yb);
 
 	if (ySortable == atomicLoad(&bins[binKey].minYSortable)) {
 		atomicMin(&bins[binKey].minYIdx, idx);
@@ -275,15 +288,15 @@ ${SHARED_TYPES}
 
 // Note: seriesValues not bound here — series is derived from binKey / numBins.
 // This keeps total storage buffers within WebGPU default limit.
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> colorValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> colorBits: array<u32>;
 @group(0) @binding(3) var<uniform> config: M4Config;
 @group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;
-@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;
-@group(1) @binding(2) var<storage, read_write> seriesOut: array<f32>;
-@group(1) @binding(3) var<storage, read_write> colorOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;
+@group(1) @binding(2) var<storage, read_write> seriesOut: array<u32>;
+@group(1) @binding(3) var<storage, read_write> colorOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
@@ -294,16 +307,13 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let outBase = binKey * 4u;
 	let firstIdx = atomicLoad(&bins[binKey].firstIdx);
 
-	// Empty bin: write NaN to all 4 output slots
-	// Use var to avoid const-expression NaN (WGSL disallows NaN in const context)
+	// Empty bin: NaN in all 4 output slots, written as bits
 	if (firstIdx == 0xFFFFFFFFu) {
-		var nanBits = 0x7FC00000u;
-		let nan = bitcast<f32>(nanBits);
 		for (var i = 0u; i < 4u; i++) {
-			xOut[outBase + i] = nan;
-			yOut[outBase + i] = nan;
-			seriesOut[outBase + i] = nan;
-			colorOut[outBase + i] = nan;
+			xOut[outBase + i] = NAN_BITS;
+			yOut[outBase + i] = NAN_BITS;
+			seriesOut[outBase + i] = NAN_BITS;
+			colorOut[outBase + i] = NAN_BITS;
 		}
 		return;
 	}
@@ -350,15 +360,16 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 
 	// Derive series value from bin key (0-indexed, matching ViewManager convention).
 	// Vertex shader uses != comparison for series breaks, so any distinct values work.
-	let seriesVal = f32(binKey / config.numBins);
+	let seriesVal = bitcast<u32>(f32(binKey / config.numBins));
 
-	// Write unique points, fill remaining slots with last unique point
+	// Write unique points, fill remaining slots with last unique point.
+	// Copied as bits, so a value arrives exactly as it left.
 	for (var i = 0u; i < 4u; i++) {
 		let srcIdx = indices[min(i, count - 1u)];
-		xOut[outBase + i] = xValues[srcIdx];
-		yOut[outBase + i] = yValues[srcIdx];
+		xOut[outBase + i] = xBits[srcIdx];
+		yOut[outBase + i] = yBits[srcIdx];
 		seriesOut[outBase + i] = seriesVal;
-		colorOut[outBase + i] = colorValues[srcIdx];
+		colorOut[outBase + i] = colorBits[srcIdx];
 	}
 }
 `;
@@ -391,11 +402,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
+${NAN_WGSL}
+
 @group(0) @binding(0) var<uniform> config: M4Config;
-@group(0) @binding(1) var<storage, read_write> xOut: array<f32>;
-@group(0) @binding(2) var<storage, read_write> yOut: array<f32>;
-@group(0) @binding(3) var<storage, read_write> seriesOut: array<f32>;
-@group(0) @binding(4) var<storage, read_write> colorOut: array<f32>;
+@group(0) @binding(1) var<storage, read_write> xOut: array<u32>;
+@group(0) @binding(2) var<storage, read_write> yOut: array<u32>;
+@group(0) @binding(3) var<storage, read_write> seriesOut: array<u32>;
+@group(0) @binding(4) var<storage, read_write> colorOut: array<u32>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
 
 @compute @workgroup_size(1)
@@ -409,14 +422,15 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let end = start + 4u * config.numBins;
 
 	// Pack non-NaN points to the front, skipping consecutive duplicates.
+	// All on bits: NaN by its pattern, duplicates by identical bits. lastX
+	// starts as NaN, which no kept x can equal.
 	var writeIdx = start;
-	var nanBits = 0x7FC00000u;
-	var lastX: f32 = bitcast<f32>(nanBits);
-	var lastY: f32 = bitcast<f32>(nanBits);
+	var lastX = NAN_BITS;
+	var lastY = NAN_BITS;
 
 	for (var i = start; i < end; i++) {
 		let x = xOut[i];
-		if (x != x) { continue; }
+		if (isNanBits(x)) { continue; }
 		let y = yOut[i];
 		if (x == lastX && y == lastY) { continue; }
 
@@ -432,12 +446,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	}
 
 	// NaN-pad remaining slots
-	let nan = bitcast<f32>(nanBits);
 	for (var i = writeIdx; i < end; i++) {
-		xOut[i] = nan;
-		yOut[i] = nan;
-		seriesOut[i] = nan;
-		colorOut[i] = nan;
+		xOut[i] = NAN_BITS;
+		yOut[i] = NAN_BITS;
+		seriesOut[i] = NAN_BITS;
+		colorOut[i] = NAN_BITS;
 	}
 
 	// Instance count is set by pass 0 (outputSize) — compact only reorganizes
@@ -469,12 +482,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
-@group(0) @binding(0) var<storage, read> xIn: array<f32>;
-@group(0) @binding(1) var<storage, read> yIn: array<f32>;
+// Copied as bits, so a null's NaN arrives exactly as it left.
+@group(0) @binding(0) var<storage, read> xIn: array<u32>;
+@group(0) @binding(1) var<storage, read> yIn: array<u32>;
 @group(0) @binding(2) var<uniform> config: M4Config;
 @group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;
-@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
@@ -517,12 +531,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
-@group(0) @binding(0) var<storage, read> seriesIn: array<f32>;
-@group(0) @binding(1) var<storage, read> colorIn: array<f32>;
+// Copied as bits, like pass 5a.
+@group(0) @binding(0) var<storage, read> seriesIn: array<u32>;
+@group(0) @binding(1) var<storage, read> colorIn: array<u32>;
 @group(0) @binding(2) var<uniform> config: M4Config;
 @group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;
-@group(1) @binding(0) var<storage, read_write> seriesOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> colorOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> seriesOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> colorOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {