@celox-sim/celox 0.1.13 → 0.1.15
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/dut.d.ts +1 -1
- package/dist/dut.d.ts.map +1 -1
- package/dist/dut.js +23 -10
- package/dist/dut.js.map +1 -1
- package/dist/index.d.ts +8 -10
- package/dist/index.d.ts.map +1 -1
- package/dist/index.js +9 -10
- package/dist/index.js.map +1 -1
- package/dist/napi-bridge.d.ts +1 -1
- package/dist/napi-bridge.d.ts.map +1 -1
- package/dist/napi-bridge.js +1 -1
- package/dist/napi-bridge.js.map +1 -1
- package/dist/napi-helpers.d.ts +17 -4
- package/dist/napi-helpers.d.ts.map +1 -1
- package/dist/napi-helpers.js +36 -4
- package/dist/napi-helpers.js.map +1 -1
- package/dist/simulation.d.ts +2 -2
- package/dist/simulation.d.ts.map +1 -1
- package/dist/simulation.js +30 -14
- package/dist/simulation.js.map +1 -1
- package/dist/simulator.d.ts +2 -2
- package/dist/simulator.d.ts.map +1 -1
- package/dist/simulator.js +29 -13
- package/dist/simulator.js.map +1 -1
- package/dist/types.d.ts +12 -3
- package/dist/types.d.ts.map +1 -1
- package/dist/types.js.map +1 -1
- package/package.json +2 -2
- package/src/dut.test.ts +1037 -742
- package/src/dut.ts +580 -528
- package/src/e2e.bench.ts +512 -509
- package/src/e2e.test.ts +2056 -1574
- package/src/index.ts +47 -46
- package/src/matchers.ts +81 -81
- package/src/napi-bridge.ts +5 -5
- package/src/napi-helpers.ts +498 -400
- package/src/simulation.test.ts +395 -368
- package/src/simulation.ts +509 -430
- package/src/simulator.test.ts +201 -168
- package/src/simulator.ts +328 -267
- package/src/types.ts +108 -98
package/src/types.ts
CHANGED
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@@ -11,6 +11,12 @@
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// Module definition (produced by Stream A's `celox-gen-ts`)
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// ---------------------------------------------------------------------------
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/** A source file with its path and content. */
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export interface SourceFile {
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readonly path: string;
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readonly content: string;
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}
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/**
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* A compiled module descriptor emitted by `celox-gen-ts`.
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* The type parameter `Ports` carries the generated port interface
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* a correctly-typed DUT accessor.
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*/
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export interface ModuleDefinition<Ports = Record<string, unknown>> {
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readonly __celox_module: true;
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readonly name: string;
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readonly sources: ReadonlyArray<SourceFile>;
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readonly ports: Record<string, PortInfo>;
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readonly events: string[];
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/** Absolute path to the Veryl project directory (set by Vite plugin). */
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readonly projectPath?: string;
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/** Default options baked in by the Vite plugin (e.g. via `?dse=` query). */
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readonly defaultOptions?: SimulatorOptions;
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/** Phantom field — never set at runtime. Carries the `Ports` type. */
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readonly __ports?: Ports;
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}
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/** Metadata for a single port / interface member. */
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export interface PortInfo {
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readonly direction: "input" | "output" | "inout" | "internal";
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readonly type: "clock" | "reset" | "logic" | "bit";
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readonly width: number;
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readonly arrayDims?: readonly number[];
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readonly is4state?: boolean;
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/** Nested interface members (recursive). */
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readonly interface?: Record<string, PortInfo>;
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}
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// ---------------------------------------------------------------------------
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@@ -49,19 +57,19 @@ export interface PortInfo {
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* @internal
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*/
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export interface SignalLayout {
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/** Byte offset within the STABLE region. */
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readonly offset: number;
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/** Bit width of the signal. */
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readonly width: number;
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/** Number of bytes occupied (ceil(width/8)). */
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readonly byteSize: number;
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/** If true, an equal-sized mask follows immediately after the value. */
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readonly is4state: boolean;
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readonly direction: "input" | "output" | "inout" | "internal";
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/** The Veryl type kind (e.g. "clock", "reset_async_high", "logic"). */
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readonly typeKind?: string;
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/** For reset signals, the name of the associated clock (from FfDeclaration). */
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readonly associatedClock?: string;
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}
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// ---------------------------------------------------------------------------
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* @internal
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*/
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export interface NativeSimulatorHandle {
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tick(eventId: number): void;
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tickN(eventId: number, count: number): void;
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evalComb(): void;
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dump(timestamp: number): void;
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dispose(): void;
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}
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/**
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* @internal
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*/
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export interface NativeSimulationHandle {
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addClock(eventId: number, period: number, initialDelay: number): void;
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schedule(eventId: number, time: number, value: number): void;
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runUntil(endTime: number): void;
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step(): number | null;
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time(): number;
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nextEventTime(): number | null;
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evalComb(): void;
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dump(timestamp: number): void;
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dispose(): void;
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}
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/**
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* @internal
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*/
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export interface CreateResult<H extends NativeHandle = NativeHandle> {
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/** The simulator's internal memory buffer shared zero-copy. */
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readonly buffer: ArrayBuffer | SharedArrayBuffer;
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/** Per-signal byte layout within `buffer`. */
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readonly layout: Record<string, SignalLayout>;
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/** Event name → internal event ID mapping. */
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readonly events: Record<string, number>;
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/** Native control handle. */
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readonly handle: H;
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/** Full instance hierarchy (optional — present when NAPI provides it). */
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readonly hierarchy?: import("./napi-helpers.js").HierarchyNode;
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}
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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export interface SimulatorOptions {
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/** Enable 4-state (X) simulation. Default: false. */
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fourState?: boolean;
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/** Path to write VCD waveform output. */
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vcd?: string;
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/** Enable Cranelift optimization passes. */
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optimize?: boolean;
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/** False-loop declarations to ignore during compilation. */
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falseLoops?: LoopBreak[];
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/** True-loop declarations with convergence limits. */
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trueLoops?: TrueLoopSpec[];
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/** Clock polarity. Default: "posedge". */
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clockType?: "posedge" | "negedge";
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/** Reset type. Default: "async_low". */
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resetType?: "async_high" | "async_low" | "sync_high" | "sync_low";
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/** Additional Veryl source to append to the main source code. */
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extraSource?: string;
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/** Top-level module parameter overrides. */
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parameters?: ParamOverride[];
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/** Dead store elimination policy. Default: "off". */
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deadStorePolicy?: "off" | "preserveTopPorts" | "preserveAllPorts";
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}
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/** A parameter override for a top-level module parameter. */
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export interface ParamOverride {
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name: string;
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value: number | bigint;
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}
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/** A resolved event reference for use with `tick()`. */
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export interface EventHandle {
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readonly name: string;
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readonly id: number;
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}
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/** A 4-state value with explicit bit-level mask. */
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export interface FourStateValue {
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readonly __fourState: true;
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readonly value: bigint;
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readonly mask: bigint;
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}
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/** Construct a 4-state value. Mask bits set to 1 indicate X. */
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export function FourState(
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value: number | bigint,
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mask: number | bigint,
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): FourStateValue {
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return { __fourState: true, value: BigInt(value), mask: BigInt(mask) };
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}
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export function isFourStateValue(v: unknown): v is FourStateValue {
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* Thrown when a simulation helper exceeds its step budget.
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*/
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export class SimulationTimeoutError extends Error {
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readonly time: number;
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readonly steps: number;
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constructor(message: string, time: number, steps: number) {
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super(message);
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this.name = "SimulationTimeoutError";
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this.time = time;
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this.steps = steps;
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}
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/** Specifies a false-loop to ignore during compilation. */
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export interface LoopBreak {
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/** Specifies a true-loop with a convergence iteration limit. */
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export interface TrueLoopSpec extends LoopBreak {
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maxIter: number;
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}
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