@aardworx/wombat.rendering 0.9.17 → 0.9.19

package/dist/core/renderObject.d.ts

@@ -54,5 +54,24 @@ export interface RenderObject {
     /** Index buffer for indexed draws. */
     readonly indices?: BufferView;
     readonly drawCall: aval<DrawCall>;
+    /**
+     * Per-axis derived-mode rules — `(u, declared) => modeValue`
+     * closures evaluated against this RO's uniforms at scene-build
+     * (and on reactive marks). See
+     * `@aardworx/wombat.rendering/runtime` — `derivedMode(...)`.
+     *
+     * A rule overrides the corresponding `pipelineState.rasterizer.*`
+     * (or `pipelineState.depth.*`) aval value. v1 evaluates rules
+     * CPU-side; v2 (deferred) lowers them to a GPU compute kernel.
+     * See `docs/derived-modes.md`.
+     */
+    readonly modeRules?: {
+        readonly cull?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"cull">;
+        readonly frontFace?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"frontFace">;
+        readonly topology?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"topology">;
+        readonly depthCompare?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"depthCompare">;
+        readonly depthWrite?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"depthWrite">;
+        readonly alphaToCoverage?: import("../runtime/derivedModes/rule.js").DerivedModeRule<"alphaToCoverage">;
+    };
 }
 //# sourceMappingURL=renderObject.d.ts.map

package/dist/core/renderObject.d.ts.map

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package/dist/runtime/derivedModes/gpuDispatcher.d.ts

@@ -0,0 +1,46 @@
+import type { CullMode } from "../pipelineCache/index.js";
+export declare class GpuDerivedModesScene {
+    readonly device: GPUDevice;
+    private readonly entries;
+    private liveCount;
+    private dirty;
+    private inputBuf;
+    private outputBuf;
+    private stagingBuf;
+    private paramsBuf;
+    private pipeline;
+    private bindGroup;
+    private layout;
+    /** Capacity in number of u32 entries (= numROs the buffers can hold). */
+    private capacity;
+    /** Last-known arena buffer, used to detect bind-group invalidation. */
+    private arenaBuf;
+    /** Last-known declared (for kernel uniform). Common case: all RO
+     *  rules share the same declared (= the SG scope's value). */
+    private declared;
+    /** Per-RO last-known output. CPU mirror, populated by finish(). */
+    readonly lastOutput: Uint32Array;
+    constructor(device: GPUDevice);
+    get registered(): number;
+    registerRo(drawId: number, modelRef: number, declared: CullMode): void;
+    deregisterRo(drawId: number): void;
+    markDirty(): void;
+    consumeDirty(): boolean;
+    private ensureResources;
+    /** Upload current per-RO input refs + params; called when dirty. */
+    private uploadInputs;
+    /**
+     * Encode the compute dispatch + the staging copy into `enc`. Caller
+     * is responsible for `device.queue.submit([enc.finish()])`. Returns
+     * the number of ROs the kernel was dispatched against.
+     */
+    dispatch(arenaBuf: GPUBuffer, numROs: number, enc: GPUCommandEncoder): number;
+    /**
+     * mapAsync the staging buffer + copy values into `lastOutput`.
+     * Resolves on the GPU finishing the copy. Caller diffs lastOutput
+     * against its own cached values to find changed ROs.
+     */
+    finish(numROs: number): Promise<void>;
+    dispose(): void;
+}
+//# sourceMappingURL=gpuDispatcher.d.ts.map

package/dist/runtime/derivedModes/gpuDispatcher.d.ts.map

@@ -0,0 +1 @@
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package/dist/runtime/derivedModes/gpuDispatcher.js

@@ -0,0 +1,170 @@
+// Scene-level dispatcher for the v1 GPU-evaluated derived-mode rule
+// (flip-cull-by-determinant; see ./gpuKernel.ts).
+//
+// Lifecycle
+// =========
+//
+//   - Construct once per heap scene with the device.
+//   - registerRo(drawId, modelRef, declaredCull): register an RO that
+//     has the GPU flip-cull rule. modelRef = byte offset into the
+//     arena where the RO's ModelTrafo mat4 lives.
+//   - deregisterRo(drawId): unregister on removeDraw.
+//   - markDirty(): caller hints that an input changed; the next
+//     `dispatch()` will run the kernel.
+//   - dispatch(arenaBuf, enc): if dirty, encode the compute pass into
+//     `enc`. Always copies the output buffer into a staging buffer for
+//     CPU readback.
+//   - finish(): mapAsync the staging buffer and resolve with the
+//     per-RO output array. The scene calls this AFTER submit and
+//     before deciding rebuckets. The promise resolves on the next
+//     microtask after the GPU completes the copy.
+//
+// The buffers grow lazily (pow2) as ROs are added.
+import { GPU_FLIP_CULL_BY_DET_WGSL, CULL_TO_U32 } from "./gpuKernel.js";
+const NO_RULE = 0xFFFFFFFF;
+const WG_SIZE = 64;
+const POW2 = (n) => { let p = 1; while (p < n)
+    p <<= 1; return Math.max(64, p); };
+export class GpuDerivedModesScene {
+    device;
+    entries = [];
+    liveCount = 0;
+    dirty = false;
+    // GPU resources — lazily allocated on first registerRo.
+    inputBuf = null;
+    outputBuf = null;
+    stagingBuf = null;
+    paramsBuf = null;
+    pipeline = null;
+    bindGroup = null;
+    layout = null;
+    /** Capacity in number of u32 entries (= numROs the buffers can hold). */
+    capacity = 0;
+    /** Last-known arena buffer, used to detect bind-group invalidation. */
+    arenaBuf = null;
+    /** Last-known declared (for kernel uniform). Common case: all RO
+     *  rules share the same declared (= the SG scope's value). */
+    declared = CULL_TO_U32.back;
+    /** Per-RO last-known output. CPU mirror, populated by finish(). */
+    lastOutput;
+    constructor(device) {
+        this.device = device;
+        this.lastOutput = new Uint32Array(0);
+    }
+    get registered() { return this.liveCount; }
+    registerRo(drawId, modelRef, declared) {
+        this.entries[drawId] = { modelRef, declaredU32: CULL_TO_U32[declared] };
+        this.liveCount++;
+        this.dirty = true;
+        this.declared = CULL_TO_U32[declared];
+    }
+    deregisterRo(drawId) {
+        if (this.entries[drawId] === undefined)
+            return;
+        this.entries[drawId] = undefined;
+        this.liveCount--;
+        this.dirty = true;
+    }
+    markDirty() { this.dirty = true; }
+    consumeDirty() { const was = this.dirty; this.dirty = false; return was; }
+    ensureResources(arenaBuf, numROs) {
+        const needCap = POW2(Math.max(1, numROs));
+        if (this.outputBuf === null || needCap > this.capacity) {
+            this.inputBuf?.destroy();
+            this.outputBuf?.destroy();
+            this.stagingBuf?.destroy();
+            const bytes = needCap * 4;
+            this.inputBuf = this.device.createBuffer({ size: bytes, usage: GPUBufferUsage.STORAGE | GPUBufferUsage.COPY_DST, label: "gpuDerivedModes/in" });
+            this.outputBuf = this.device.createBuffer({ size: bytes, usage: GPUBufferUsage.STORAGE | GPUBufferUsage.COPY_SRC | GPUBufferUsage.COPY_DST, label: "gpuDerivedModes/out" });
+            this.stagingBuf = this.device.createBuffer({ size: bytes, usage: GPUBufferUsage.MAP_READ | GPUBufferUsage.COPY_DST, label: "gpuDerivedModes/staging" });
+            this.lastOutput = new Uint32Array(needCap);
+            this.capacity = needCap;
+            this.bindGroup = null;
+        }
+        if (this.paramsBuf === null) {
+            this.paramsBuf = this.device.createBuffer({ size: 16, usage: GPUBufferUsage.UNIFORM | GPUBufferUsage.COPY_DST, label: "gpuDerivedModes/params" });
+        }
+        if (this.layout === null) {
+            this.layout = this.device.createBindGroupLayout({
+                label: "gpuDerivedModes/bgl",
+                entries: [
+                    { binding: 0, visibility: GPUShaderStage.COMPUTE, buffer: { type: "read-only-storage" } },
+                    { binding: 1, visibility: GPUShaderStage.COMPUTE, buffer: { type: "read-only-storage" } },
+                    { binding: 2, visibility: GPUShaderStage.COMPUTE, buffer: { type: "storage" } },
+                    { binding: 3, visibility: GPUShaderStage.COMPUTE, buffer: { type: "uniform" } },
+                ],
+            });
+        }
+        if (this.pipeline === null) {
+            const module = this.device.createShaderModule({ code: GPU_FLIP_CULL_BY_DET_WGSL, label: "gpuDerivedModes/module" });
+            this.pipeline = this.device.createComputePipeline({
+                label: "gpuDerivedModes/pipeline",
+                layout: this.device.createPipelineLayout({ bindGroupLayouts: [this.layout] }),
+                compute: { module, entryPoint: "evaluate" },
+            });
+        }
+        if (this.bindGroup === null || this.arenaBuf !== arenaBuf) {
+            this.bindGroup = this.device.createBindGroup({
+                label: "gpuDerivedModes/bindGroup",
+                layout: this.layout,
+                entries: [
+                    { binding: 0, resource: { buffer: arenaBuf } },
+                    { binding: 1, resource: { buffer: this.inputBuf } },
+                    { binding: 2, resource: { buffer: this.outputBuf } },
+                    { binding: 3, resource: { buffer: this.paramsBuf } },
+                ],
+            });
+            this.arenaBuf = arenaBuf;
+        }
+    }
+    /** Upload current per-RO input refs + params; called when dirty. */
+    uploadInputs(numROs) {
+        const refs = new Uint32Array(this.capacity).fill(NO_RULE);
+        for (let i = 0; i < numROs; i++) {
+            const e = this.entries[i];
+            if (e !== undefined)
+                refs[i] = e.modelRef;
+        }
+        this.device.queue.writeBuffer(this.inputBuf, 0, refs.buffer, refs.byteOffset, refs.byteLength);
+        const params = new Uint32Array([numROs, this.declared, 0, 0]);
+        this.device.queue.writeBuffer(this.paramsBuf, 0, params.buffer, params.byteOffset, params.byteLength);
+    }
+    /**
+     * Encode the compute dispatch + the staging copy into `enc`. Caller
+     * is responsible for `device.queue.submit([enc.finish()])`. Returns
+     * the number of ROs the kernel was dispatched against.
+     */
+    dispatch(arenaBuf, numROs, enc) {
+        this.ensureResources(arenaBuf, numROs);
+        this.uploadInputs(numROs);
+        const pass = enc.beginComputePass({ label: "gpuDerivedModes/pass" });
+        pass.setPipeline(this.pipeline);
+        pass.setBindGroup(0, this.bindGroup);
+        pass.dispatchWorkgroups(Math.ceil(numROs / WG_SIZE));
+        pass.end();
+        const bytes = numROs * 4;
+        enc.copyBufferToBuffer(this.outputBuf, 0, this.stagingBuf, 0, bytes);
+        return numROs;
+    }
+    /**
+     * mapAsync the staging buffer + copy values into `lastOutput`.
+     * Resolves on the GPU finishing the copy. Caller diffs lastOutput
+     * against its own cached values to find changed ROs.
+     */
+    async finish(numROs) {
+        if (this.stagingBuf === null || numROs === 0)
+            return;
+        const bytes = numROs * 4;
+        await this.stagingBuf.mapAsync(GPUMapMode.READ, 0, bytes);
+        const view = new Uint32Array(this.stagingBuf.getMappedRange(0, bytes).slice(0));
+        this.stagingBuf.unmap();
+        this.lastOutput.set(view, 0);
+    }
+    dispose() {
+        this.inputBuf?.destroy();
+        this.outputBuf?.destroy();
+        this.stagingBuf?.destroy();
+        this.paramsBuf?.destroy();
+    }
+}
+//# sourceMappingURL=gpuDispatcher.js.map

package/dist/runtime/derivedModes/gpuDispatcher.js.map

@@ -0,0 +1 @@
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package/dist/runtime/derivedModes/gpuKernel.d.ts

@@ -0,0 +1,9 @@
+export declare const GPU_FLIP_CULL_BY_DET_WGSL = "\n// Per-RO record. Index i corresponds to drawId i in the scene's\n// flat RO table.\nstruct GpuRuleParams {\n  numROs:     u32,\n  declared:   u32,   // 0 = none, 1 = front, 2 = back  (must match CULL_MODE[] order in bitfield.ts)\n  _pad0:      u32,\n  _pad1:      u32,\n};\n\n@group(0) @binding(0) var<storage, read>       arena:        array<u32>;\n// One per-RO entry: byte offset within the arena of the ROs ModelTrafo\n// allocation header. Data is at offset + 16 (ALLOC_HEADER_PAD_TO).\n// 0xFFFFFFFFu means \"this RO does NOT have a flip-cull-by-det rule\".\n@group(0) @binding(1) var<storage, read>       roInputRefs:  array<u32>;\n@group(0) @binding(2) var<storage, read_write> roOutputs:    array<u32>;\n@group(0) @binding(3) var<uniform>             uIn:          GpuRuleParams;\n\n// Read a row-major mat4 from the arena at byte offset `refBytes + 16`\n// (header is 16 bytes wide due to ALLOC_HEADER_PAD_TO). Returns the\n// 3\u00D73 upper-left in row-major order: [m00,m01,m02, m10,m11,m12, m20,m21,m22].\nfn loadUpper3x3(refBytes: u32) -> array<f32, 9> {\n  let baseU32 = (refBytes + 16u) >> 2u;\n  // The arena is a Float32 storage of mat4 in row-major, 16 floats.\n  // Read 9 of them.\n  return array<f32, 9>(\n    bitcast<f32>(arena[baseU32 + 0u]),  bitcast<f32>(arena[baseU32 + 1u]),  bitcast<f32>(arena[baseU32 + 2u]),\n    bitcast<f32>(arena[baseU32 + 4u]),  bitcast<f32>(arena[baseU32 + 5u]),  bitcast<f32>(arena[baseU32 + 6u]),\n    bitcast<f32>(arena[baseU32 + 8u]),  bitcast<f32>(arena[baseU32 + 9u]),  bitcast<f32>(arena[baseU32 + 10u]),\n  );\n}\n\nfn det3x3(m: array<f32, 9>) -> f32 {\n  return m[0] * (m[4] * m[8] - m[5] * m[7])\n       - m[1] * (m[3] * m[8] - m[5] * m[6])\n       + m[2] * (m[3] * m[7] - m[4] * m[6]);\n}\n\n// Mirror of bitfield.ts CULL_MODE[] order: 0=none, 1=front, 2=back.\nfn flipCull(c: u32) -> u32 {\n  if (c == 1u) { return 2u; } // front -> back\n  if (c == 2u) { return 1u; } // back  -> front\n  return c;                   // none\n}\n\n@compute @workgroup_size(64)\nfn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {\n  let i = gid.x;\n  if (i >= uIn.numROs) { return; }\n  let ref = roInputRefs[i];\n  if (ref == 0xFFFFFFFFu) {\n    // No rule on this RO; leave existing output untouched. Allows a\n    // single kernel dispatch to skip non-participating ROs.\n    return;\n  }\n  let m = loadUpper3x3(ref);\n  let d = det3x3(m);\n  let declared = uIn.declared;\n  let outVal = select(declared, flipCull(declared), d < 0.0);\n  roOutputs[i] = outVal;\n}\n";
+/** Map between bitfield.ts's CULL_MODE order and the kernel's u32 enum. */
+export declare const CULL_TO_U32: {
+    readonly none: 0;
+    readonly front: 1;
+    readonly back: 2;
+};
+export declare const U32_TO_CULL: readonly ["none", "front", "back"];
+//# sourceMappingURL=gpuKernel.d.ts.map

package/dist/runtime/derivedModes/gpuKernel.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"gpuKernel.d.ts","sourceRoot":"","sources":["../../../src/runtime/derivedModes/gpuKernel.ts"],"names":[],"mappings":"AAgCA,eAAO,MAAM,yBAAyB,s+EA6DrC,CAAC;AAEF,2EAA2E;AAC3E,eAAO,MAAM,WAAW;;;;CAAgD,CAAC;AACzE,eAAO,MAAM,WAAW,oCAAqC,CAAC"}

package/dist/runtime/derivedModes/gpuKernel.js

@@ -0,0 +1,97 @@
+// GPU-evaluated derived-mode rules — minimum viable kernel.
+//
+// CPU eval (Task 2 Phase 1-3, 0.9.17) runs rule closures in JS. For
+// rules whose inputs live GPU-side (per-RO trafos, etc.) JS evaluation
+// fans out CPU work that's wasted: the trafo bytes are right there in
+// the arena. This module runs the rule on the GPU instead, in one
+// dispatch over all dirty ROs per frame.
+//
+// v1 scope is deliberately narrow: ONE hard-coded WGSL kernel for
+// "flip cullMode by sign of det(upper3x3 of an arena mat4)". Picked
+// because it's the motivating case from docs/derived-modes.md and
+// proves the GPU-eval path end-to-end. Generalizes via a traced IR
+// builder in v2 (see derived-mode-rules-plan.md Phase 5).
+//
+// Architecture
+// ============
+//
+//   - One **module-wide** `GpuDerivedModesScene` per heap scene. Holds:
+//       * `roOutputBuf`  — `array<u32>` sized to scene.numROs.
+//                          Each entry = the rule's modeKey contribution.
+//       * `roInputBuf`   — `array<u32>` (one ref-into-arena per RO)
+//                          telling the kernel where to read the input.
+//       * `stagingBuf`   — MAP_READ + COPY_DST mirror of roOutputBuf,
+//                          for the per-frame readback.
+//   - Dispatch each frame in `update()`, ONLY when something dirty.
+//   - `mapAsync(staging)` resolves on a microtask; the CPU diffs the
+//     buffer against `roLastKey[]`. Any change → mark drawId dirty;
+//     the existing rebucket flow does the rest.
+//
+// The dirty gate keeps steady-state cost ≈ 0 — when no input aval
+// marks AND no RO add/remove, we skip the dispatch + readback.
+export const GPU_FLIP_CULL_BY_DET_WGSL = /* wgsl */ `
+// Per-RO record. Index i corresponds to drawId i in the scene's
+// flat RO table.
+struct GpuRuleParams {
+  numROs:     u32,
+  declared:   u32,   // 0 = none, 1 = front, 2 = back  (must match CULL_MODE[] order in bitfield.ts)
+  _pad0:      u32,
+  _pad1:      u32,
+};
+
+@group(0) @binding(0) var<storage, read>       arena:        array<u32>;
+// One per-RO entry: byte offset within the arena of the ROs ModelTrafo
+// allocation header. Data is at offset + 16 (ALLOC_HEADER_PAD_TO).
+// 0xFFFFFFFFu means "this RO does NOT have a flip-cull-by-det rule".
+@group(0) @binding(1) var<storage, read>       roInputRefs:  array<u32>;
+@group(0) @binding(2) var<storage, read_write> roOutputs:    array<u32>;
+@group(0) @binding(3) var<uniform>             uIn:          GpuRuleParams;
+
+// Read a row-major mat4 from the arena at byte offset \`refBytes + 16\`
+// (header is 16 bytes wide due to ALLOC_HEADER_PAD_TO). Returns the
+// 3×3 upper-left in row-major order: [m00,m01,m02, m10,m11,m12, m20,m21,m22].
+fn loadUpper3x3(refBytes: u32) -> array<f32, 9> {
+  let baseU32 = (refBytes + 16u) >> 2u;
+  // The arena is a Float32 storage of mat4 in row-major, 16 floats.
+  // Read 9 of them.
+  return array<f32, 9>(
+    bitcast<f32>(arena[baseU32 + 0u]),  bitcast<f32>(arena[baseU32 + 1u]),  bitcast<f32>(arena[baseU32 + 2u]),
+    bitcast<f32>(arena[baseU32 + 4u]),  bitcast<f32>(arena[baseU32 + 5u]),  bitcast<f32>(arena[baseU32 + 6u]),
+    bitcast<f32>(arena[baseU32 + 8u]),  bitcast<f32>(arena[baseU32 + 9u]),  bitcast<f32>(arena[baseU32 + 10u]),
+  );
+}
+
+fn det3x3(m: array<f32, 9>) -> f32 {
+  return m[0] * (m[4] * m[8] - m[5] * m[7])
+       - m[1] * (m[3] * m[8] - m[5] * m[6])
+       + m[2] * (m[3] * m[7] - m[4] * m[6]);
+}
+
+// Mirror of bitfield.ts CULL_MODE[] order: 0=none, 1=front, 2=back.
+fn flipCull(c: u32) -> u32 {
+  if (c == 1u) { return 2u; } // front -> back
+  if (c == 2u) { return 1u; } // back  -> front
+  return c;                   // none
+}
+
+@compute @workgroup_size(64)
+fn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {
+  let i = gid.x;
+  if (i >= uIn.numROs) { return; }
+  let ref = roInputRefs[i];
+  if (ref == 0xFFFFFFFFu) {
+    // No rule on this RO; leave existing output untouched. Allows a
+    // single kernel dispatch to skip non-participating ROs.
+    return;
+  }
+  let m = loadUpper3x3(ref);
+  let d = det3x3(m);
+  let declared = uIn.declared;
+  let outVal = select(declared, flipCull(declared), d < 0.0);
+  roOutputs[i] = outVal;
+}
+`;
+/** Map between bitfield.ts's CULL_MODE order and the kernel's u32 enum. */
+export const CULL_TO_U32 = { "none": 0, "front": 1, "back": 2 };
+export const U32_TO_CULL = ["none", "front", "back"];
+//# sourceMappingURL=gpuKernel.js.map

package/dist/runtime/derivedModes/gpuKernel.js.map

@@ -0,0 +1 @@
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package/dist/runtime/derivedModes/rule.d.ts

@@ -17,10 +17,28 @@ export type ModeValue<A extends ModeAxis> = A extends "cull" ? CullMode : A exte
  *     want to pass declared through unchanged.
  */
 export type DerivedModeBuilder<A extends ModeAxis> = (u: Record<string, unknown>, declared: ModeValue<A>) => ModeValue<A>;
+/**
+ * Opt-in GPU evaluation marker. When present on a rule, the heap
+ * scene runs a hard-coded WGSL kernel (see `./gpuKernel.ts`) instead
+ * of the CPU closure. The closure is retained for fallback (e.g.
+ * MockGPU tests, devices without compute, or before frame 0).
+ *
+ * v1 supports one kernel: `"flipCullByDeterminant"`. v2 generalizes
+ * via a traced IR builder.
+ */
+export interface GpuRuleSpec<A extends ModeAxis = ModeAxis> {
+    readonly kernel: "flipCullByDeterminant";
+    /** Name of the input uniform the kernel reads (e.g. "ModelTrafo"). */
+    readonly inputUniform: string;
+    /** Declared (SG-scope) value the kernel mutates by. */
+    readonly declared: ModeValue<A>;
+}
 export interface DerivedModeRule<A extends ModeAxis = ModeAxis> {
     readonly __derivedModeRule: true;
     readonly axis: A;
     readonly evaluate: DerivedModeBuilder<A>;
+    /** Opt-in GPU evaluation. Absent → CPU closure path. */
+    readonly gpu?: GpuRuleSpec<A>;
     /**
      * Conservative over-approximation of the rule's output set. Used by
      * the build-time pre-warm in v2 to enumerate the pipelines a scene
@@ -56,4 +74,19 @@ export declare function isDerivedModeRule(x: unknown): x is DerivedModeRule;
 /** Convenience: flip 'back' ↔ 'front' (and pass through 'none').
  *  Useful in `(u, declared) => mirrored ? flipCull(declared) : declared`. */
 export declare function flipCull(c: CullMode): CullMode;
+/**
+ * Construct a derived-mode rule that flips cullMode based on the sign
+ * of `det(upperLeft3x3(u.<inputUniform>))`. Runs on the GPU when
+ * heapScene's compute path is available; the same logic is mirrored
+ * in the CPU closure for tests and fallback.
+ *
+ *   const rule = gpuFlipCullByDeterminant("ModelTrafo", "back");
+ *   spec.modeRules = { cull: rule };
+ *
+ * Useful for mirrored geometry: scenes that animate a per-RO trafo
+ * with potentially-negative scale don't pay CPU per-RO determinant
+ * cost — the kernel walks the arena once per frame for ALL ROs that
+ * carry this rule.
+ */
+export declare function gpuFlipCullByDeterminant(inputUniform: string, declared?: CullMode): DerivedModeRule<"cull">;
 //# sourceMappingURL=rule.d.ts.map

package/dist/runtime/derivedModes/rule.d.ts.map

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package/dist/runtime/derivedModes/rule.js

@@ -52,4 +52,43 @@ export function isDerivedModeRule(x) {
 export function flipCull(c) {
     return c === "back" ? "front" : c === "front" ? "back" : "none";
 }
+/**
+ * Construct a derived-mode rule that flips cullMode based on the sign
+ * of `det(upperLeft3x3(u.<inputUniform>))`. Runs on the GPU when
+ * heapScene's compute path is available; the same logic is mirrored
+ * in the CPU closure for tests and fallback.
+ *
+ *   const rule = gpuFlipCullByDeterminant("ModelTrafo", "back");
+ *   spec.modeRules = { cull: rule };
+ *
+ * Useful for mirrored geometry: scenes that animate a per-RO trafo
+ * with potentially-negative scale don't pay CPU per-RO determinant
+ * cost — the kernel walks the arena once per frame for ALL ROs that
+ * carry this rule.
+ */
+export function gpuFlipCullByDeterminant(inputUniform, declared = "back") {
+    return {
+        __derivedModeRule: true,
+        axis: "cull",
+        domain: ["back", "front", "none"],
+        gpu: { kernel: "flipCullByDeterminant", inputUniform, declared },
+        evaluate: (u, declaredFromCtx) => {
+            const m = u[inputUniform];
+            // Accept Trafo3d ({forward: M44d}), M44 ({_data}), or row-major
+            // Float32Array. Reads upper-left 3x3.
+            const data = m.forward?._data ??
+                m._data ??
+                m;
+            if (data === undefined)
+                return declaredFromCtx;
+            const m00 = data[0], m01 = data[1], m02 = data[2];
+            const m10 = data[4], m11 = data[5], m12 = data[6];
+            const m20 = data[8], m21 = data[9], m22 = data[10];
+            const det = m00 * (m11 * m22 - m12 * m21)
+                - m01 * (m10 * m22 - m12 * m20)
+                + m02 * (m10 * m21 - m11 * m20);
+            return det < 0 ? flipCull(declaredFromCtx) : declaredFromCtx;
+        },
+    };
+}
 //# sourceMappingURL=rule.js.map

package/dist/runtime/derivedModes/rule.js.map

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package/dist/runtime/heapAdapter.d.ts.map

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package/dist/runtime/heapAdapter.js

@@ -304,6 +304,7 @@ export function renderObjectToHeapSpec(ro, token, pool) {
         ...(dc.instanceCount > 1 ? { instanceCount: dc.instanceCount } : {}),
         indices,
         ...(textures !== undefined ? { textures } : {}),
+        ...(ro.modeRules !== undefined ? { modeRules: ro.modeRules } : {}),
     };
 }
 //# sourceMappingURL=heapAdapter.js.map

package/dist/runtime/heapAdapter.js.map

@@ -1 +1 @@
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package/dist/runtime/heapScene.d.ts.map

@@ -1 +1 @@
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