wasmtime 24.0.0 → 25.0.1
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- checksums.yaml +4 -4
- data/Cargo.lock +112 -111
- data/ext/Cargo.toml +6 -6
- data/ext/cargo-vendor/cranelift-bforest-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.1/Cargo.toml +59 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.1/src/node.rs +806 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.1/src/path.rs +830 -0
- data/ext/cargo-vendor/cranelift-bforest-0.112.1/src/pool.rs +219 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.1/Cargo.toml +74 -0
- data/ext/cargo-vendor/cranelift-bitset-0.112.1/src/scalar.rs +626 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/Cargo.toml +222 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/build.rs +267 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/binemit/mod.rs +168 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/cfg_printer.rs +83 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/data_value.rs +402 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/dbg.rs +28 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/egraph.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/incremental_cache.rs +256 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/inst_predicates.rs +207 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/constant.rs +485 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/dfg.rs +1802 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/entities.rs +564 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/extfunc.rs +408 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/extname.rs +333 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/function.rs +500 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/globalvalue.rs +147 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/immediates.rs +1941 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/instructions.rs +1021 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/memtype.rs +190 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/progpoint.rs +75 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/trapcode.rs +148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/types.rs +624 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/ir/user_stack_maps.rs +199 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/abi.rs +1520 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/emit.rs +3567 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/emit_tests.rs +7972 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/imms.rs +1244 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/mod.rs +3051 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/regs.rs +269 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/inst.isle +4267 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/lower/isle.rs +811 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/lower.isle +2968 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/pcc.rs +570 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/aarch64/settings.rs +9 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/mod.rs +471 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley32.rs +13 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley64.rs +13 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/abi.rs +798 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/inst/args.rs +192 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/inst/emit.rs +482 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/inst/mod.rs +905 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/inst/regs.rs +164 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/inst.isle +543 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/lower/isle/generated_code.rs +17 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/lower/isle.rs +195 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/lower.isle +178 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/lower.rs +36 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/mod.rs +281 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/pulley_shared/settings.rs +16 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/abi.rs +993 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/args.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/emit.rs +2685 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/emit_tests.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/encode.rs +721 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/mod.rs +1865 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst/vector.rs +1150 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst.isle +3128 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/inst_vector.isle +1907 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/lower/isle.rs +721 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/riscv64/lower.isle +2940 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/abi.rs +1348 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst/emit.rs +3470 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst/emit_tests.rs +13370 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst/mod.rs +3461 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst/regs.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst/unwind/systemv.rs +212 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/inst.isle +5071 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/lower/isle.rs +1109 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/s390x/lower.isle +3981 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/unwind/systemv.rs +276 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/abi.rs +1390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/encoding/evex.rs +747 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/args.rs +2318 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/emit.rs +4400 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/emit_state.rs +55 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/emit_tests.rs +5146 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/mod.rs +2811 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/regs.rs +275 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/stack_switch.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst/unwind/systemv.rs +198 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/inst.isle +5382 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/lower/isle.rs +1047 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/lower.isle +4919 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/lower.rs +338 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/mod.rs +239 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isa/x64/pcc.rs +1022 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/isle_prelude.rs +1144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/abi.rs +2417 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/buffer.rs +2492 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/isle.rs +890 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/lower.rs +1590 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/mod.rs +560 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/reg.rs +484 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/machinst/vcode.rs +1762 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/opts/extends.isle +95 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/opts/icmp.isle +258 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/opts/selects.isle +88 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/prelude.isle +751 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/prelude_lower.isle +1081 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/print_errors.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/remove_constant_phis.rs +419 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/result.rs +111 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/settings.rs +591 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/timing.rs +296 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/verifier/mod.rs +1941 -0
- data/ext/cargo-vendor/cranelift-codegen-0.112.1/src/write.rs +694 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/Cargo.toml +54 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/cdsl/settings.rs +429 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/cdsl/types.rs +420 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/cdsl/typevar.rs +946 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/error.rs +48 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/gen_inst.rs +1274 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/gen_isle.rs +519 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/gen_settings.rs +505 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/gen_types.rs +70 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isa/arm64.rs +59 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isa/mod.rs +81 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isa/pulley.rs +14 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isa/riscv64.rs +181 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isa/x86.rs +414 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/isle.rs +142 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/lib.rs +98 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/shared/instructions.rs +3801 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/shared/mod.rs +87 -0
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- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/shared/types.rs +103 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.112.1/src/srcgen.rs +464 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.112.1/Cargo.toml +32 -0
- data/ext/cargo-vendor/cranelift-control-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.112.1/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.1/Cargo.toml +75 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.1/src/lib.rs +381 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.1/src/packed_option.rs +173 -0
- data/ext/cargo-vendor/cranelift-entity-0.112.1/src/sparse.rs +367 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.1/Cargo.toml +97 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.1/src/frontend.rs +1963 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.1/src/ssa.rs +1325 -0
- data/ext/cargo-vendor/cranelift-frontend-0.112.1/src/switch.rs +676 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/Cargo.toml +69 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/build.rs +35 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/ast.rs +412 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/codegen.rs +922 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/compile.rs +65 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/error.rs +318 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/files.rs +133 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/lexer.rs +343 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/lib.rs +34 -0
- data/ext/cargo-vendor/cranelift-isle-0.112.1/src/overlap.rs +130 -0
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# regalloc2 Design Overview
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This document describes the basic architecture of the regalloc2
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register allocator. It describes the externally-visible interface
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(input CFG, instructions, operands, with their invariants; meaning of
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various parts of the output); core data structures; and the allocation
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pipeline, or series of algorithms that compute an allocation. It ends
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with a description of future work and expectations, as well as an
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appendix that notes design influences and similarities to the
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IonMonkey backtracking allocator.
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# API, Input IR and Invariants
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The toplevel API to regalloc2 consists of a single entry point `run()`
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that takes a register environment, which specifies all physical
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registers, and the input program. The function returns either an error
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or an `Output` struct that provides allocations for each operand and a
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vector of additional instructions (moves, loads, stores) to insert.
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## Register Environment
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The allocator takes a `MachineEnv` which specifies, for each of the
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two register classes `Int` and `Float`, a vector of `PReg`s by index. A
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`PReg` is nothing more than the class and index within the class; the
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allocator does not need to know anything more.
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The `MachineEnv` provides a vector of preferred and non-preferred
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physical registers per class. Any register not in either vector will
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not be allocated. Usually, registers that do not need to be saved in
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the prologue if used (i.e., caller-save registers) are given in the
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"preferred" vector. The environment also provides exactly one scratch
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register per class. This register must not be in the preferred or
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non-preferred vectors, and is used whenever a set of moves that need
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to occur logically in parallel have a cycle (for a simple example,
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consider a swap `r0, r1 := r1, r0`).
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With some more work, we could potentially remove the need for the
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scratch register by requiring support for an additional edit type from
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the client ("swap"), but we have not pursued this.
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## CFG and Instructions
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The allocator operates on an input program that is in a standard CFG
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representation: the function body is a sequence of basic blocks, and
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each block has a sequence of instructions and zero or more
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successors. The allocator also requires the client to provide
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predecessors for each block, and these must be consistent with the
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successors.
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Instructions are opaque to the allocator except for a few important
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bits: (1) `is_ret` (is a return instruction); (2) `is_branch` (is a
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branch instruction); and (3) a vector of Operands, covered below.
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Every block must end in a return or branch.
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Both instructions and blocks are named by indices in contiguous index
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spaces. A block's instructions must be a contiguous range of
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instruction indices, and block i's first instruction must come
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immediately after block i-1's last instruction.
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The CFG must have *no critical edges*. A critical edge is an edge from
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block A to block B such that A has more than one successor *and* B has
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more than one predecessor. For this definition, the entry block has an
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implicit predecessor, and any block that ends in a return has an
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implicit successor.
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Note that there are *no* requirements related to the ordering of
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blocks, and there is no requirement that the control flow be
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reducible. Some *heuristics* used by the allocator will perform better
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if the code is reducible and ordered in reverse postorder (RPO),
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however: in particular, (1) this interacts better with the
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contiguous-range-of-instruction-indices live range representation that
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we use, and (2) the "approximate loop depth" metric will actually be
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exact if both these conditions are met.
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## Operands and VRegs
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Every instruction operates on values by way of `Operand`s. An operand
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consists of the following fields:
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- VReg, or virtual register. *Every* operand mentions a virtual
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register, even if it is constrained to a single physical register in
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practice. This is because we track liveranges uniformly by vreg.
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- Policy, or "constraint". Every reference to a vreg can apply some
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constraint to the vreg at that point in the program. Valid policies are:
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- Any location;
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- Any register of the vreg's class;
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- Any stack slot;
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- A particular fixed physical register; or
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- For a def (output), a *reuse* of an input register.
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- The "kind" of reference to this vreg: Def, Use, Mod. A def
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(definition) writes to the vreg, and disregards any possible earlier
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value. A mod (modify) reads the current value then writes a new
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one. A use simply reads the vreg's value.
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- The position: before or after the instruction.
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- Note that to have a def (output) register available in a way that
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does not conflict with inputs, the def should be placed at the
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"before" position. Similarly, to have a use (input) register
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available in a way that does not conflict with outputs, the use
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should be placed at the "after" position.
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VRegs, or virtual registers, are specified by an index and a register
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class (Float or Int). The classes are not given separately; they are
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encoded on every mention of the vreg. (In a sense, the class is an
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extra index bit, or part of the register name.) The input function
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trait does require the client to provide the exact vreg count,
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however.
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Implementation note: both vregs and operands are bit-packed into
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u32s. This is essential for memory-efficiency. As a result of the
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operand bit-packing in particular (including the policy constraints!),
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the allocator supports up to 2^21 (2M) vregs per function, and 2^6
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(64) physical registers per class. Later we will also see a limit of
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2^20 (1M) instructions per function. These limits are considered
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sufficient for the anticipated use-cases (e.g., compiling Wasm, which
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also has function-size implementation limits); for larger functions,
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it is likely better to use a simpler register allocator in any case.
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## Reuses and Two-Address ISAs
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Some instruction sets primarily have instructions that name only two
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registers for a binary operator, rather than three: both registers are
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inputs, and the result is placed in one of the registers, clobbering
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its original value. The most well-known modern example is x86. It is
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thus imperative that we support this pattern well in the register
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allocator.
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This instruction-set design is somewhat at odds with an SSA
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representation, where a value cannot be redefined.
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Thus, the allocator supports a useful fiction of sorts: the
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instruction can be described as if it has three register mentions --
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two inputs and a separate output -- and neither input will be
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clobbered. The output, however, is special: its register-placement
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policy is "reuse input i" (where i == 0 or 1). The allocator
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guarantees that the register assignment for that input and the output
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will be the same, so the instruction can use that register as its
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"modifies" operand. If the input is needed again later, the allocator
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will take care of the necessary copying.
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We will see below how the allocator makes this work by doing some
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preprocessing so that the core allocation algorithms do not need to
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worry about this constraint.
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## SSA
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regalloc2 takes an SSA IR as input, where the usual definitions apply:
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every vreg is defined exactly once, and every vreg use is dominated by
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its one def. (Using blockparams means that we do not need additional
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conditions for phi-nodes.)
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## Block Parameters
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Every block can have *block parameters*, and a branch to a block with
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block parameters must provide values for those parameters via
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operands. When a branch has more than one successor, it provides
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separate operands for each possible successor. These block parameters
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are equivalent to phi-nodes; we chose this representation because they
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are in many ways a more consistent representation of SSA.
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To see why we believe block parameters are a slightly nicer design
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choice than use of phi nodes, consider: phis are special
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pseudoinstructions that must come first in a block, are all defined in
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parallel, and whose uses occur on the edge of a particular
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predecessor. All of these facts complicate any analysis that scans
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instructions and reasons about uses and defs. It is much closer to the
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truth to actually put those uses *in* the predecessor, on the branch,
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and put all the defs at the top of the block as a separate kind of
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def. The tradeoff is that a vreg's def now has two possibilities --
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ordinary instruction def or blockparam def -- but this is fairly
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reasonable to handle.
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## Output
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The allocator produces two main data structures as output: an array of
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`Allocation`s and a sequence of edits. Some other data, such as
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stackmap slot info, is also provided.
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### Allocations
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The allocator provides an array of `Allocation` values, one per
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`Operand`. Each `Allocation` has a kind and an index. The kind may
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indicate that this is a physical register or a stack slot, and the
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index gives the respective register or slot. All allocations will
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conform to the constraints given, and will faithfully preserve the
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dataflow of the input program.
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### Inserted Moves
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In order to implement the necessary movement of data between
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allocations, the allocator needs to insert moves at various program
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points.
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The vector of inserted moves contains tuples that name a program point
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and an "edit". The edit is either a move, from one `Allocation` to
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another, or else a kind of metadata used by the checker to know which
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VReg is live in a given allocation at any particular time. The latter
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sort of edit can be ignored by a backend that is just interested in
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generating machine code.
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|
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+
Note that the allocator will never generate a move from one stackslot
|
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+
directly to another, by design. Instead, if it needs to do so, it will
|
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|
+
make use of the scratch register. (Sometimes such a move occurs when
|
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|
+
the scratch register is already holding a value, e.g. to resolve a
|
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+
cycle of moves; in this case, it will allocate another spillslot and
|
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+
spill the original scratch value around the move.)
|
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|
+
|
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|
+
Thus, the single "edit" type can become either a register-to-register
|
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|
+
move, a load from a stackslot into a register, or a store from a
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+
register into a stackslot.
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+
|
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+
# Data Structures
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+
|
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+
We now review the data structures that regalloc2 uses to track its
|
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+
state.
|
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+
|
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|
+
## Program-Derived Alloc-Invariant Data
|
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+
|
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|
+
There are a number of data structures that are computed in a
|
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|
+
deterministic way from the input program and then subsequently used
|
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+
only as read-only data during the core allocation procedure.
|
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|
+
|
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|
+
### Livein/Liveout Bitsets
|
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|
+
|
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|
+
The livein and liveout bitsets (`liveins` and `liveouts` on the `Env`)
|
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|
+
are allocated one per basic block and record, per block, which vregs
|
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|
+
are live entering and leaving that block. They are computed using a
|
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+
standard backward iterative dataflow analysis and are exact; they do
|
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+
not over-approximate (this turns out to be important for performance,
|
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+
and is also necessary for correctness in the case of stackmaps).
|
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|
+
|
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|
+
### Blockparam Vectors: Source-Side and Dest-Side
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|
+
|
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|
+
The initialization stage scans the input program and produces two
|
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|
+
vectors that represent blockparam flows from branches to destination
|
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|
+
blocks: `blockparam_ins` and `blockparam_outs`.
|
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|
+
|
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|
+
These two vectors are the first instance we will see of a recurring
|
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|
+
pattern: the vectors contain tuples that are carefully ordered in a
|
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|
+
way such that their sort-order is meaningful. "Build a vector lazily
|
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|
+
then sort" is a common idiom: it batches the O(n log n) cost into one
|
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|
+
operation that the stdlib has aggressively optimized, it provides
|
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|
+
dense storage, and it allows for a scan in a certain order that often
|
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|
+
lines up with a scan over the program.
|
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|
+
|
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|
+
In this particular case, we will build vectors of (vreg, block) points
|
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|
+
that are meaningful either at the start or end of a block, so that
|
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|
+
later, when we scan over a particular vreg's allocations in block
|
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|
+
order, we can generate another vector of allocations. One side (the
|
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|
+
"outs") also contains enough information that it can line up with the
|
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|
+
other side (the "ins") in a later sort.
|
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|
+
|
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|
+
To make this work, `blockparam_ins` contains a vector of (to-vreg,
|
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|
+
to-block, from-block) tuples, and has an entry for every blockparam of
|
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|
+
every block. Note that we can compute this without actually observing
|
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|
+
from-blocks; we only need to iterate over `block_preds` at any given
|
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|
+
block.
|
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|
+
|
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|
+
Then, `blockparam_outs` contains a vector of (from-vreg, from-block,
|
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|
+
to-block, to-vreg), and has an entry for every parameter on every
|
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|
+
branch that ends a block. There is exactly one "out" tuple for every
|
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|
+
"in" tuple. As mentioned above, we will later scan over both to
|
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+
generate moves.
|
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|
+
|
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|
+
## Core Allocation State: Ranges, Uses, Bundles, VRegs, PRegs
|
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|
+
|
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|
+
We now come to the core data structures: live-ranges, bundles, virtual
|
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|
+
registers and their state, and physical registers and their state.
|
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|
+
|
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|
+
First we must define a `ProgPoint` precisely: a `ProgPoint` is an
|
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|
+
instruction index and a `Before` or `After` suffix. We pack the
|
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|
+
before/after suffix into the LSB of a `u32`, so a `ProgPoint` can be
|
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|
+
incremented and compared as a simple integer.
|
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|
+
|
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|
+
A live-range is a contiguous range of program points (half-open,
|
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|
+
i.e. including `from` and excluding `to`) for which a particular vreg
|
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|
+
is live with a value.
|
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|
+
|
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|
+
A live-range contains a vector of uses. Each use contains four parts:
|
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|
+
the Operand word (directly copied, so there is no need to dereference
|
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|
+
it); the ProgPoint at which the use occurs; the operand slot on that
|
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|
+
instruction, if any, that the operand comes from, and the use's
|
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|
+
'weight". (It's possible to have "ghost uses" that do not derive from
|
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|
+
any slot on the instruction.) These four parts are packed into three
|
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|
+
`u32`s: the slot can fit in 8 bits, and the weight in 16.
|
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|
+
|
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|
+
The live-range carries its program-point range, uses, vreg index,
|
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|
+
bundle index (see below), and some metadata: spill weight and
|
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|
+
flags. The spill weight is the sum of weights of each use. The flags
|
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|
+
set currently carries one flag only: whether the live-range starts at
|
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|
+
a Def-kind operand. (This is equivalent to whether the range consumes
|
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|
+
a value at its start or not.)
|
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|
+
|
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|
+
Uses are owned only by live-ranges and have no separate identity, but
|
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|
+
live-ranges live in a toplevel array and are known by `LiveRangeIndex`
|
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|
+
values throughout the allocator. New live-ranges can be created
|
300
|
+
(e.g. during splitting); old ones are not cleaned up, but rather, all
|
301
|
+
state is bulk-freed at the end.
|
302
|
+
|
303
|
+
Live-ranges are aggregated into "bundles". A bundle is a collection of
|
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|
+
ranges that does not overlap. Each bundle carries: a vector (inline
|
305
|
+
SmallVec) of (range, live-range index) tuples, an allocation (starts
|
306
|
+
as "none"), a "spillset" (more below), and some metadata, including a
|
307
|
+
spill weight (sum of ranges' weights), a priority (sum of ranges'
|
308
|
+
lengths), and three property flags: "minimal", "contains fixed
|
309
|
+
constraints", "contains stack constraints".
|
310
|
+
|
311
|
+
VRegs also contain their vectors of live-ranges, in the same form as a
|
312
|
+
bundle does (inline SmallVec that has inline (from, to) range bounds
|
313
|
+
and range indices).
|
314
|
+
|
315
|
+
There are two important overlap invariants: (i) no liveranges within a
|
316
|
+
bundle overlap, and (ii) no liveranges within a vreg overlap. These
|
317
|
+
are extremely important and we rely on them implicitly in many places.
|
318
|
+
|
319
|
+
The live-range vectors in bundles and vregs, and use-vectors in ranges,
|
320
|
+
have various sorting invariants as well. These invariants differ
|
321
|
+
according to the phase of the allocator's computation. First, during
|
322
|
+
live-range construction, live-ranges are placed into vregs in reverse
|
323
|
+
order (because the computation is a reverse scan) and uses into ranges
|
324
|
+
in reverse order; these are sorted into forward order at the end of
|
325
|
+
live-range computation. When bundles are first constructed, their
|
326
|
+
range vectors are sorted, and they remain so for the rest of allocation,
|
327
|
+
as we need for interference testing. However, as ranges are created
|
328
|
+
and split, sortedness of vreg ranges is *not* maintained; they are
|
329
|
+
sorted once more, in bulk, when allocation is done and we start to
|
330
|
+
resolve moves.
|
331
|
+
|
332
|
+
Finally, we have physical registers. The main data associated with
|
333
|
+
each is the allocation map. This map is a standard BTree, indexed by
|
334
|
+
ranges (`from` and `to` ProgPoints) and yielding a LiveRange for each
|
335
|
+
location range. The ranges have a custom comparison operator defined
|
336
|
+
that compares equal for any overlap.
|
337
|
+
|
338
|
+
This comparison operator allows us to determine whether a range is
|
339
|
+
free, i.e. has no overlap with a particular range, in one probe -- the
|
340
|
+
btree will not contain a match. However, it makes iteration over *all*
|
341
|
+
overlapping ranges somewhat tricky to get right. Notably, Rust's
|
342
|
+
BTreeMap does not guarantee that the lookup result will be the *first*
|
343
|
+
equal key, if multiple keys are equal to the probe key. Thus, when we
|
344
|
+
want to enumerate all overlapping ranges, we probe with a range that
|
345
|
+
consists of the single program point *before* the start of the actual
|
346
|
+
query range, using the API that returns an iterator over a range in
|
347
|
+
the BTree, and then iterate through the resulting iterator to gather
|
348
|
+
all overlapping ranges (which will be contiguous).
|
349
|
+
|
350
|
+
## Spill Bundles
|
351
|
+
|
352
|
+
It is worth describing "spill bundles" separately. Every spillset (see
|
353
|
+
below; a group of bundles that originated from one bundle) optionally
|
354
|
+
points to a single bundle that we designate the "spill bundle" for
|
355
|
+
that spillset. Contrary to the name, this bundle is not
|
356
|
+
unconditionally spilled. Rather, one can see it as a sort of fallback:
|
357
|
+
it is where liveranges go when we give up on processing them via the
|
358
|
+
normal backtracking loop, and will only process them once more in the
|
359
|
+
"second-chance" stage.
|
360
|
+
|
361
|
+
This fallback behavior implies that the spill bundle must always be
|
362
|
+
able to accept a spillslot allocation, i.e., it cannot require a
|
363
|
+
register. This invariant is what allows spill bundles to be processed
|
364
|
+
in a different way, after backtracking has completed.
|
365
|
+
|
366
|
+
The spill bundle acquires liveranges in two ways. First, as we split
|
367
|
+
bundles, we will trim the split pieces in certain ways so that some
|
368
|
+
liveranges are immediately placed in the spill bundle. Intuitively,
|
369
|
+
the "empty" regions that just carry a value, but do not satisfy any
|
370
|
+
operands, should be in the spill bundle: it is better to have a single
|
371
|
+
consistent location for the value than to move it between lots of
|
372
|
+
different split pieces without using it, as moves carry a cost.
|
373
|
+
|
374
|
+
Second, the spill bundle acquires the liveranges of a bundle that has
|
375
|
+
no requirement to be in a register when that bundle is processed, but
|
376
|
+
only if the spill bundle already exists. In other words, we won't
|
377
|
+
create a second-chance spill bundle just for a liverange with an "Any"
|
378
|
+
use; but if it was already forced into existence by splitting and
|
379
|
+
trimming, then we might as well use it.
|
380
|
+
|
381
|
+
Note that unlike other bundles, a spill bundle's liverange vector
|
382
|
+
remains unsorted until we do the second-chance allocation. This allows
|
383
|
+
quick appends of more liveranges.
|
384
|
+
|
385
|
+
## Allocation Queue
|
386
|
+
|
387
|
+
The allocation queue is simply a priority queue (built with a binary
|
388
|
+
max-heap) of (prio, bundle-index) tuples.
|
389
|
+
|
390
|
+
## Spillsets and Spillslots
|
391
|
+
|
392
|
+
Every bundle contains a reference to a spillset. Spillsets are used to
|
393
|
+
assign spillslots near the end of allocation, but before then, they
|
394
|
+
are also a convenient place to store information that is common among
|
395
|
+
*all bundles* that share the spillset. In particular, spillsets are
|
396
|
+
initially assigned 1-to-1 to bundles after all bundle-merging is
|
397
|
+
complete; so spillsets represent in some sense the "original bundles",
|
398
|
+
and as splitting commences, the smaller bundle-pieces continue to
|
399
|
+
refer to their original spillsets.
|
400
|
+
|
401
|
+
We stash some useful information on the spillset because of this: a
|
402
|
+
register hint, used to create some "stickiness" between pieces of an
|
403
|
+
original bundle that are assigned separately after splitting; the
|
404
|
+
spill bundle; the common register class of all vregs in this bundle;
|
405
|
+
the vregs whose liveranges are contained in this bundle; and then some
|
406
|
+
information actually used if this is spilled to the stack (`required`
|
407
|
+
indicates actual stack use; `size` is the spillslot count; `slot` is
|
408
|
+
the actual stack slot).
|
409
|
+
|
410
|
+
Spill *sets* are later allocated to spill *slots*. Multiple spillsets
|
411
|
+
can be assigned to one spillslot; the only constraint is that
|
412
|
+
spillsets assigned to a spillslot must not overlap. When we look up
|
413
|
+
the allocation for a bundle, if the bundle is not given a specific
|
414
|
+
allocation (its `alloc` field is `Allocation::none()`), this means it
|
415
|
+
is spilled, and we traverse to the spillset then spillslot.
|
416
|
+
|
417
|
+
## Other: Fixups, Stats, Debug Annotations
|
418
|
+
|
419
|
+
There are a few fixup vectors that we will cover in more detail
|
420
|
+
later. Of particular note is the "multi-fixed-reg fixup vector": this
|
421
|
+
handles instructions that constrain the same input vreg to multiple,
|
422
|
+
different, fixed registers for different operands at the same program
|
423
|
+
point. The only way to satisfy such a set of constraints is to
|
424
|
+
decouple all but one of the inputs (make them no longer refer to the
|
425
|
+
vreg) and then later insert copies from the first fixed use of the
|
426
|
+
vreg to the other fixed regs.
|
427
|
+
|
428
|
+
The `Env` also carries a statistics structure with counters that are
|
429
|
+
incremented, which can be useful for evaluating the effects of
|
430
|
+
changes; and a "debug annotations" hashmap from program point to
|
431
|
+
arbitrary strings that is filled out with various useful diagnostic
|
432
|
+
information if enabled, so that an annotated view of the program with
|
433
|
+
its liveranges, bundle assignments, inserted moves, merge and split
|
434
|
+
decisions, etc. can be viewed.
|
435
|
+
|
436
|
+
# Allocation Pipeline
|
437
|
+
|
438
|
+
We now describe the pipeline that computes register allocations.
|
439
|
+
|
440
|
+
## Live-range Construction
|
441
|
+
|
442
|
+
The first step in performing allocation is to analyze the input
|
443
|
+
program to understand its dataflow: that is, the ranges during which
|
444
|
+
virtual registers must be assigned to physical registers. Computing
|
445
|
+
these ranges is what allows us to do better than a trivial "every vreg
|
446
|
+
lives in a different location, always" allocation.
|
447
|
+
|
448
|
+
We compute precise liveness first using an iterative dataflow
|
449
|
+
algorithm with BitVecs. (See below for our sparse chunked BitVec
|
450
|
+
description.) This produces the `liveins` and `liveouts` vectors of
|
451
|
+
BitVecs per block.
|
452
|
+
|
453
|
+
We then perform a single pass over blocks in reverse order, and scan
|
454
|
+
instructions in each block in reverse order. Why reverse order? We
|
455
|
+
must see instructions within a block in reverse to properly compute
|
456
|
+
liveness (a value is live backward from an use to a def). Because we
|
457
|
+
want to keep liveranges in-order as we build them, to enable
|
458
|
+
coalescing, we visit blocks in reverse order as well, so overall this
|
459
|
+
is simply a scan over the whole instruction index space in reverse
|
460
|
+
order.
|
461
|
+
|
462
|
+
For each block, we perform a scan with the following state:
|
463
|
+
|
464
|
+
- A liveness bitvec, initialized at the start from `liveouts`.
|
465
|
+
- A vector of live-range indices, with one entry per vreg, initially
|
466
|
+
"invalid" (this vector is allocated once and reused at each block).
|
467
|
+
- In-progress vector of live-range indices per vreg in the vreg state,
|
468
|
+
in *reverse* order (we will reverse it when we're done).
|
469
|
+
|
470
|
+
A vreg is live at the current point in the scan if its bit is set in
|
471
|
+
the bitvec; its entry in the vreg-to-liverange vec may be stale, but
|
472
|
+
if the bit is not set, we ignore it.
|
473
|
+
|
474
|
+
We initially create a liverange for all vregs that are live out of the
|
475
|
+
block, spanning the whole block. We will trim this below if it is
|
476
|
+
locally def'd and does not pass through the block.
|
477
|
+
|
478
|
+
For each instruction, we process its effects on the scan state:
|
479
|
+
|
480
|
+
- For all clobbers (which logically happen at the end of the
|
481
|
+
instruction), add a single-program-point liverange to each clobbered
|
482
|
+
preg.
|
483
|
+
|
484
|
+
- For each program point [after, before], for each operand at
|
485
|
+
this point(\*):
|
486
|
+
- if a def:
|
487
|
+
- if not currently live, this is a dead def; create an empty LR.
|
488
|
+
- set the start of the LR for this vreg to this point.
|
489
|
+
- set as dead.
|
490
|
+
- if a use:
|
491
|
+
- create LR if not live, with start at beginning of block.
|
492
|
+
|
493
|
+
|
494
|
+
(\*) an instruction operand's effective point is adjusted in a few
|
495
|
+
cases. If the instruction is a branch, its uses (which are
|
496
|
+
blockparams) are extended to the "after" point. If there is a reused
|
497
|
+
input, all *other* inputs are extended to "after": this ensures proper
|
498
|
+
interference (as we explain more below).
|
499
|
+
|
500
|
+
We then treat blockparams as defs at the end of the scan (beginning of
|
501
|
+
the block), and create the "ins" tuples. (The uses for the other side
|
502
|
+
of the edge are already handled as normal uses on a branch
|
503
|
+
instruction.)
|
504
|
+
|
505
|
+
### Handling Reused Inputs
|
506
|
+
|
507
|
+
Reused inputs are also handled a bit specially. We have already
|
508
|
+
described how we essentially translate the idiom so that the output's
|
509
|
+
allocation is used for input and output, and there is a move just
|
510
|
+
before the instruction that copies the actual input (which will not be
|
511
|
+
clobbered) to the output. Together with an attempt to merge the
|
512
|
+
bundles for the two, to elide the move if possible, this works
|
513
|
+
perfectly well as long as we ignore all of the other inputs.
|
514
|
+
|
515
|
+
But we can't do that: we have to ensure that other inputs' allocations
|
516
|
+
are correct too. Note that using the output's allocation as the input
|
517
|
+
is actually potentially incorrect if the output is at the After point
|
518
|
+
and the input is at the Before: the output might share a register with
|
519
|
+
one of the *other* (normal, non-reused) inputs if that input's vreg
|
520
|
+
were dead afterward. This will mean that we clobber the other input.
|
521
|
+
|
522
|
+
So, to get the interference right, we *extend* all other (non-reused)
|
523
|
+
inputs of an instruction with a reused input to the After point. This
|
524
|
+
ensures that the other inputs are *not* clobbered by the slightly
|
525
|
+
premature use of the output register.
|
526
|
+
|
527
|
+
The source has a link to a comment in IonMonkey that implies that it
|
528
|
+
uses a similar solution to this problem, though it's not entirely
|
529
|
+
clear.
|
530
|
+
|
531
|
+
(This odd dance, like many of the others above and below, is "written
|
532
|
+
in fuzzbug failures", so to speak. It's not entirely obvious until one
|
533
|
+
sees the corner case where it's necessary!)
|
534
|
+
|
535
|
+
## Bundle Merging
|
536
|
+
|
537
|
+
Once we have built the liverange vectors for every vreg, we can reverse
|
538
|
+
these vectors (recall, they were built in strict reverse order) and
|
539
|
+
initially assign one bundle per (non-pinned) vreg. We then try to
|
540
|
+
merge bundles together as long as find pairs of bundles that do not
|
541
|
+
overlap and that (heuristically) make sense to merge.
|
542
|
+
|
543
|
+
Note that this is the only point in the allocation pipeline where
|
544
|
+
bundles get larger. We initially merge as large as we dare (but not
|
545
|
+
too large, because then we'll just cause lots of conflicts and
|
546
|
+
splitting later), and then try out assignments, backtrack via
|
547
|
+
eviction, and split continuously to chip away at the problem until we
|
548
|
+
have a working set of allocation assignments.
|
549
|
+
|
550
|
+
We attempt to merge two kinds of bundle pairs: reused-input to
|
551
|
+
corresponding output; and across blockparam assignments.
|
552
|
+
|
553
|
+
To merge two bundles, we traverse over both their sorted liverange
|
554
|
+
vectors at once, checking for overlaps. Note that we can do this without
|
555
|
+
pointer-chasing to the liverange data; the (from, to) range is in the
|
556
|
+
liverange vector itself.
|
557
|
+
|
558
|
+
We also check whether the merged bundle would have conflicting
|
559
|
+
requirements (see below for more on requirements). We do a coarse
|
560
|
+
check first, checking 1-bit flags that indicate whether either bundle
|
561
|
+
has any fixed-reg constraints or stack-only constraints. If so, we
|
562
|
+
need to do a detailed check by actually computing merged requirements
|
563
|
+
on both sides, merging, and checking for Conflict (the lattice bottom
|
564
|
+
value). If no conflict, we merge.
|
565
|
+
|
566
|
+
A performance note: merging is extremely performance-sensitive, and it
|
567
|
+
turns out that a mergesort-like merge of the liverange vectors is too
|
568
|
+
expensive, partly because it requires allocating a separate result
|
569
|
+
vector (in-place merge in mergesort is infamously complex). Instead,
|
570
|
+
we simply append one vector onto the end of the other and invoke
|
571
|
+
Rust's builtin sort. We could special-case "one bundle is completely
|
572
|
+
before the other", but we currently don't do that (performance idea!).
|
573
|
+
|
574
|
+
Once all bundles are merged as far as they will go, we compute cached
|
575
|
+
bundle properties (priorities and weights) and enqueue them on the
|
576
|
+
priority queue for allocation.
|
577
|
+
|
578
|
+
## Recurring: Bundle Property Computation
|
579
|
+
|
580
|
+
The core allocation loop is a recurring iteration of the following: we
|
581
|
+
take the highest-priority bundle from the allocation queue; we compute
|
582
|
+
its requirements; we try to find it a register according to those
|
583
|
+
requirements; if no fit, we either evict some other bundle(s) from
|
584
|
+
their allocations and try again, or we split the bundle and put the
|
585
|
+
parts back on the queue. We record all the information we need to make
|
586
|
+
the evict-or-split decision (and where to split) *during* the physical
|
587
|
+
register allocation-map scans, so we don't need to go back again to
|
588
|
+
compute that.
|
589
|
+
|
590
|
+
Termination is nontrivial to see, because of eviction. How do we
|
591
|
+
guarantee we don't get into an infinite loop where two bundles fight
|
592
|
+
over a register forever? In fact, this can easily happen if there is a
|
593
|
+
bug; we fixed many fuzzbugs like this, and we have a check for
|
594
|
+
"infinite loop" based on an upper bound on iterations. But if the
|
595
|
+
allocator is correct, it should never happen.
|
596
|
+
|
597
|
+
Termination is guaranteed because (i) bundles always get smaller, (ii)
|
598
|
+
eviction only occurs when a bundle is *strictly* higher weight (not
|
599
|
+
higher-or-equal), and (iii) once a bundle gets down to its "minimal"
|
600
|
+
size, it has an extremely high weight that is guaranteed to evict any
|
601
|
+
non-minimal bundle. A minimal bundle is one that covers only one
|
602
|
+
instruction. As long as the input program does not have impossible
|
603
|
+
constraints that require more than one vreg to exist in one preg, an
|
604
|
+
allocation problem of all minimal bundles will always have a solution.
|
605
|
+
|
606
|
+
## Bundle Processing
|
607
|
+
|
608
|
+
Let's now talk about what happens when we take a bundle off the
|
609
|
+
allocation queue. The three basic outcomes are: allocate; split and
|
610
|
+
requeue; or evict and try again immediately (and eventually allocate
|
611
|
+
or split/requeue).
|
612
|
+
|
613
|
+
### Properties: Weight, Priority, and Requirements
|
614
|
+
|
615
|
+
To process a bundle, we have to compute a few properties. In fact we
|
616
|
+
will have already computed a few of these beforehand, but we describe
|
617
|
+
them all here.
|
618
|
+
|
619
|
+
- Priority: a bundle's priority determines the order in which it is
|
620
|
+
considered for allocation. RA2 defines as the sum of the lengths (in
|
621
|
+
instruction index space) of each liverange. This causes the
|
622
|
+
allocator to consider larger bundles first, when the allocation maps
|
623
|
+
are generally more free; they can always be evicted and split later.
|
624
|
+
|
625
|
+
- Weight: a bundle's weight indicates how important (in terms of
|
626
|
+
runtime) its uses/register mentions are. In an approximate sense,
|
627
|
+
inner loop bodies create higher-weight uses. Fixed register
|
628
|
+
constraints add some weight, and defs add some weight. Finally,
|
629
|
+
weight is divided by priority, so a very large bundle that happens
|
630
|
+
to have a few important uses does not unformly exert its weight
|
631
|
+
across its entire range. This has the effect of causing bundles to
|
632
|
+
be more important (more likely to evict others) the more they are
|
633
|
+
split.
|
634
|
+
|
635
|
+
- Requirement: a bundle's requirement is a value in a lattice that we
|
636
|
+
have defined, where top is "Unknown" and bottom is
|
637
|
+
"Conflict". Between these two, we have: any register (of a class);
|
638
|
+
any stackslot (of a class); a particular register. "Any register"
|
639
|
+
can degrade to "a particular register", but any other pair of
|
640
|
+
different requirements meets to Conflict. Requirements are derived
|
641
|
+
from the operand constraints for all uses in all liveranges in a
|
642
|
+
bundle, and then merged with the lattice meet-function.
|
643
|
+
|
644
|
+
The lattice is as follows (diagram simplified to remove multiple
|
645
|
+
classes and multiple fixed registers which parameterize nodes; any two
|
646
|
+
differently-parameterized values are unordered with respect to each
|
647
|
+
other):
|
648
|
+
|
649
|
+
```plain
|
650
|
+
|
651
|
+
Any(rc)
|
652
|
+
/ \
|
653
|
+
FixedReg(reg) FixedStack(reg)
|
654
|
+
\ /
|
655
|
+
Conflict
|
656
|
+
```
|
657
|
+
|
658
|
+
Once we have the Requirement for a bundle, we can decide what to do.
|
659
|
+
|
660
|
+
### No-Register-Required Cases
|
661
|
+
|
662
|
+
If the requirement indicates that no register is needed (`Unknown` or
|
663
|
+
`Any`, i.e. a register or stack slot would be OK), *and* if the spill
|
664
|
+
bundle already exists for this bundle's spillset, then we move all the
|
665
|
+
liveranges over to the spill bundle, as described above.
|
666
|
+
|
667
|
+
If the requirement indicates a conflict, we immediately split and
|
668
|
+
requeue the split pieces. This split is performed at the point at
|
669
|
+
which the conflict is first introduced, i.e. just before the first use
|
670
|
+
whose requirement, when merged into the requirement for all prior uses
|
671
|
+
combined, goes to `Conflict`. In this way, we always guarantee forward
|
672
|
+
progress. Note also that a bundle can reach this stage with a
|
673
|
+
conflicting requirement only if the original liverange had conflicting
|
674
|
+
uses (e.g., a liverange from a def in a register to a use on stack, or
|
675
|
+
a liverange between two different fixed-reg-constrained operands); our
|
676
|
+
bundle merging logic explicitly avoids merging two bundles if it would
|
677
|
+
create a conflict.
|
678
|
+
|
679
|
+
### Allocation-Map Probing
|
680
|
+
|
681
|
+
If we did not immediately dispose of the bundle as described above,
|
682
|
+
then we *can* use a register (either `Any`, which accepts a register
|
683
|
+
as one of several options, or `Reg`, which must have one, or `Fixed`,
|
684
|
+
which must have a particular one).
|
685
|
+
|
686
|
+
We determine which physical registers whose allocation maps we will
|
687
|
+
probe, and in what order. If a particular fixed register is required,
|
688
|
+
we probe only that register. Otherwise, we probe all registers in the
|
689
|
+
required class.
|
690
|
+
|
691
|
+
The order in which we probe, if we are not constrained to a single
|
692
|
+
register, is carefully chosen. First, if there is a hint register from
|
693
|
+
the spillset (this is set by the last allocation into a register of
|
694
|
+
any other bundle in this spillset), we probe that. Then, we probe all
|
695
|
+
preferred registers; then all non-preferred registers.
|
696
|
+
|
697
|
+
For each of the preferred and non-preferred register sequences, we
|
698
|
+
probe in an *offset* manner: we start at some index partway through
|
699
|
+
the sequence, determined by some heuristic number that is random and
|
700
|
+
well-distributed. (In practice, we use the sum of the bundle index and
|
701
|
+
the instruction index of the start of the first range in the bundle.)
|
702
|
+
We then march through the sequence and wrap around, stopping before we
|
703
|
+
hit our starting point again.
|
704
|
+
|
705
|
+
The purpose of this offset is to distribute the contention and speed
|
706
|
+
up the allocation process. In the common case where there are enough
|
707
|
+
registers to hold values without spilling (for small functions), we
|
708
|
+
are more likely to choose a free register right away if we throw the
|
709
|
+
dart at random than if we start *every* probe at register 0, in
|
710
|
+
order. This has a large allocation performance impact in practice.
|
711
|
+
|
712
|
+
For each register in probe order, we probe the allocation map, and
|
713
|
+
gather, simultaneously, several results: (i) whether the entire range
|
714
|
+
is free; (ii) if not, the vector of all conflicting bundles, *and* the
|
715
|
+
highest weight among those bundles; (iii) if not, the *first* conflict
|
716
|
+
point.
|
717
|
+
|
718
|
+
We do this by iterating over all liveranges in the preg's btree that
|
719
|
+
overlap with each range in the current bundle. This iteration is
|
720
|
+
somewhat subtle due to multiple "equal" keys (see above where we
|
721
|
+
describe the use of the btree). It is also adaptive for performance
|
722
|
+
reasons: it initially obtains an iterator into the btree corresponding
|
723
|
+
to the start of the first range in the bundle, and concurrently
|
724
|
+
iterates through both the btree and the bundle. However, if there is a
|
725
|
+
large gap in the bundle, this might require skipping many irrelevant
|
726
|
+
entries in the btree. So, if we skip too many entries (heuristically,
|
727
|
+
16, right now), we do another lookup from scratch in the btree for the
|
728
|
+
start of the next range in the bundle. This balances between the two
|
729
|
+
cases: dense bundle, where O(1) iteration through the btree is faster,
|
730
|
+
and sparse bundle, where O(log n) lookup for each entry is better.
|
731
|
+
|
732
|
+
### Decision: Allocate, Evict, or Split
|
733
|
+
|
734
|
+
First, the "allocate" case is easy: if, during our register probe
|
735
|
+
loop, we find a physical register whose allocations do not overlap
|
736
|
+
this bundle, then we allocate this register; done!
|
737
|
+
|
738
|
+
If not, then we need to decide whether to evict some conflicting
|
739
|
+
bundles and retry, or to split the current bundle into smaller pieces
|
740
|
+
that may have better luck.
|
741
|
+
|
742
|
+
A bit about our split strategy first: contrary to the IonMonkey
|
743
|
+
allocator which inspired much of our design, we do *not* have a list
|
744
|
+
of split strategies that split one bundle into many pieces at
|
745
|
+
once. Instead, each iteration of the allocation loop splits at most
|
746
|
+
*once*. This simplifies the splitting code greatly, but also turns out
|
747
|
+
to be a nice heuristic: we split at the point that the bundle first
|
748
|
+
encounters a conflict for a particular preg assignment, then we hint
|
749
|
+
that preg for the first (pre-conflict) piece when we retry. In this
|
750
|
+
way, we always make forward progress -- one piece of the bundle is
|
751
|
+
always allocated -- and splits are informed by the actual situation at
|
752
|
+
hand, rather than best guesses. Also note that while this may appear
|
753
|
+
at first to be a greedy algorithm, it still allows backtracking: the
|
754
|
+
first half of the split bundle, which we *can* now assign to a preg,
|
755
|
+
does not necessarily remain on that preg forever (it can still be
|
756
|
+
evicted later). It is just a split that is known to make at least one
|
757
|
+
part of the allocation problem solvable.
|
758
|
+
|
759
|
+
To determine whether to split or evict, we track our best options: as
|
760
|
+
we probe, we track the "lowest cost eviction option", which is a set
|
761
|
+
of bundles and the maximum weight in that set of bundles. We also
|
762
|
+
track the "lowest cost split option", which is the cost (more below),
|
763
|
+
the point at which to split, and the register for this option.
|
764
|
+
|
765
|
+
For each register we probe, if there is a conflict but none of the
|
766
|
+
conflicts are fixed allocations, we receive a vector of bundles that
|
767
|
+
conflicted, and also separately, the first conflicting program
|
768
|
+
point. We update the lowest-cost eviction option if the cost (max
|
769
|
+
weight) of the conflicting bundles is less than the current best. We
|
770
|
+
update the lowest-cost split option if the cost is less as well,
|
771
|
+
according to the following definition of cost: a split's cost is the
|
772
|
+
cost of its move, as defined by the weight of a normal def operand at
|
773
|
+
the split program point, plus the cost of all bundles beyond the split
|
774
|
+
point (which will still be conflicts even after the split).
|
775
|
+
|
776
|
+
If there is a conflict with a fixed allocation, then eviction is not
|
777
|
+
an option, but we can still compute the candidate split point and cost
|
778
|
+
in the same way as above.
|
779
|
+
|
780
|
+
Finally, as an optimization, we pass in the current best cost to the
|
781
|
+
btree probe inner loop; if, while probing, we have already exceeded
|
782
|
+
the best cost, we stop early (this improves allocation time without
|
783
|
+
affecting the result).
|
784
|
+
|
785
|
+
Once we have the best cost for split and evict options, we split if
|
786
|
+
(i) the bundle is not already a minimal bundle, and (ii) we've already
|
787
|
+
evicted once in this toplevel iteration without success, or the weight
|
788
|
+
of the current bundle is less than the eviction cost. We then requeue
|
789
|
+
*both* resulting halves of the bundle with the preg that resulted in
|
790
|
+
this option as the register hint. Otherwise, we evict all conflicting
|
791
|
+
bundles and try again.
|
792
|
+
|
793
|
+
Note that the split cost does not actually play into the above (split
|
794
|
+
vs. evict) decision; it is only used to choose *which* split is
|
795
|
+
best. This is equivalent to saying: we never evict if the current
|
796
|
+
bundle is less important than the evicted bundles, even if the split
|
797
|
+
is more expensive still. This is important for forward progress, and
|
798
|
+
the case where the split would be even more expensive should be very
|
799
|
+
very rare (it would have to come from a costly move in the middle of
|
800
|
+
an inner loop).
|
801
|
+
|
802
|
+
### How to Split
|
803
|
+
|
804
|
+
The actual split procedure is fairly simple. We are given a bundle and
|
805
|
+
a split-point. We create a new bundle to take on the second half
|
806
|
+
("rest") of the original. We find the point in the liverange vector
|
807
|
+
that corresponds to the split, and distribute appropriately. If the
|
808
|
+
split-point lands in the middle of a liverange, then we split that
|
809
|
+
liverange as well.
|
810
|
+
|
811
|
+
In the case that a new liverange is created, we add the liverange to
|
812
|
+
the corresponding vreg liverange vector as well. Note that, as described
|
813
|
+
above, the vreg's liverange vector is unsorted while splitting is
|
814
|
+
occurring (because we do not need to traverse it or do any lookups
|
815
|
+
during this phase); so we just append.
|
816
|
+
|
817
|
+
The splitting code also supports a "minimal split", in which it simply
|
818
|
+
peels off the first use. This is used to ensure forward progress when
|
819
|
+
a bundle has conflicting requirements within it (see above).
|
820
|
+
|
821
|
+
#### Spill Bundle and Splitting
|
822
|
+
|
823
|
+
Once a split occurs, however, it turns out that we can improve results
|
824
|
+
by doing a little cleanup. Once we distribute a bundle's liveranges
|
825
|
+
across two half-bundles, we postprocess by trimming a bit.
|
826
|
+
|
827
|
+
In particular, if we see that the "loose ends" around the split point
|
828
|
+
extend beyond uses, we will create and move ranges to a spill
|
829
|
+
bundle. That is: if the last liverange in the first-half bundle
|
830
|
+
extends beyond its last use, we trim that part off into an empty (no
|
831
|
+
uses) liverange and place that liverange in the spill
|
832
|
+
bundle. Likewise, if the first liverange in the second-half bundle
|
833
|
+
starts before its first use, we trim that part off into an empty
|
834
|
+
liverange and place it in the spill bundle.
|
835
|
+
|
836
|
+
This is, empirically, an improvement: it reduces register contention
|
837
|
+
and makes splitting more effective. The intuition is twofold: (i) it
|
838
|
+
is better to put all of the "flow-through" parts of a vreg's liveness
|
839
|
+
into one bundle that is never split, and can be spilled to the stack
|
840
|
+
if needed, to avoid unnecessary moves; and (ii) if contention is high
|
841
|
+
enough to cause splitting, it is more likely there will be an actual
|
842
|
+
stack spill, and if this is the case, it is better to do the store
|
843
|
+
just after the last use and reload just before the first use of the
|
844
|
+
respective bundles.
|
845
|
+
|
846
|
+
## Second-Chance Allocation: Spilled Bundles
|
847
|
+
|
848
|
+
Once the main allocation loop terminates, when all bundles have either
|
849
|
+
been allocated or punted to the "spilled bundles" vector, we do
|
850
|
+
second-chance allocation. This is a simpler loop that never evicts and
|
851
|
+
never splits. Instead, each bundle gets one second chance, in which it
|
852
|
+
can probe pregs and attempt to allocate. If it fails, it will actually
|
853
|
+
live on the stack.
|
854
|
+
|
855
|
+
This is correct because we are careful to only place bundles on the
|
856
|
+
spilled-bundles vector that are *allowed* to live on the
|
857
|
+
stack. Specifically, only the canonical spill bundles (which will
|
858
|
+
contain only empty ranges) and other bundles that have an "any" or
|
859
|
+
"unknown" requirement are placed here (but *not* "stack" requirements;
|
860
|
+
those *must* be on the stack, so do not undergo second-chance
|
861
|
+
allocation).
|
862
|
+
|
863
|
+
At the end of this process, we have marked spillsets as required
|
864
|
+
whenever at least one bundle in the spillset actually requires a stack
|
865
|
+
slot. We can then allocate slots to the spillsets.
|
866
|
+
|
867
|
+
## Spillslot Allocation
|
868
|
+
|
869
|
+
We must allocate space on the stack, denoted by an abstract index
|
870
|
+
space, to each spillset that requires it, and for the liveranges in
|
871
|
+
which it requires it.
|
872
|
+
|
873
|
+
To facilitate this, we keep a btree per spillslot in the same way we
|
874
|
+
do per preg. We will allocate spillsets to slots in a way that avoids
|
875
|
+
interference.
|
876
|
+
|
877
|
+
Note that we actually overapproximate the required ranges for each
|
878
|
+
spillset in order to improve the behavior of a later phase (redundant
|
879
|
+
move elimination). Specifically, when we allocate a slot for a
|
880
|
+
spillset, we reserve that slot for *all* of the liveranges of *every*
|
881
|
+
vreg that is assigned to that spillset (due to merging rules that
|
882
|
+
initially merge one-vreg bundles into final merged bundles, there will
|
883
|
+
be no overlaps here). In other words, we rule out interleaving of
|
884
|
+
completely different values in the same slot, though bundle merging
|
885
|
+
does mean that potentially many (non-interfering) vregs may share
|
886
|
+
it. This provides the important property that if a vreg has been
|
887
|
+
reloaded, but not modified, its spillslot *still contains the
|
888
|
+
up-to-date value* (because the slot is reserved for all liveranges of
|
889
|
+
the vreg). This enables us to avoid another store to the spillslot
|
890
|
+
later if there is another spilled range.
|
891
|
+
|
892
|
+
We perform probing in a way that is somewhat different than for
|
893
|
+
registers, because the spillslot space is conceptually infinite. We
|
894
|
+
can thus optimize for slightly better allocation performance by giving
|
895
|
+
up and allocating a new slot at any time.
|
896
|
+
|
897
|
+
For each size class, we keep a linked list of slots. When we need to
|
898
|
+
allocate a spillset to a slot, we traverse down the list and try a
|
899
|
+
fixed number of slots. If we find one that fits the spillset's ranges,
|
900
|
+
we allocate, and we remove the slot from its current place in the list
|
901
|
+
and append to the end. In this way, it is deprioritized from probing
|
902
|
+
"for a while", which tends to reduce contention. This is a simple way
|
903
|
+
to round-robin between slots. If we don't find one that fits after a
|
904
|
+
fixed number of probes, we allocate a new slot.
|
905
|
+
|
906
|
+
And with that, we have valid allocations for all vregs for all points
|
907
|
+
that they are live! Now we just need to modify the program to reify
|
908
|
+
these choices.
|
909
|
+
|
910
|
+
## Allocation Assignment
|
911
|
+
|
912
|
+
The first step in reifying the allocation is to iterate through all
|
913
|
+
mentions of a vreg and fill in the resulting `Allocation` array with
|
914
|
+
the appropriate allocations. We do this by simply traversing
|
915
|
+
liveranges per vreg, looking up the allocation by observing the bundle
|
916
|
+
(and spillset if no specific allocation for the bundle), and for each
|
917
|
+
use, filling in the slot according to the saved progpoint/slot info in
|
918
|
+
the use data.
|
919
|
+
|
920
|
+
## Move Generation
|
921
|
+
|
922
|
+
The more difficult half of the reification step is generating the
|
923
|
+
*moves* that will put the values in the right spots.
|
924
|
+
|
925
|
+
There are two sources of moves that we must generate. The first are
|
926
|
+
moves between different ranges of the same vreg, as the split pieces
|
927
|
+
of that vreg's original bundle may have been assigned to different
|
928
|
+
locations. The second are moves that result from move semantics in the
|
929
|
+
input program: assignments from blockparam args on branches to the
|
930
|
+
target block's params.
|
931
|
+
|
932
|
+
Moves are tricky to handle efficiently because they join two
|
933
|
+
potentially very different locations in the program (in the case of
|
934
|
+
control-flow-edge moves). In order to avoid the need for random
|
935
|
+
lookups, which are a cache-locality nightmare even if we have O(log n)
|
936
|
+
lookups, we instead take a scan-sort-scan approach.
|
937
|
+
|
938
|
+
First, we scan over each vreg's liveranges, find the allocation for
|
939
|
+
each, and for each move that comes *to* or *from* this liverange,
|
940
|
+
generate a "half-move". The key idea is that we generate a record for
|
941
|
+
each "side" of the move, and these records are keyed in a way that
|
942
|
+
after a sort, the "from" and "to" ends will be consecutive. We can
|
943
|
+
sort the vector of halfmoves once (this is expensive, but not as
|
944
|
+
expensive as many separate pointer-chasing lookups), then scan it
|
945
|
+
again to actually generate the move instructions.
|
946
|
+
|
947
|
+
To enable the sort to work, half-moves are sorted by a key that is
|
948
|
+
equivalent to the tuple (from-block, to-block, to-vreg, kind), where
|
949
|
+
`kind` is "source" or "dest". For each key, the payload is an
|
950
|
+
allocation. The fields in this tuple are carefully chosen: we know all
|
951
|
+
of them at every location we generate a halfmove, without expensive
|
952
|
+
lookups, and sorting by this key will make the source and all dests
|
953
|
+
(there can be more than one) contiguous in the final order.
|
954
|
+
|
955
|
+
Half-moves are generated for several situations. First, at the start
|
956
|
+
of every block covered by a liverange, we can generate "dest"
|
957
|
+
half-moves for blockparams, and at the end of every block covered by a
|
958
|
+
liverange, we can generate "source" half-moves for blockparam args on
|
959
|
+
branches. Incidentally, this is the reason that `blockparam_ins` and
|
960
|
+
`blockparam_outs` are sorted tuple-vectors whose tuples begin with
|
961
|
+
(vreg, block, ...): this is the order in which we do the toplevel scan
|
962
|
+
over allocations.
|
963
|
+
|
964
|
+
Second, at every block edge, if the vreg is live in any pred (at
|
965
|
+
block-start) or succ (at block-end), we generate a half-move to
|
966
|
+
transfer the vreg to its own location in the connected block.
|
967
|
+
|
968
|
+
This completes the "edge-moves". We sort the half-move array and then
|
969
|
+
have all of the alloc-to-alloc pairs on a given (from-block, to-block)
|
970
|
+
edge.
|
971
|
+
|
972
|
+
Next, when a live-range ends and another begins for the same vreg in
|
973
|
+
the same block (i.e., a split in the middle of a block), we know both
|
974
|
+
sides of the move immediately (because it is the same vreg and we can
|
975
|
+
look up the adjacent allocation easily), and we can generate that
|
976
|
+
move.
|
977
|
+
|
978
|
+
Finally, we generate moves to fix up multi-fixed-reg-constraint
|
979
|
+
situations, and make reused inputs work, as described earlier.
|
980
|
+
|
981
|
+
## Move Resolution
|
982
|
+
|
983
|
+
During this whole discussion, we have described "generating moves",
|
984
|
+
but we have not said what that meant. Note that in many cases, there
|
985
|
+
are several moves at a particular program point that semantically
|
986
|
+
happen *in parallel*. For example, if multiple vregs change
|
987
|
+
allocations between two instructions, all of those moves happen as
|
988
|
+
part of one parallel permutation. Similarly, blockparams have
|
989
|
+
parallel-assignment semantics. We thus enqueue all the moves that we
|
990
|
+
generate at program points and resolve them into sequences of
|
991
|
+
sequential moves that can actually be lowered to move instructions in
|
992
|
+
the machine code.
|
993
|
+
|
994
|
+
First, a word on *move priorities*. There are different kinds of moves
|
995
|
+
that are generated between instructions, and we have to ensure that
|
996
|
+
some happen before others, i.e., *not* in parallel. For example, a
|
997
|
+
vreg might change allocation (due to a split) before an instruction,
|
998
|
+
then be copied to an output register for an output with a reused-input
|
999
|
+
policy. The latter move must happen *after* the vreg has been moved
|
1000
|
+
into its location for this instruction.
|
1001
|
+
|
1002
|
+
To enable this, we define "move priorities", which are a logical
|
1003
|
+
extension of program points (i.e., they are sub-points) that enable
|
1004
|
+
finer-grained ordering of moves. We currently have the following
|
1005
|
+
priorities:
|
1006
|
+
|
1007
|
+
- In-edge moves, to place edge-moves before the first instruction in a
|
1008
|
+
block.
|
1009
|
+
- Regular, used for vreg movement between allocations.
|
1010
|
+
- Multi-fixed-reg, used for moves that handle the
|
1011
|
+
single-vreg-in-multiple-fixed-pregs constraint case.
|
1012
|
+
- Reused-input, used for implementing outputs with reused-input policies.
|
1013
|
+
- Out-edge moves, to place edge-moves after the last instruction
|
1014
|
+
(prior to the branch) in a block.
|
1015
|
+
|
1016
|
+
Every move is statically given one of these priorities by the code
|
1017
|
+
that generates it.
|
1018
|
+
|
1019
|
+
We collect moves with (prog-point, prio) keys, and we sort by those
|
1020
|
+
keys. We then have, for each such key, a set of moves that
|
1021
|
+
semantically happen in parallel.
|
1022
|
+
|
1023
|
+
We then resolve those moves using a parallel-move resolver, as we now
|
1024
|
+
describe.
|
1025
|
+
|
1026
|
+
### Parallel-Move Resolver
|
1027
|
+
|
1028
|
+
The fundamental issue that arises when resolving parallel moves to
|
1029
|
+
sequential moves is *overlap*: some of the moves may overwrite
|
1030
|
+
registers that other moves use as sources. We must carefully order
|
1031
|
+
moves so that this does not clobber values incorrectly.
|
1032
|
+
|
1033
|
+
We first check if such overlap occurs. If it does not (this is
|
1034
|
+
actually the most common case), the sequence of parallel moves can be
|
1035
|
+
emitted as sequential moves directly. Done!
|
1036
|
+
|
1037
|
+
Otherwise, we have to order the moves carefully. Furthermore, if there
|
1038
|
+
is a *cycle* anywhere among the moves, we will need a scratch
|
1039
|
+
register. (Consider, e.g., t0 := t1 and t1 := t0 in parallel: with
|
1040
|
+
only move instructions and no direct "exchange" instruction, we cannot
|
1041
|
+
reify this without a third register.)
|
1042
|
+
|
1043
|
+
We first compute a mapping from each move instruction to the move
|
1044
|
+
instruction, if any, that it must precede. Note that there can be only
|
1045
|
+
one such move for a given move, because each destination can be
|
1046
|
+
written only once; so a move might be constrained only before the one
|
1047
|
+
move that overwrites its source. (This will be important in a bit!)
|
1048
|
+
|
1049
|
+
Our task is now to find an ordering of moves that respects these
|
1050
|
+
dependencies. To do so, we perform a depth-first search on the graph
|
1051
|
+
induced by the dependencies, which will generate a sequence of
|
1052
|
+
sequential moves in reverse order. We keep a stack of moves; we start
|
1053
|
+
with any move that has not been visited yet; in each iteration, if the
|
1054
|
+
top-of-stack has no out-edge to another move (does not need to come
|
1055
|
+
before any others), then push it to a result vector, followed by all
|
1056
|
+
others on the stack (in popped order). If it does have an out-edge and
|
1057
|
+
the target is already visited and not on the stack anymore (so already
|
1058
|
+
emitted), likewise, emit this move and the rest on the stack. If it
|
1059
|
+
has an out-edge to a move not yet visited, push on the stack and
|
1060
|
+
continue. Otherwise, if out-edge to a move currently on the stack, we
|
1061
|
+
have found a cycle. In this case, we emit the moves on the stack with
|
1062
|
+
a modification: the first move writes to a scratch register, and we
|
1063
|
+
emit an additional move that moves from the scratch to the first
|
1064
|
+
move's dest. This breaks the cycle.
|
1065
|
+
|
1066
|
+
The astute reader may notice that this sounds like a canonical
|
1067
|
+
application of Tarjan's algorithm for finding SCCs (strongly-connected
|
1068
|
+
components). Why don't we have the full complexity of that algorithm?
|
1069
|
+
In particular, *why* can we emit the cycle *right away* once we find
|
1070
|
+
it, rather than ensuring that we have gotten all of the SCC first?
|
1071
|
+
|
1072
|
+
The answer is that because there is only *one* out-edge at most (a
|
1073
|
+
move can only require preceding *one* other move), all SCCs must be
|
1074
|
+
simple cycles. This means that once we have found a cycle, no other
|
1075
|
+
nodes (moves) can be part of the SCC, because every node's single
|
1076
|
+
out-edge is already accounted for. This is what allows us to avoid a
|
1077
|
+
fully general SCC algorithm.
|
1078
|
+
|
1079
|
+
Once the vector of moves in-reverse has been constructed, we reverse
|
1080
|
+
it and return.
|
1081
|
+
|
1082
|
+
Note that this "move resolver" is fuzzed separately with a simple
|
1083
|
+
symbolic move simulator (the `moves` fuzz-target).
|
1084
|
+
|
1085
|
+
### Stack-to-Stack Moves
|
1086
|
+
|
1087
|
+
There is one potentially difficult situation that could arise from the
|
1088
|
+
move-resolution logic so far: if a vreg moves from one spillslot to
|
1089
|
+
another, this implies a memory-to-memory move, which most machine
|
1090
|
+
architectures cannot handle natively. It would be much nicer if we
|
1091
|
+
could ensure within the regalloc that this never occurs.
|
1092
|
+
|
1093
|
+
This is in fact possible to do in a postprocessing step. We iterate
|
1094
|
+
through the sequential moves, tracking whether the scratch register is
|
1095
|
+
in use (has been written). When we see a stack-to-stack move: (i) if
|
1096
|
+
the scratch register is not in use, generate a stack-to-scratch move
|
1097
|
+
and scratch-to-stack move; otherwise, (ii) if the scratch register is
|
1098
|
+
in use, allocate an "extra spillslot" if one has not already been
|
1099
|
+
allocated, move the scratch reg to that, do the above stack-to-scratch
|
1100
|
+
/ scratch-to-stack sequence, then reload the scratch reg from the
|
1101
|
+
extra spillslot.
|
1102
|
+
|
1103
|
+
## Redundant-Spill/Load Elimination
|
1104
|
+
|
1105
|
+
As a final step before returning the vector of program edits to the
|
1106
|
+
client, we perform one optimization: redundant-spill/load elimination.
|
1107
|
+
|
1108
|
+
To understand the need for this, consider what will occur when a vreg
|
1109
|
+
is (i) defined once, (ii) used many times, and (iii) spilled multiple
|
1110
|
+
times between some of the uses: with the design described above, we
|
1111
|
+
will move the value from the preg to the stack after every segment of
|
1112
|
+
uses, and then reload it when the next use occurs. However, only the
|
1113
|
+
first spill is actually needed; as we noted above, we allocate
|
1114
|
+
spillslots so that the slot that corresponded to the vreg at the first
|
1115
|
+
spill will always be reserved for that vreg as long as it is live. If
|
1116
|
+
no other defs or mods occur, the value in the slot can be reloaded,
|
1117
|
+
and need not be written back every time.
|
1118
|
+
|
1119
|
+
This inefficiency is a result of our invariant that a vreg lives in
|
1120
|
+
exactly one place at a time, and these locations are joined by
|
1121
|
+
moves. This is a simple and effective design to use for most of the
|
1122
|
+
allocation pipeline, but falls flat here. It is especially inefficient
|
1123
|
+
when the unnecessary spill occurs in an inner loop. (E.g.: value
|
1124
|
+
defined at top of function is spilled, then used once in the middle of
|
1125
|
+
an inner loop body.)
|
1126
|
+
|
1127
|
+
The opposite case can also sometimes occur, though it is rarer: a
|
1128
|
+
value is loaded into a register, spilled, and then reloaded into the
|
1129
|
+
same register. This can happen when hinting is successful at getting
|
1130
|
+
several segments of a vreg to use the same preg, but splitting has
|
1131
|
+
trimmed part of the liverange between uses and put it in the spill
|
1132
|
+
bundle, and the spill bundle did not get a reg.
|
1133
|
+
|
1134
|
+
In order to resolve this inefficiency, we implement a general
|
1135
|
+
redundant-spill/load elimination pass (an even more general solution
|
1136
|
+
would be a full redundant-move elimination pass, but we focus on moves
|
1137
|
+
that are spills/loads to contain the complexity for now). This pass
|
1138
|
+
tracks, for every allocation (reg or spillslot), whether it is a copy
|
1139
|
+
of another allocation. This state is invalidated whenever either that
|
1140
|
+
allocation or the allocation of which it is a copy is
|
1141
|
+
overwritten. When we see a move instruction, if the destination is
|
1142
|
+
already a copy of the source, we elide the move. (There are some
|
1143
|
+
additional complexities to preserve checker metadata which we do not
|
1144
|
+
describe here.)
|
1145
|
+
|
1146
|
+
Note that this could, in principle, be done as a fixpoint analysis
|
1147
|
+
over the CFG; it must be, if we try to preserve state across
|
1148
|
+
blocks. This is because a location is only a copy of another if that
|
1149
|
+
is true on every incoming edge. However, to avoid the cost and
|
1150
|
+
complexity of doing such an analysis, we instead take the much simpler
|
1151
|
+
approach of doing only an intra-block analysis. This turns out to be
|
1152
|
+
sufficient to remove most redundant moves, especially in the common
|
1153
|
+
case of a single use of an otherwise-spilled value.
|
1154
|
+
|
1155
|
+
Note that there is an opportunity to do better: as we only accept SSA
|
1156
|
+
code we would know that a value could not be redefined once written.
|
1157
|
+
|
1158
|
+
# Future Plans
|
1159
|
+
|
1160
|
+
## Better Split Heuristics
|
1161
|
+
|
1162
|
+
We have spent quite some effort trying to improve splitting behavior,
|
1163
|
+
and it is now generally decent, but more work could be done here,
|
1164
|
+
especially with regard to the interaction between splits and the loop
|
1165
|
+
nest.
|
1166
|
+
|
1167
|
+
# Appendix: Comparison to IonMonkey Allocator
|
1168
|
+
|
1169
|
+
There are a number of differences between the [IonMonkey
|
1170
|
+
allocator](https://searchfox.org/mozilla-central/source/js/src/jit/BacktrackingAllocator.cpp)
|
1171
|
+
and this one. While this allocator initially began as an attempt to
|
1172
|
+
clone IonMonkey's, it has drifted significantly as we optimized the
|
1173
|
+
design (especially after we built the regalloc.rs shim and had to
|
1174
|
+
adapt to its code style); it is easier at this point to name the
|
1175
|
+
similarities than the differences.
|
1176
|
+
|
1177
|
+
* The core abstractions of "liverange", "bundle", "vreg", "preg", and
|
1178
|
+
"operand" (with policies/constraints) are the same.
|
1179
|
+
|
1180
|
+
* The overall allocator pipeline is the same, and the top-level
|
1181
|
+
structure of each stage should look similar. Both allocators begin
|
1182
|
+
by computing liveranges, then merging bundles, then handling bundles
|
1183
|
+
and splitting/evicting as necessary, then doing second-chance
|
1184
|
+
allocation, then reifying the decisions.
|
1185
|
+
|
1186
|
+
* The cost functions are very similar, though the heuristics that make
|
1187
|
+
decisions based on them are not.
|
1188
|
+
|
1189
|
+
Several notable high-level differences are:
|
1190
|
+
|
1191
|
+
* There are [fuzz/fuzz_targets/](many different fuzz targets) that
|
1192
|
+
exercise the allocator, including a full symbolic checker
|
1193
|
+
(`ion_checker` target) based on the [symbolic checker in
|
1194
|
+
regalloc.rs](https://cfallin.org/blog/2021/03/15/cranelift-isel-3/)
|
1195
|
+
and, e.g., a targetted fuzzer for the parallel move-resolution
|
1196
|
+
algorithm (`moves`) and the SSA generator used for generating cases
|
1197
|
+
for the other fuzz targets (`ssagen`).
|
1198
|
+
|
1199
|
+
* The data-structure invariants are simplified. While the IonMonkey
|
1200
|
+
allocator allowed for LiveRanges and Bundles to overlap in certain
|
1201
|
+
cases, this allocator sticks to a strict invariant: ranges do not
|
1202
|
+
overlap in bundles, and bundles do not overlap. There are other
|
1203
|
+
examples too: e.g., the definition of minimal bundles is very simple
|
1204
|
+
and does not depend on scanning the code at all. In general, we
|
1205
|
+
should be able to state simple invariants and see by inspection (as
|
1206
|
+
well as fuzzing -- see above) that they hold.
|
1207
|
+
|
1208
|
+
* The data structures themselves are simplified. Where IonMonkey uses
|
1209
|
+
linked lists in many places, this allocator stores simple inline
|
1210
|
+
smallvecs of liveranges on bundles and vregs, and smallvecs of uses
|
1211
|
+
on liveranges. We also (i) find a way to construct liveranges
|
1212
|
+
in-order immediately, without any need for splicing, unlike
|
1213
|
+
IonMonkey, and (ii) relax sorting invariants where possible to allow
|
1214
|
+
for cheap append operations in many cases.
|
1215
|
+
|
1216
|
+
* The splitting heuristics are significantly reworked. Whereas
|
1217
|
+
IonMonkey has an all-at-once approach to splitting an entire bundle,
|
1218
|
+
and has a list of complex heuristics to choose where to split, this
|
1219
|
+
allocator does conflict-based splitting, and tries to decide whether
|
1220
|
+
to split or evict and which split to take based on cost heuristics.
|
1221
|
+
|
1222
|
+
* The liverange computation is exact, whereas IonMonkey approximates
|
1223
|
+
using a single-pass algorithm that makes vregs live across entire
|
1224
|
+
loop bodies. We have found that precise liveness improves allocation
|
1225
|
+
performance and generated code quality, even though the liveness
|
1226
|
+
itself is slightly more expensive to compute.
|
1227
|
+
|
1228
|
+
* Many of the algorithms in the IonMonkey allocator are built with
|
1229
|
+
helper functions that do linear scans. These "small quadratic" loops
|
1230
|
+
are likely not a huge issue in practice, but nevertheless have the
|
1231
|
+
potential to be in corner cases. As much as possible, all work in
|
1232
|
+
this allocator is done in linear scans.
|
1233
|
+
|
1234
|
+
* There are novel schemes for solving certain interesting design
|
1235
|
+
challenges. One example: in IonMonkey, liveranges are connected
|
1236
|
+
across blocks by, when reaching one end of a control-flow edge in a
|
1237
|
+
scan, doing a lookup of the allocation at the other end. This is in
|
1238
|
+
principle a linear lookup (so quadratic overall). We instead
|
1239
|
+
generate a vector of "half-moves", keyed on the edge and from/to
|
1240
|
+
vregs, with each holding one of the allocations. By sorting and then
|
1241
|
+
scanning this vector, we can generate all edge moves in one linear
|
1242
|
+
scan. There are a number of other examples of simplifications: for
|
1243
|
+
example, we handle multiple conflicting
|
1244
|
+
physical-register-constrained uses of a vreg in a single instruction
|
1245
|
+
by recording a copy to do in a side-table, then removing constraints
|
1246
|
+
for the core regalloc. Ion instead has to tweak its definition of
|
1247
|
+
minimal bundles and create two liveranges that overlap (!) to
|
1248
|
+
represent the two uses.
|
1249
|
+
|
1250
|
+
* Using block parameters rather than phi-nodes significantly
|
1251
|
+
simplifies handling of inter-block data movement. IonMonkey had to
|
1252
|
+
special-case phis in many ways because they are actually quite
|
1253
|
+
weird: their uses happen semantically in other blocks, and their
|
1254
|
+
defs happen in parallel at the top of the block. Block parameters
|
1255
|
+
naturally and explicitly reprsent these semantics in a direct way.
|
1256
|
+
|
1257
|
+
* The allocator supports irreducible control flow and arbitrary block
|
1258
|
+
ordering (its only CFG requirement is that critical edges are
|
1259
|
+
split).
|
1260
|
+
|
1261
|
+
* The allocator supports non-SSA code, and has native support for
|
1262
|
+
handling program moves specially.
|
1263
|
+
|
1264
|
+
# Appendix: Performance-Tuning Lessons
|
1265
|
+
|
1266
|
+
In the course of optimizing the allocator's performance, we found a
|
1267
|
+
number of general principles:
|
1268
|
+
|
1269
|
+
* We got substantial performance speedups from using vectors rather
|
1270
|
+
than linked lists everywhere. This is well-known, but nevertheless,
|
1271
|
+
it took some thought to work out how to avoid the need for any
|
1272
|
+
splicing, and it turns out that even when our design is slightly
|
1273
|
+
less efficient asymptotically (e.g., apend-and-re-sort rather than
|
1274
|
+
linear-time merge of two sorted liverange lists when merging
|
1275
|
+
bundles), it is faster.
|
1276
|
+
|
1277
|
+
* We initially used a direct translation of IonMonkey's splay tree as
|
1278
|
+
an allocation map for each PReg. This turned out to be significantly
|
1279
|
+
(!) less efficient than Rust's built-in BTree data structures, for
|
1280
|
+
the usual cache-efficiency vs. pointer-chasing reasons.
|
1281
|
+
|
1282
|
+
* We initially used dense bitvecs, as IonMonkey does, for
|
1283
|
+
livein/liveout bits. It turned out that a chunked sparse design (see
|
1284
|
+
below) was much more efficient.
|
1285
|
+
|
1286
|
+
* Precise liveness significantly improves performance because it
|
1287
|
+
reduces the size of liveranges (i.e., interference), and probing
|
1288
|
+
registers with liveranges is the most significant hot inner
|
1289
|
+
loop. Paying a fraction of a percent runtime for the iterative
|
1290
|
+
dataflow algorithm to get precise bitsets is more than worth it.
|
1291
|
+
|
1292
|
+
* The randomized probing of registers was a huge win: as above, the
|
1293
|
+
probing is very expensive, and reducing the average number of probes
|
1294
|
+
it takes to find a free register is very important.
|
1295
|
+
|
1296
|
+
* In general, single-pass algorithms and design of data structures to
|
1297
|
+
enable them are important. For example, the half-move technique
|
1298
|
+
avoids the need to do any O(log n) search at all, and is relatively
|
1299
|
+
cache-efficient. As another example, a side-effect of the precise
|
1300
|
+
liveness was that we could then process operands within blocks in
|
1301
|
+
actual instruction order (in reverse), which allowed us to simply
|
1302
|
+
append liveranges to in-progress vreg liverange vectors and then
|
1303
|
+
reverse at the end. The expensive part is a single pass; only the
|
1304
|
+
bitset computation is a fixpoint loop.
|
1305
|
+
|
1306
|
+
* Sorts are better than always-sorted data structures (like btrees):
|
1307
|
+
they amortize all the comparison and update cost to one phase, and
|
1308
|
+
this phase is much more cache-friendly than a bunch of spread-out
|
1309
|
+
updates.
|
1310
|
+
|
1311
|
+
* Take care of basic data structures and their operator definitions!
|
1312
|
+
We initially used the auto-derived comparator on ProgPoint, and let
|
1313
|
+
ProgPoint be a normal struct (with a u32 inst index and a
|
1314
|
+
Befor/After enum). The comparator for this, used in many sorting
|
1315
|
+
inner loops, was a compound thing with conditionals. Instead, pack
|
1316
|
+
them in a u32 and do a simple compare (and save half the memory as
|
1317
|
+
well). Likewise, the half-move key is a single value packed in a
|
1318
|
+
u64; this is far more efficient than the tuple comparator on a
|
1319
|
+
4-tuple, and the half-move sort (which can be a few percent or more
|
1320
|
+
of total allocation time) became multiple times cheaper.
|
1321
|
+
|
1322
|
+
# Appendix: Data Structure: Chunked Sparse BitVec
|
1323
|
+
|
1324
|
+
We use a "chunked sparse bitvec" to store liveness information, which
|
1325
|
+
is just a set of VReg indices. The design is fairly simple: the
|
1326
|
+
toplevel is a HashMap from "chunk" to a `u64`, and each `u64`
|
1327
|
+
represents 64 contiguous indices.
|
1328
|
+
|
1329
|
+
The intuition is that while the vreg sets are likely sparse overall,
|
1330
|
+
they will probably be dense within small regions of the index
|
1331
|
+
space. For example, in the Nth block in a function, the values that
|
1332
|
+
flow from block N-1 will largely be almost-contiguous vreg indices, if
|
1333
|
+
vregs are allocated in sequence down the function body. Or, at least,
|
1334
|
+
they will be some local vregs together with a few defined at the top
|
1335
|
+
of the function; two separate chunks will cover that.
|
1336
|
+
|
1337
|
+
We tried a number of other designs as well. Initially we used a simple
|
1338
|
+
dense bitvec, but this was prohibitively expensive: O(n^2) space when
|
1339
|
+
the real need is closer to O(n) (i.e., a classic sparse matrix). We
|
1340
|
+
also tried a hybrid scheme that kept a vector of indices when small
|
1341
|
+
and used either a bitvec or a hashset when large. This did not perform
|
1342
|
+
as well because (i) it was less memory-efficient (the chunking helps
|
1343
|
+
with this) and (ii) insertions are more expensive when they always
|
1344
|
+
require a full hashset/hashmap insert.
|
1345
|
+
|
1346
|
+
# Appendix: Fuzzing
|
1347
|
+
|
1348
|
+
We have five fuzz targets: `ssagen`, `domtree`, `moves`, `ion`, and
|
1349
|
+
`ion_checker`.
|
1350
|
+
|
1351
|
+
## SSAGen
|
1352
|
+
|
1353
|
+
The SSAGen target tests our SSA generator, which generates cases for
|
1354
|
+
the full allocator fuzz targets. The SSA generator is careful to
|
1355
|
+
always generate a valid CFG, with split critical edges, and valid SSA,
|
1356
|
+
so that we never have to throw out a test input before we reach the
|
1357
|
+
allocator itself. (An alternative fuzzing approach randomly generates
|
1358
|
+
programs and then throws out those that do not meet certain conditions
|
1359
|
+
before using them as legitimate testcases; this is much simpler, but
|
1360
|
+
less efficient.)
|
1361
|
+
|
1362
|
+
To generate a valid CFG, with no unreachable blocks and with no
|
1363
|
+
critical edges, the generator (i) glues together units of either one
|
1364
|
+
or three blocks (A->B, A->C), forming either a straight-through
|
1365
|
+
section or a conditional. These are glued together into a "spine", and
|
1366
|
+
the conditionals (the "C" block), where they exist, are then linked to
|
1367
|
+
a random target block chosen among the main blocks of these one- or
|
1368
|
+
three-block units. The targets are chosen either randomly, for
|
1369
|
+
potentially irreducible CFGs, or in a way that ensures proper nesting
|
1370
|
+
of loop backedges, if a structured CFG is requested.
|
1371
|
+
|
1372
|
+
SSA is generated by first choosing which vregs will be defined in each
|
1373
|
+
block, and which will be defined as blockparams vs. instruction
|
1374
|
+
defs. Instructions are then generated, with operands chosen among the
|
1375
|
+
"available" vregs: those defined so far in the current block and all
|
1376
|
+
of those in any other block that dominates this one.
|
1377
|
+
|
1378
|
+
The SSAGen fuzz target runs the above code generator against an SSA
|
1379
|
+
validator, and thus ensures that it will only generate valid SSA code.
|
1380
|
+
|
1381
|
+
## Domtree
|
1382
|
+
|
1383
|
+
The `domtree` fuzz target computes dominance using the algorithm that
|
1384
|
+
we use elsewhere in our CFG analysis, and then walks a
|
1385
|
+
randomly-generated path through the CFG. It checks that the dominance
|
1386
|
+
definition ("a dom b if any path from entry to b must pass through a")
|
1387
|
+
is consistent with this particular randomly-chosen path.
|
1388
|
+
|
1389
|
+
## Moves
|
1390
|
+
|
1391
|
+
The `moves` fuzz target tests the parallel move resolver. It generates
|
1392
|
+
a random sequence of parallel moves, careful to ensure that each
|
1393
|
+
destination is written only once. It then runs the parallel move
|
1394
|
+
resolver, and then *abstractly interprets* the resulting sequential
|
1395
|
+
series of moves, thus determining which inputs flow to which
|
1396
|
+
outputs. This must match the original set of parallel moves.
|
1397
|
+
|
1398
|
+
## Ion and Ion-checker
|
1399
|
+
|
1400
|
+
The `ion` fuzz target runs the allocator over test programs generated
|
1401
|
+
by SSAGen. It does not validate the output; it only tests that the
|
1402
|
+
allocator runs to completion and does not panic. This was used mainly
|
1403
|
+
during development, and is now less useful than the checker-based
|
1404
|
+
target.
|
1405
|
+
|
1406
|
+
The `ion_checker` fuzz target runs the allocator's result through a
|
1407
|
+
symbolic checker, which is adapted from the one developed for
|
1408
|
+
regalloc.rs (see [this blog
|
1409
|
+
post](https://cfallin.org/blog/2021/01/22/cranelift-isel-2/) for more
|
1410
|
+
details). This is the most useful fuzz target in the fuzzing suite,
|
1411
|
+
and has found many bugs in development.
|