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- checksums.yaml +4 -4
- data/Cargo.lock +234 -173
- data/ext/Cargo.toml +7 -7
- data/ext/cargo-vendor/addr2line-0.20.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/addr2line-0.20.0/CHANGELOG.md +321 -0
- data/ext/cargo-vendor/addr2line-0.20.0/Cargo.lock +548 -0
- data/ext/cargo-vendor/addr2line-0.20.0/Cargo.toml +145 -0
- data/ext/cargo-vendor/addr2line-0.20.0/examples/addr2line.rs +306 -0
- data/ext/cargo-vendor/addr2line-0.20.0/src/builtin_split_dwarf_loader.rs +164 -0
- data/ext/cargo-vendor/addr2line-0.20.0/src/function.rs +555 -0
- data/ext/cargo-vendor/addr2line-0.20.0/src/lazy.rs +31 -0
- data/ext/cargo-vendor/addr2line-0.20.0/src/lib.rs +1729 -0
- data/ext/cargo-vendor/addr2line-0.20.0/tests/correctness.rs +126 -0
- data/ext/cargo-vendor/addr2line-0.20.0/tests/output_equivalence.rs +135 -0
- data/ext/cargo-vendor/addr2line-0.20.0/tests/parse.rs +114 -0
- data/ext/cargo-vendor/bytes-1.4.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/bytes-1.4.0/Cargo.toml +54 -0
- data/ext/cargo-vendor/bytes-1.4.0/LICENSE +25 -0
- data/ext/cargo-vendor/bytes-1.4.0/README.md +56 -0
- data/ext/cargo-vendor/bytes-1.4.0/benches/buf.rs +186 -0
- data/ext/cargo-vendor/bytes-1.4.0/benches/bytes.rs +120 -0
- data/ext/cargo-vendor/bytes-1.4.0/benches/bytes_mut.rs +266 -0
- data/ext/cargo-vendor/bytes-1.4.0/ci/miri.sh +11 -0
- data/ext/cargo-vendor/bytes-1.4.0/ci/test-stable.sh +28 -0
- data/ext/cargo-vendor/bytes-1.4.0/ci/tsan.sh +13 -0
- data/ext/cargo-vendor/bytes-1.4.0/clippy.toml +1 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/buf_impl.rs +1394 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/buf_mut.rs +1493 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/chain.rs +242 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/iter.rs +130 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/limit.rs +75 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/mod.rs +41 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/reader.rs +81 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/take.rs +155 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/uninit_slice.rs +213 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/vec_deque.rs +22 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/buf/writer.rs +88 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/bytes.rs +1304 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/bytes_mut.rs +1812 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/fmt/debug.rs +49 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/fmt/hex.rs +37 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/fmt/mod.rs +5 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/lib.rs +117 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/loom.rs +30 -0
- data/ext/cargo-vendor/bytes-1.4.0/src/serde.rs +89 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_buf.rs +120 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_buf_mut.rs +178 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_bytes.rs +1210 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_bytes_odd_alloc.rs +97 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_bytes_vec_alloc.rs +143 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_chain.rs +177 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_debug.rs +35 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_iter.rs +21 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_reader.rs +29 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_serde.rs +20 -0
- data/ext/cargo-vendor/bytes-1.4.0/tests/test_take.rs +32 -0
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- data/ext/cargo-vendor/cap-fs-ext-2.0.0/src/is_file_read_write.rs +61 -0
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- data/ext/cargo-vendor/cap-primitives-2.0.0/src/net/pool.rs +284 -0
- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/copy_impl.rs +233 -0
- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/metadata_ext.rs +384 -0
- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/oflags.rs +98 -0
- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/open_unchecked.rs +71 -0
- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/reopen_impl.rs +18 -0
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- data/ext/cargo-vendor/cap-primitives-2.0.0/src/rustix/fs/times.rs +61 -0
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- data/ext/cargo-vendor/cap-primitives-2.0.0/src/windows/fs/open_unchecked.rs +228 -0
- data/ext/cargo-vendor/cap-rand-2.0.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cap-std-2.0.0/Cargo.toml +67 -0
- data/ext/cargo-vendor/cap-std-2.0.0/build.rs +41 -0
- data/ext/cargo-vendor/cap-std-2.0.0/src/fs/file.rs +614 -0
- data/ext/cargo-vendor/cap-std-2.0.0/src/fs_utf8/file.rs +608 -0
- data/ext/cargo-vendor/cap-std-2.0.0/src/lib.rs +51 -0
- data/ext/cargo-vendor/cap-std-2.0.0/src/net/udp_socket.rs +418 -0
- data/ext/cargo-vendor/cap-time-ext-2.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cap-time-ext-2.0.0/Cargo.toml +42 -0
- data/ext/cargo-vendor/cap-time-ext-2.0.0/src/monotonic_clock.rs +62 -0
- data/ext/cargo-vendor/cap-time-ext-2.0.0/src/system_clock.rs +59 -0
- data/ext/cargo-vendor/cranelift-bforest-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.99.1/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/Cargo.toml +159 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/cursor.rs +644 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/ir/extfunc.rs +411 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/ir/function.rs +469 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/ir/globalvalue.rs +155 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/ir/mod.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/aarch64/abi.rs +1543 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/aarch64/inst/emit.rs +3919 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/aarch64/inst/mod.rs +3039 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/aarch64/inst.isle +4048 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/aarch64/lower/isle.rs +873 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/abi.rs +985 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/inst/emit.rs +3254 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/inst/mod.rs +2125 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/inst.isle +2972 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/riscv64/lower/isle.rs +620 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/x64/abi.rs +1204 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/isa/x64/lower.isle +4651 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/lib.rs +140 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/machinst/abi.rs +2641 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/machinst/buffer.rs +2365 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/machinst/isle.rs +837 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/machinst/lower.rs +1393 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/machinst/vcode.rs +1591 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/opts/cprop.isle +200 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/opts/icmp.isle +177 -0
- data/ext/cargo-vendor/cranelift-codegen-0.99.1/src/value_label.rs +32 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/Cargo.toml +26 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/gen_inst.rs +1785 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/isa/arm64.rs +53 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/isa/mod.rs +66 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/isa/riscv64.rs +101 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/isa/s390x.rs +39 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/isa/x86.rs +401 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/lib.rs +59 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.99.1/src/shared/mod.rs +88 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.99.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.99.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.99.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-frontend-0.99.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.99.1/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-frontend-0.99.1/src/lib.rs +204 -0
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- data/ext/cargo-vendor/cranelift-isle-0.99.1/Cargo.toml +37 -0
- data/ext/cargo-vendor/cranelift-native-0.99.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-wasm-0.99.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/cranelift-wasm-0.99.1/src/code_translator.rs +3608 -0
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- data/ext/cargo-vendor/cranelift-wasm-0.99.1/src/environ/spec.rs +913 -0
- data/ext/cargo-vendor/cranelift-wasm-0.99.1/src/func_translator.rs +431 -0
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- data/ext/cargo-vendor/cranelift-wasm-0.99.1/tests/wasm_testsuite.rs +153 -0
- data/ext/cargo-vendor/fs-set-times-0.20.0/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/futures-0.3.28/tests/eventual.rs +179 -0
- data/ext/cargo-vendor/futures-0.3.28/tests/future_abortable.rs +44 -0
- data/ext/cargo-vendor/futures-0.3.28/tests/future_basic_combinators.rs +104 -0
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- data/ext/cargo-vendor/futures-0.3.28/tests/future_join.rs +32 -0
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- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/parse-fail/world-top-level-func.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/parse-fail/world-top-level-func2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/parse-fail/world-top-level-func2.wit.result +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/type-then-eof.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/types.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/use-chain.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/use.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/versions/deps/a1/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/versions/deps/a2/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/versions/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/wasi.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/world-iface-no-collide.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/world-implicit-import2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/world-implicit-import3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/world-top-level-funcs.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.8.0 → wit-parser-0.9.2}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,836 +0,0 @@
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use crate::ir::{BlockCall, Value, ValueList};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use smallvec::SmallVec;
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use std::cell::Cell;
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pub use super::MachLabel;
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use super::RetPair;
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pub use crate::ir::{
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condcodes, condcodes::CondCode, dynamic_to_fixed, ArgumentExtension, ArgumentPurpose, Constant,
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DynamicStackSlot, ExternalName, FuncRef, GlobalValue, Immediate, SigRef, StackSlot,
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};
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pub use crate::isa::unwind::UnwindInst;
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pub use crate::isa::TargetIsa;
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pub use crate::machinst::{
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ABIArg, ABIArgSlot, InputSourceInst, Lower, LowerBackend, RealReg, Reg, RelocDistance, Sig,
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VCodeInst, Writable,
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};
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pub use crate::settings::{OptLevel, TlsModel};
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pub type Unit = ();
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pub type ValueSlice = (ValueList, usize);
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pub type ValueArray2 = [Value; 2];
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pub type ValueArray3 = [Value; 3];
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pub type BlockArray2 = [BlockCall; 2];
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pub type WritableReg = Writable<Reg>;
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pub type VecRetPair = Vec<RetPair>;
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pub type VecMask = Vec<u8>;
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pub type ValueRegs = crate::machinst::ValueRegs<Reg>;
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pub type WritableValueRegs = crate::machinst::ValueRegs<WritableReg>;
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pub type InstOutput = SmallVec<[ValueRegs; 2]>;
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pub type InstOutputBuilder = Cell<InstOutput>;
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pub type BoxExternalName = Box<ExternalName>;
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pub type Range = (usize, usize);
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pub enum RangeView {
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Empty,
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NonEmpty { index: usize, rest: Range },
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}
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/// Helper macro to define methods in `prelude.isle` within `impl Context for
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/// ...` for each backend. These methods are shared amongst all backends.
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#[macro_export]
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#[doc(hidden)]
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macro_rules! isle_lower_prelude_methods {
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() => {
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isle_common_prelude_methods!();
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#[inline]
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fn value_type(&mut self, val: Value) -> Type {
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self.lower_ctx.dfg().value_type(val)
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}
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#[inline]
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fn value_reg(&mut self, reg: Reg) -> ValueRegs {
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ValueRegs::one(reg)
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}
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#[inline]
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fn value_regs(&mut self, r1: Reg, r2: Reg) -> ValueRegs {
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ValueRegs::two(r1, r2)
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}
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#[inline]
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fn value_regs_invalid(&mut self) -> ValueRegs {
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ValueRegs::invalid()
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}
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#[inline]
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fn output_none(&mut self) -> InstOutput {
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smallvec::smallvec![]
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}
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#[inline]
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fn output(&mut self, regs: ValueRegs) -> InstOutput {
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smallvec::smallvec![regs]
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}
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#[inline]
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fn output_pair(&mut self, r1: ValueRegs, r2: ValueRegs) -> InstOutput {
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smallvec::smallvec![r1, r2]
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}
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#[inline]
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fn output_builder_new(&mut self) -> InstOutputBuilder {
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std::cell::Cell::new(InstOutput::new())
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}
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#[inline]
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fn output_builder_push(&mut self, builder: &InstOutputBuilder, regs: ValueRegs) -> Unit {
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let mut vec = builder.take();
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vec.push(regs);
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builder.set(vec);
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}
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#[inline]
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fn output_builder_finish(&mut self, builder: &InstOutputBuilder) -> InstOutput {
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builder.take()
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}
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#[inline]
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fn temp_writable_reg(&mut self, ty: Type) -> WritableReg {
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let value_regs = self.lower_ctx.alloc_tmp(ty);
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value_regs.only_reg().unwrap()
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}
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#[inline]
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fn is_valid_reg(&mut self, reg: Reg) -> bool {
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use crate::machinst::valueregs::InvalidSentinel;
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!reg.is_invalid_sentinel()
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}
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#[inline]
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fn invalid_reg(&mut self) -> Reg {
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use crate::machinst::valueregs::InvalidSentinel;
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Reg::invalid_sentinel()
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}
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#[inline]
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fn mark_value_used(&mut self, val: Value) {
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self.lower_ctx.increment_lowered_uses(val);
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}
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#[inline]
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fn put_in_reg(&mut self, val: Value) -> Reg {
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self.put_in_regs(val).only_reg().unwrap()
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}
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#[inline]
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fn put_in_regs(&mut self, val: Value) -> ValueRegs {
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self.lower_ctx.put_value_in_regs(val)
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}
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#[inline]
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fn ensure_in_vreg(&mut self, reg: Reg, ty: Type) -> Reg {
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self.lower_ctx.ensure_in_vreg(reg, ty)
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}
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#[inline]
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fn value_regs_get(&mut self, regs: ValueRegs, i: usize) -> Reg {
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regs.regs()[i]
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}
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#[inline]
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fn value_regs_len(&mut self, regs: ValueRegs) -> usize {
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regs.regs().len()
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}
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#[inline]
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fn value_list_slice(&mut self, list: ValueList) -> ValueSlice {
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(list, 0)
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}
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#[inline]
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fn value_slice_empty(&mut self, slice: ValueSlice) -> Option<()> {
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let (list, off) = slice;
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if off >= list.len(&self.lower_ctx.dfg().value_lists) {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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fn value_slice_unwrap(&mut self, slice: ValueSlice) -> Option<(Value, ValueSlice)> {
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let (list, off) = slice;
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if let Some(val) = list.get(off, &self.lower_ctx.dfg().value_lists) {
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Some((val, (list, off + 1)))
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} else {
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None
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}
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}
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#[inline]
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fn value_slice_len(&mut self, slice: ValueSlice) -> usize {
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let (list, off) = slice;
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list.len(&self.lower_ctx.dfg().value_lists) - off
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}
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#[inline]
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fn value_slice_get(&mut self, slice: ValueSlice, idx: usize) -> Value {
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let (list, off) = slice;
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list.get(off + idx, &self.lower_ctx.dfg().value_lists)
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.unwrap()
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}
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#[inline]
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fn writable_reg_to_reg(&mut self, r: WritableReg) -> Reg {
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r.to_reg()
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}
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#[inline]
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fn inst_results(&mut self, inst: Inst) -> ValueSlice {
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(self.lower_ctx.dfg().inst_results_list(inst), 0)
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}
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#[inline]
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fn first_result(&mut self, inst: Inst) -> Option<Value> {
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self.lower_ctx.dfg().inst_results(inst).first().copied()
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}
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#[inline]
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fn inst_data(&mut self, inst: Inst) -> InstructionData {
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self.lower_ctx.dfg().insts[inst]
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}
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#[inline]
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fn def_inst(&mut self, val: Value) -> Option<Inst> {
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self.lower_ctx.dfg().value_def(val).inst()
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}
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fn zero_value(&mut self, value: Value) -> Option<Value> {
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let insn = self.def_inst(value);
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if insn.is_some() {
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let insn = insn.unwrap();
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let inst_data = self.lower_ctx.data(insn);
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match inst_data {
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InstructionData::Unary {
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opcode: Opcode::Splat,
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arg,
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} => {
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let arg = arg.clone();
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return self.zero_value(arg);
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}
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InstructionData::UnaryConst {
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opcode: Opcode::Vconst,
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constant_handle,
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} => {
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let constant_data =
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self.lower_ctx.get_constant_data(*constant_handle).clone();
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if constant_data.into_vec().iter().any(|&x| x != 0) {
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return None;
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} else {
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return Some(value);
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}
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}
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InstructionData::UnaryImm { imm, .. } => {
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return Some(value);
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} else {
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return None;
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}
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}
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InstructionData::UnaryIeee32 { imm, .. } => {
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if imm.bits() == 0 {
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return Some(value);
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} else {
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return None;
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}
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}
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InstructionData::UnaryIeee64 { imm, .. } => {
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if imm.bits() == 0 {
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return Some(value);
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} else {
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return None;
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}
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}
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_ => None,
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}
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} else {
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None
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}
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}
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#[inline]
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fn tls_model(&mut self, _: Type) -> TlsModel {
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self.backend.flags().tls_model()
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}
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#[inline]
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fn tls_model_is_elf_gd(&mut self) -> Option<()> {
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if self.backend.flags().tls_model() == TlsModel::ElfGd {
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Some(())
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} else {
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None
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}
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}
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#[inline]
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280
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fn tls_model_is_macho(&mut self) -> Option<()> {
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if self.backend.flags().tls_model() == TlsModel::Macho {
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Some(())
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} else {
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None
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}
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}
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287
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#[inline]
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289
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fn tls_model_is_coff(&mut self) -> Option<()> {
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290
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if self.backend.flags().tls_model() == TlsModel::Coff {
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Some(())
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292
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} else {
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None
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}
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295
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}
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296
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297
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#[inline]
|
298
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fn preserve_frame_pointers(&mut self) -> Option<()> {
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299
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if self.backend.flags().preserve_frame_pointers() {
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300
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Some(())
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301
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} else {
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None
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303
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}
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304
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}
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305
|
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|
306
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#[inline]
|
307
|
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fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) {
|
308
|
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let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref];
|
309
|
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(
|
310
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funcdata.signature,
|
311
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funcdata.name.clone(),
|
312
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funcdata.reloc_distance(),
|
313
|
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)
|
314
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}
|
315
|
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|
316
|
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#[inline]
|
317
|
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fn box_external_name(&mut self, extname: ExternalName) -> BoxExternalName {
|
318
|
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Box::new(extname)
|
319
|
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}
|
320
|
-
|
321
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#[inline]
|
322
|
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fn symbol_value_data(
|
323
|
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&mut self,
|
324
|
-
global_value: GlobalValue,
|
325
|
-
) -> Option<(ExternalName, RelocDistance, i64)> {
|
326
|
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let (name, reloc, offset) = self.lower_ctx.symbol_value_data(global_value)?;
|
327
|
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Some((name.clone(), reloc, offset))
|
328
|
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}
|
329
|
-
|
330
|
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#[inline]
|
331
|
-
fn reloc_distance_near(&mut self, dist: RelocDistance) -> Option<()> {
|
332
|
-
if dist == RelocDistance::Near {
|
333
|
-
Some(())
|
334
|
-
} else {
|
335
|
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None
|
336
|
-
}
|
337
|
-
}
|
338
|
-
|
339
|
-
#[inline]
|
340
|
-
fn u128_from_immediate(&mut self, imm: Immediate) -> Option<u128> {
|
341
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
342
|
-
Some(u128::from_le_bytes(bytes.try_into().ok()?))
|
343
|
-
}
|
344
|
-
|
345
|
-
#[inline]
|
346
|
-
fn vconst_from_immediate(&mut self, imm: Immediate) -> Option<VCodeConstant> {
|
347
|
-
Some(self.lower_ctx.use_constant(VCodeConstantData::Generated(
|
348
|
-
self.lower_ctx.get_immediate_data(imm).clone(),
|
349
|
-
)))
|
350
|
-
}
|
351
|
-
|
352
|
-
#[inline]
|
353
|
-
fn vec_mask_from_immediate(&mut self, imm: Immediate) -> Option<VecMask> {
|
354
|
-
let data = self.lower_ctx.get_immediate_data(imm);
|
355
|
-
if data.len() == 16 {
|
356
|
-
Some(Vec::from(data.as_slice()))
|
357
|
-
} else {
|
358
|
-
None
|
359
|
-
}
|
360
|
-
}
|
361
|
-
|
362
|
-
#[inline]
|
363
|
-
fn u64_from_constant(&mut self, constant: Constant) -> Option<u64> {
|
364
|
-
let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
|
365
|
-
Some(u64::from_le_bytes(bytes.try_into().ok()?))
|
366
|
-
}
|
367
|
-
|
368
|
-
#[inline]
|
369
|
-
fn u128_from_constant(&mut self, constant: Constant) -> Option<u128> {
|
370
|
-
let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
|
371
|
-
Some(u128::from_le_bytes(bytes.try_into().ok()?))
|
372
|
-
}
|
373
|
-
|
374
|
-
#[inline]
|
375
|
-
fn emit_u64_le_const(&mut self, value: u64) -> VCodeConstant {
|
376
|
-
let data = VCodeConstantData::U64(value.to_le_bytes());
|
377
|
-
self.lower_ctx.use_constant(data)
|
378
|
-
}
|
379
|
-
|
380
|
-
#[inline]
|
381
|
-
fn emit_u128_le_const(&mut self, value: u128) -> VCodeConstant {
|
382
|
-
let data = VCodeConstantData::Generated(value.to_le_bytes().as_slice().into());
|
383
|
-
self.lower_ctx.use_constant(data)
|
384
|
-
}
|
385
|
-
|
386
|
-
#[inline]
|
387
|
-
fn const_to_vconst(&mut self, constant: Constant) -> VCodeConstant {
|
388
|
-
self.lower_ctx.use_constant(VCodeConstantData::Pool(
|
389
|
-
constant,
|
390
|
-
self.lower_ctx.get_constant_data(constant).clone(),
|
391
|
-
))
|
392
|
-
}
|
393
|
-
|
394
|
-
fn only_writable_reg(&mut self, regs: WritableValueRegs) -> Option<WritableReg> {
|
395
|
-
regs.only_reg()
|
396
|
-
}
|
397
|
-
|
398
|
-
fn writable_regs_get(&mut self, regs: WritableValueRegs, idx: usize) -> WritableReg {
|
399
|
-
regs.regs()[idx]
|
400
|
-
}
|
401
|
-
|
402
|
-
fn abi_num_args(&mut self, abi: Sig) -> usize {
|
403
|
-
self.lower_ctx.sigs().num_args(abi)
|
404
|
-
}
|
405
|
-
|
406
|
-
fn abi_get_arg(&mut self, abi: Sig, idx: usize) -> ABIArg {
|
407
|
-
self.lower_ctx.sigs().get_arg(abi, idx)
|
408
|
-
}
|
409
|
-
|
410
|
-
fn abi_num_rets(&mut self, abi: Sig) -> usize {
|
411
|
-
self.lower_ctx.sigs().num_rets(abi)
|
412
|
-
}
|
413
|
-
|
414
|
-
fn abi_get_ret(&mut self, abi: Sig, idx: usize) -> ABIArg {
|
415
|
-
self.lower_ctx.sigs().get_ret(abi, idx)
|
416
|
-
}
|
417
|
-
|
418
|
-
fn abi_ret_arg(&mut self, abi: Sig) -> Option<ABIArg> {
|
419
|
-
self.lower_ctx.sigs().get_ret_arg(abi)
|
420
|
-
}
|
421
|
-
|
422
|
-
fn abi_no_ret_arg(&mut self, abi: Sig) -> Option<()> {
|
423
|
-
if let Some(_) = self.lower_ctx.sigs().get_ret_arg(abi) {
|
424
|
-
None
|
425
|
-
} else {
|
426
|
-
Some(())
|
427
|
-
}
|
428
|
-
}
|
429
|
-
|
430
|
-
fn abi_sized_stack_arg_space(&mut self, abi: Sig) -> i64 {
|
431
|
-
self.lower_ctx.sigs()[abi].sized_stack_arg_space()
|
432
|
-
}
|
433
|
-
|
434
|
-
fn abi_sized_stack_ret_space(&mut self, abi: Sig) -> i64 {
|
435
|
-
self.lower_ctx.sigs()[abi].sized_stack_ret_space()
|
436
|
-
}
|
437
|
-
|
438
|
-
fn abi_arg_only_slot(&mut self, arg: &ABIArg) -> Option<ABIArgSlot> {
|
439
|
-
match arg {
|
440
|
-
&ABIArg::Slots { ref slots, .. } => {
|
441
|
-
if slots.len() == 1 {
|
442
|
-
Some(slots[0])
|
443
|
-
} else {
|
444
|
-
None
|
445
|
-
}
|
446
|
-
}
|
447
|
-
_ => None,
|
448
|
-
}
|
449
|
-
}
|
450
|
-
|
451
|
-
fn abi_arg_struct_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, u64)> {
|
452
|
-
match arg {
|
453
|
-
&ABIArg::StructArg {
|
454
|
-
pointer,
|
455
|
-
offset,
|
456
|
-
size,
|
457
|
-
..
|
458
|
-
} => {
|
459
|
-
if let Some(pointer) = pointer {
|
460
|
-
Some((pointer, offset, size))
|
461
|
-
} else {
|
462
|
-
None
|
463
|
-
}
|
464
|
-
}
|
465
|
-
_ => None,
|
466
|
-
}
|
467
|
-
}
|
468
|
-
|
469
|
-
fn abi_arg_implicit_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, Type)> {
|
470
|
-
match arg {
|
471
|
-
&ABIArg::ImplicitPtrArg {
|
472
|
-
pointer,
|
473
|
-
offset,
|
474
|
-
ty,
|
475
|
-
..
|
476
|
-
} => Some((pointer, offset, ty)),
|
477
|
-
_ => None,
|
478
|
-
}
|
479
|
-
}
|
480
|
-
|
481
|
-
fn abi_stackslot_addr(
|
482
|
-
&mut self,
|
483
|
-
dst: WritableReg,
|
484
|
-
stack_slot: StackSlot,
|
485
|
-
offset: Offset32,
|
486
|
-
) -> MInst {
|
487
|
-
let offset = u32::try_from(i32::from(offset)).unwrap();
|
488
|
-
self.lower_ctx
|
489
|
-
.abi()
|
490
|
-
.sized_stackslot_addr(stack_slot, offset, dst)
|
491
|
-
}
|
492
|
-
|
493
|
-
fn abi_dynamic_stackslot_addr(
|
494
|
-
&mut self,
|
495
|
-
dst: WritableReg,
|
496
|
-
stack_slot: DynamicStackSlot,
|
497
|
-
) -> MInst {
|
498
|
-
assert!(self
|
499
|
-
.lower_ctx
|
500
|
-
.abi()
|
501
|
-
.dynamic_stackslot_offsets()
|
502
|
-
.is_valid(stack_slot));
|
503
|
-
self.lower_ctx.abi().dynamic_stackslot_addr(stack_slot, dst)
|
504
|
-
}
|
505
|
-
|
506
|
-
fn real_reg_to_reg(&mut self, reg: RealReg) -> Reg {
|
507
|
-
Reg::from(reg)
|
508
|
-
}
|
509
|
-
|
510
|
-
fn real_reg_to_writable_reg(&mut self, reg: RealReg) -> WritableReg {
|
511
|
-
Writable::from_reg(Reg::from(reg))
|
512
|
-
}
|
513
|
-
|
514
|
-
fn is_sinkable_inst(&mut self, val: Value) -> Option<Inst> {
|
515
|
-
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
516
|
-
|
517
|
-
if let InputSourceInst::UniqueUse(inst, _) = input.inst {
|
518
|
-
Some(inst)
|
519
|
-
} else {
|
520
|
-
None
|
521
|
-
}
|
522
|
-
}
|
523
|
-
|
524
|
-
#[inline]
|
525
|
-
fn sink_inst(&mut self, inst: Inst) {
|
526
|
-
self.lower_ctx.sink_inst(inst);
|
527
|
-
}
|
528
|
-
|
529
|
-
#[inline]
|
530
|
-
fn maybe_uextend(&mut self, value: Value) -> Option<Value> {
|
531
|
-
if let Some(def_inst) = self.def_inst(value) {
|
532
|
-
if let InstructionData::Unary {
|
533
|
-
opcode: Opcode::Uextend,
|
534
|
-
arg,
|
535
|
-
} = self.lower_ctx.data(def_inst)
|
536
|
-
{
|
537
|
-
return Some(*arg);
|
538
|
-
}
|
539
|
-
}
|
540
|
-
|
541
|
-
Some(value)
|
542
|
-
}
|
543
|
-
|
544
|
-
#[inline]
|
545
|
-
fn preg_to_reg(&mut self, preg: PReg) -> Reg {
|
546
|
-
preg.into()
|
547
|
-
}
|
548
|
-
|
549
|
-
#[inline]
|
550
|
-
fn gen_move(&mut self, ty: Type, dst: WritableReg, src: Reg) -> MInst {
|
551
|
-
MInst::gen_move(dst, src, ty)
|
552
|
-
}
|
553
|
-
|
554
|
-
/// Generate the return instruction.
|
555
|
-
fn gen_return(&mut self, (list, off): ValueSlice) {
|
556
|
-
let rets = (off..list.len(&self.lower_ctx.dfg().value_lists))
|
557
|
-
.map(|ix| {
|
558
|
-
let val = list.get(ix, &self.lower_ctx.dfg().value_lists).unwrap();
|
559
|
-
self.put_in_regs(val)
|
560
|
-
})
|
561
|
-
.collect();
|
562
|
-
self.lower_ctx.gen_return(rets);
|
563
|
-
}
|
564
|
-
|
565
|
-
/// Same as `shuffle32_from_imm`, but for 64-bit lane shuffles.
|
566
|
-
fn shuffle64_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8)> {
|
567
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
568
|
-
|
569
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
570
|
-
Some((
|
571
|
-
shuffle_imm_as_le_lane_idx(8, &bytes[0..8])?,
|
572
|
-
shuffle_imm_as_le_lane_idx(8, &bytes[8..16])?,
|
573
|
-
))
|
574
|
-
}
|
575
|
-
|
576
|
-
/// Attempts to interpret the shuffle immediate `imm` as a shuffle of
|
577
|
-
/// 32-bit lanes, returning four integers, each of which is less than 8,
|
578
|
-
/// which represents a permutation of 32-bit lanes as specified by
|
579
|
-
/// `imm`.
|
580
|
-
///
|
581
|
-
/// For example the shuffle immediate
|
582
|
-
///
|
583
|
-
/// `0 1 2 3 8 9 10 11 16 17 18 19 24 25 26 27`
|
584
|
-
///
|
585
|
-
/// would return `Some((0, 2, 4, 6))`.
|
586
|
-
fn shuffle32_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8, u8, u8)> {
|
587
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
588
|
-
|
589
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
590
|
-
Some((
|
591
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[0..4])?,
|
592
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[4..8])?,
|
593
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[8..12])?,
|
594
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[12..16])?,
|
595
|
-
))
|
596
|
-
}
|
597
|
-
|
598
|
-
/// Same as `shuffle32_from_imm`, but for 16-bit lane shuffles.
|
599
|
-
fn shuffle16_from_imm(
|
600
|
-
&mut self,
|
601
|
-
imm: Immediate,
|
602
|
-
) -> Option<(u8, u8, u8, u8, u8, u8, u8, u8)> {
|
603
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
604
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
605
|
-
Some((
|
606
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[0..2])?,
|
607
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[2..4])?,
|
608
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[4..6])?,
|
609
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[6..8])?,
|
610
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[8..10])?,
|
611
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[10..12])?,
|
612
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[12..14])?,
|
613
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[14..16])?,
|
614
|
-
))
|
615
|
-
}
|
616
|
-
|
617
|
-
fn safe_divisor_from_imm64(&mut self, ty: Type, val: Imm64) -> Option<u64> {
|
618
|
-
let minus_one = if ty.bytes() == 8 {
|
619
|
-
-1
|
620
|
-
} else {
|
621
|
-
(1 << (ty.bytes() * 8)) - 1
|
622
|
-
};
|
623
|
-
let bits = val.bits() & minus_one;
|
624
|
-
if bits == 0 || bits == minus_one {
|
625
|
-
None
|
626
|
-
} else {
|
627
|
-
Some(bits as u64)
|
628
|
-
}
|
629
|
-
}
|
630
|
-
};
|
631
|
-
}
|
632
|
-
|
633
|
-
/// Returns the `size`-byte lane referred to by the shuffle immediate specified
|
634
|
-
/// in `bytes`.
|
635
|
-
///
|
636
|
-
/// This helper is used by `shuffleNN_from_imm` above and is used to interpret a
|
637
|
-
/// byte-based shuffle as a higher-level shuffle of bigger lanes. This will see
|
638
|
-
/// if the `bytes` specified, which must have `size` length, specifies a lane in
|
639
|
-
/// vectors aligned to a `size`-byte boundary.
|
640
|
-
///
|
641
|
-
/// Returns `None` if `bytes` doesn't specify a `size`-byte lane aligned
|
642
|
-
/// appropriately, or returns `Some(n)` where `n` is the index of the lane being
|
643
|
-
/// shuffled.
|
644
|
-
pub fn shuffle_imm_as_le_lane_idx(size: u8, bytes: &[u8]) -> Option<u8> {
|
645
|
-
assert_eq!(bytes.len(), usize::from(size));
|
646
|
-
|
647
|
-
// The first index in `bytes` must be aligned to a `size` boundary for the
|
648
|
-
// bytes to be a valid specifier for a lane of `size` bytes.
|
649
|
-
if bytes[0] % size != 0 {
|
650
|
-
return None;
|
651
|
-
}
|
652
|
-
|
653
|
-
// Afterwards the bytes must all be one larger than the prior to specify a
|
654
|
-
// contiguous sequence of bytes that's being shuffled. Basically `bytes`
|
655
|
-
// must refer to the entire `size`-byte lane, in little-endian order.
|
656
|
-
for i in 0..size - 1 {
|
657
|
-
let idx = usize::from(i);
|
658
|
-
if bytes[idx] + 1 != bytes[idx + 1] {
|
659
|
-
return None;
|
660
|
-
}
|
661
|
-
}
|
662
|
-
|
663
|
-
// All of the `bytes` are in-order, meaning that this is a valid shuffle
|
664
|
-
// immediate to specify a lane of `size` bytes. The index, when viewed as
|
665
|
-
// `size`-byte immediates, will be the first byte divided by the byte size.
|
666
|
-
Some(bytes[0] / size)
|
667
|
-
}
|
668
|
-
|
669
|
-
/// Helpers specifically for machines that use `abi::CallSite`.
|
670
|
-
#[macro_export]
|
671
|
-
#[doc(hidden)]
|
672
|
-
macro_rules! isle_prelude_caller_methods {
|
673
|
-
($abispec:ty, $abicaller:ty) => {
|
674
|
-
fn gen_call(
|
675
|
-
&mut self,
|
676
|
-
sig_ref: SigRef,
|
677
|
-
extname: ExternalName,
|
678
|
-
dist: RelocDistance,
|
679
|
-
args @ (inputs, off): ValueSlice,
|
680
|
-
) -> InstOutput {
|
681
|
-
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
682
|
-
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
683
|
-
let num_rets = sig.returns.len();
|
684
|
-
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
685
|
-
let caller = <$abicaller>::from_func(
|
686
|
-
self.lower_ctx.sigs(),
|
687
|
-
sig_ref,
|
688
|
-
&extname,
|
689
|
-
dist,
|
690
|
-
caller_conv,
|
691
|
-
self.backend.flags().clone(),
|
692
|
-
);
|
693
|
-
|
694
|
-
assert_eq!(
|
695
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
696
|
-
sig.params.len()
|
697
|
-
);
|
698
|
-
|
699
|
-
self.gen_call_common(abi, num_rets, caller, args)
|
700
|
-
}
|
701
|
-
|
702
|
-
fn gen_call_indirect(
|
703
|
-
&mut self,
|
704
|
-
sig_ref: SigRef,
|
705
|
-
val: Value,
|
706
|
-
args @ (inputs, off): ValueSlice,
|
707
|
-
) -> InstOutput {
|
708
|
-
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
709
|
-
let ptr = self.put_in_reg(val);
|
710
|
-
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
711
|
-
let num_rets = sig.returns.len();
|
712
|
-
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
713
|
-
let caller = <$abicaller>::from_ptr(
|
714
|
-
self.lower_ctx.sigs(),
|
715
|
-
sig_ref,
|
716
|
-
ptr,
|
717
|
-
Opcode::CallIndirect,
|
718
|
-
caller_conv,
|
719
|
-
self.backend.flags().clone(),
|
720
|
-
);
|
721
|
-
|
722
|
-
assert_eq!(
|
723
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
724
|
-
sig.params.len()
|
725
|
-
);
|
726
|
-
|
727
|
-
self.gen_call_common(abi, num_rets, caller, args)
|
728
|
-
}
|
729
|
-
};
|
730
|
-
}
|
731
|
-
|
732
|
-
/// Helpers for the above ISLE prelude implementations. Meant to go
|
733
|
-
/// inside the `impl` for the context type, not the trait impl.
|
734
|
-
#[macro_export]
|
735
|
-
#[doc(hidden)]
|
736
|
-
macro_rules! isle_prelude_method_helpers {
|
737
|
-
($abicaller:ty) => {
|
738
|
-
fn gen_call_common_args(&mut self, call_site: &mut $abicaller, (inputs, off): ValueSlice) {
|
739
|
-
let num_args = call_site.num_args(self.lower_ctx.sigs());
|
740
|
-
|
741
|
-
assert_eq!(
|
742
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
743
|
-
num_args
|
744
|
-
);
|
745
|
-
let mut arg_regs = vec![];
|
746
|
-
for i in 0..num_args {
|
747
|
-
let input = inputs
|
748
|
-
.get(off + i, &self.lower_ctx.dfg().value_lists)
|
749
|
-
.unwrap();
|
750
|
-
arg_regs.push(self.put_in_regs(input));
|
751
|
-
}
|
752
|
-
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
753
|
-
call_site.emit_copy_regs_to_buffer(self.lower_ctx, i, *arg_regs);
|
754
|
-
}
|
755
|
-
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
756
|
-
for inst in call_site.gen_arg(self.lower_ctx, i, *arg_regs) {
|
757
|
-
self.lower_ctx.emit(inst);
|
758
|
-
}
|
759
|
-
}
|
760
|
-
}
|
761
|
-
|
762
|
-
fn gen_call_common(
|
763
|
-
&mut self,
|
764
|
-
abi: Sig,
|
765
|
-
num_rets: usize,
|
766
|
-
mut caller: $abicaller,
|
767
|
-
args: ValueSlice,
|
768
|
-
) -> InstOutput {
|
769
|
-
caller.emit_stack_pre_adjust(self.lower_ctx);
|
770
|
-
|
771
|
-
self.gen_call_common_args(&mut caller, args);
|
772
|
-
|
773
|
-
// Handle retvals prior to emitting call, so the
|
774
|
-
// constraints are on the call instruction; but buffer the
|
775
|
-
// instructions till after the call.
|
776
|
-
let mut outputs = InstOutput::new();
|
777
|
-
let mut retval_insts: crate::machinst::abi::SmallInstVec<_> = smallvec::smallvec![];
|
778
|
-
// We take the *last* `num_rets` returns of the sig:
|
779
|
-
// this skips a StructReturn, if any, that is present.
|
780
|
-
let sigdata_num_rets = self.lower_ctx.sigs().num_rets(abi);
|
781
|
-
debug_assert!(num_rets <= sigdata_num_rets);
|
782
|
-
for i in (sigdata_num_rets - num_rets)..sigdata_num_rets {
|
783
|
-
// Borrow `sigdata` again so we don't hold a `self`
|
784
|
-
// borrow across the `&mut self` arg to
|
785
|
-
// `abi_arg_slot_regs()` below.
|
786
|
-
let ret = self.lower_ctx.sigs().get_ret(abi, i);
|
787
|
-
let retval_regs = self.abi_arg_slot_regs(&ret).unwrap();
|
788
|
-
retval_insts.extend(
|
789
|
-
caller
|
790
|
-
.gen_retval(self.lower_ctx, i, retval_regs.clone())
|
791
|
-
.into_iter(),
|
792
|
-
);
|
793
|
-
outputs.push(valueregs::non_writable_value_regs(retval_regs));
|
794
|
-
}
|
795
|
-
|
796
|
-
caller.emit_call(self.lower_ctx);
|
797
|
-
|
798
|
-
for inst in retval_insts {
|
799
|
-
self.lower_ctx.emit(inst);
|
800
|
-
}
|
801
|
-
|
802
|
-
caller.emit_stack_post_adjust(self.lower_ctx);
|
803
|
-
|
804
|
-
outputs
|
805
|
-
}
|
806
|
-
|
807
|
-
fn abi_arg_slot_regs(&mut self, arg: &ABIArg) -> Option<WritableValueRegs> {
|
808
|
-
match arg {
|
809
|
-
&ABIArg::Slots { ref slots, .. } => match slots.len() {
|
810
|
-
1 => {
|
811
|
-
let a = self.temp_writable_reg(slots[0].get_type());
|
812
|
-
Some(WritableValueRegs::one(a))
|
813
|
-
}
|
814
|
-
2 => {
|
815
|
-
let a = self.temp_writable_reg(slots[0].get_type());
|
816
|
-
let b = self.temp_writable_reg(slots[1].get_type());
|
817
|
-
Some(WritableValueRegs::two(a, b))
|
818
|
-
}
|
819
|
-
_ => panic!("Expected to see one or two slots only from {:?}", arg),
|
820
|
-
},
|
821
|
-
_ => None,
|
822
|
-
}
|
823
|
-
}
|
824
|
-
};
|
825
|
-
}
|
826
|
-
|
827
|
-
/// This structure is used to implement the ISLE-generated `Context` trait and
|
828
|
-
/// internally has a temporary reference to a machinst `LowerCtx`.
|
829
|
-
pub(crate) struct IsleContext<'a, 'b, I, B>
|
830
|
-
where
|
831
|
-
I: VCodeInst,
|
832
|
-
B: LowerBackend,
|
833
|
-
{
|
834
|
-
pub lower_ctx: &'a mut Lower<'b, I>,
|
835
|
-
pub backend: &'a B,
|
836
|
-
}
|