vhdl_help 0.4.2 → 0.4.3
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/lib/templates/bram.vhd +43 -0
- data/lib/templates/fifo.vhd +113 -0
- data/lib/templates/generic_ram.vhd +47 -0
- data/lib/vhdl_helper.rb +13 -3
- metadata +21 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA1:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 9b7534abca726794b91b9978d84d144100c4308b
|
4
|
+
data.tar.gz: 6b6b47b7f915da83204a27ef734a80fe92083ad9
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 4b33a7b116645cbc3e5bc6f4b60b17fddf08bde9b982515cd9077ba6c8a466d8a89282a0766e4a50d6b214be946c97634aea774b2a7c28b9335be8bbf23d7931
|
7
|
+
data.tar.gz: 5b5985a62b965ab06ef12aef4da47c5efebd76f818332ceb402a31ae9bd6a8d1a6fe6899efaad3e669b8f0f2e076b583c66ff6764e99a4edd6031866c2c0741f
|
@@ -0,0 +1,43 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.std_logic_1164.all;
|
3
|
+
use ieee.numeric_std.all;
|
4
|
+
|
5
|
+
entity bram is
|
6
|
+
generic(
|
7
|
+
data_width: integer:= 8;
|
8
|
+
address_width:integer := 8;
|
9
|
+
mem_depth: integer:= 256);
|
10
|
+
|
11
|
+
port (
|
12
|
+
clk : in std_logic;
|
13
|
+
we : in std_logic;
|
14
|
+
datain : in std_logic_vector(data_width-1 downto 0);
|
15
|
+
address : in unsigned(address_width-1 downto 0);
|
16
|
+
dataout: out std_logic_vector(data_width-1 downto 0));
|
17
|
+
end bram;
|
18
|
+
|
19
|
+
architecture rtl of bram is
|
20
|
+
|
21
|
+
type mem_type is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
|
22
|
+
signal mem: mem_type;
|
23
|
+
signal raddress : unsigned(address_width-1 downto 0);
|
24
|
+
|
25
|
+
begin
|
26
|
+
l0: process (clk, we, address)
|
27
|
+
begin
|
28
|
+
if (clk = '1' and clk'event) then
|
29
|
+
raddress <= address;
|
30
|
+
if (we = '1') then
|
31
|
+
mem(to_integer(raddress)) <= datain;
|
32
|
+
end if;
|
33
|
+
end if;
|
34
|
+
end process;
|
35
|
+
|
36
|
+
l1: process (clk, address)
|
37
|
+
begin
|
38
|
+
if (clk = '1' and clk'event) then
|
39
|
+
dataout <= mem(to_integer(address));
|
40
|
+
end if;
|
41
|
+
end process;
|
42
|
+
|
43
|
+
end rtl;
|
@@ -0,0 +1,113 @@
|
|
1
|
+
-- Pong Chu FIFO
|
2
|
+
|
3
|
+
library ieee;
|
4
|
+
use ieee.std_logic_1164.all;
|
5
|
+
use ieee.numeric_std.all;
|
6
|
+
|
7
|
+
entity fifo is
|
8
|
+
generic(
|
9
|
+
B : natural := 8; -- number of bits
|
10
|
+
W : natural := 4 -- number of address bits
|
11
|
+
);
|
12
|
+
port(
|
13
|
+
clk, reset : in std_logic;
|
14
|
+
rd, wr : in std_logic;
|
15
|
+
w_data : in std_logic_vector (B-1 downto 0);
|
16
|
+
empty, full : out std_logic;
|
17
|
+
r_data : out std_logic_vector (B-1 downto 0)
|
18
|
+
);
|
19
|
+
end fifo;
|
20
|
+
|
21
|
+
architecture arch of fifo is
|
22
|
+
|
23
|
+
type reg_file_type is array (2**W-1 downto 0) of std_logic_vector(B-1 downto 0);
|
24
|
+
signal array_reg : reg_file_type;
|
25
|
+
signal w_ptr_reg, w_ptr_next, w_ptr_succ : std_logic_vector(W-1 downto 0);
|
26
|
+
signal r_ptr_reg, r_ptr_next, r_ptr_succ : std_logic_vector(W-1 downto 0);
|
27
|
+
signal full_reg, empty_reg, full_next, empty_next : std_logic;
|
28
|
+
signal wr_op : std_logic_vector(1 downto 0);
|
29
|
+
signal wr_en : std_logic;
|
30
|
+
|
31
|
+
begin
|
32
|
+
|
33
|
+
--=================================================
|
34
|
+
-- register file
|
35
|
+
--=================================================
|
36
|
+
process(clk, reset)
|
37
|
+
begin
|
38
|
+
if (reset = '1') then
|
39
|
+
array_reg <= (others => (others => '0'));
|
40
|
+
elsif (clk'event and clk = '1') then
|
41
|
+
if wr_en = '1' then
|
42
|
+
array_reg(to_integer(unsigned(w_ptr_reg)))
|
43
|
+
<= w_data;
|
44
|
+
end if;
|
45
|
+
end if;
|
46
|
+
end process;
|
47
|
+
|
48
|
+
-- read port
|
49
|
+
r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
|
50
|
+
-- write enabled only when FIFO is not full
|
51
|
+
wr_en <= wr and (not full_reg);
|
52
|
+
|
53
|
+
--=================================================
|
54
|
+
-- fifo control logic
|
55
|
+
--=================================================
|
56
|
+
-- register for read and write pointers
|
57
|
+
process(clk, reset)
|
58
|
+
begin
|
59
|
+
if (reset = '1') then
|
60
|
+
w_ptr_reg <= (others => '0');
|
61
|
+
r_ptr_reg <= (others => '0');
|
62
|
+
full_reg <= '0';
|
63
|
+
empty_reg <= '1';
|
64
|
+
elsif (clk'event and clk = '1') then
|
65
|
+
w_ptr_reg <= w_ptr_next;
|
66
|
+
r_ptr_reg <= r_ptr_next;
|
67
|
+
full_reg <= full_next;
|
68
|
+
empty_reg <= empty_next;
|
69
|
+
end if;
|
70
|
+
end process;
|
71
|
+
|
72
|
+
-- successive pointer values
|
73
|
+
w_ptr_succ <= std_logic_vector(unsigned(w_ptr_reg)+1);
|
74
|
+
r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);
|
75
|
+
|
76
|
+
-- next-state logic for read and write pointers
|
77
|
+
wr_op <= wr & rd;
|
78
|
+
process(w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op,
|
79
|
+
empty_reg, full_reg)
|
80
|
+
begin
|
81
|
+
w_ptr_next <= w_ptr_reg;
|
82
|
+
r_ptr_next <= r_ptr_reg;
|
83
|
+
full_next <= full_reg;
|
84
|
+
empty_next <= empty_reg;
|
85
|
+
case wr_op is
|
86
|
+
when "00" => -- no op
|
87
|
+
when "01" => -- read
|
88
|
+
if (empty_reg /= '1') then -- not empty
|
89
|
+
r_ptr_next <= r_ptr_succ;
|
90
|
+
full_next <= '0';
|
91
|
+
if (r_ptr_succ = w_ptr_reg) then
|
92
|
+
empty_next <= '1';
|
93
|
+
end if;
|
94
|
+
end if;
|
95
|
+
when "10" => -- write
|
96
|
+
if (full_reg /= '1') then -- not full
|
97
|
+
w_ptr_next <= w_ptr_succ;
|
98
|
+
empty_next <= '0';
|
99
|
+
if (w_ptr_succ = r_ptr_reg) then
|
100
|
+
full_next <= '1';
|
101
|
+
end if;
|
102
|
+
end if;
|
103
|
+
when others => -- write/read;
|
104
|
+
w_ptr_next <= w_ptr_succ;
|
105
|
+
r_ptr_next <= r_ptr_succ;
|
106
|
+
end case;
|
107
|
+
end process;
|
108
|
+
|
109
|
+
-- output
|
110
|
+
full <= full_reg;
|
111
|
+
empty <= empty_reg;
|
112
|
+
|
113
|
+
end arch;
|
@@ -0,0 +1,47 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.std_logic_1164.all;
|
3
|
+
use ieee.numeric_std.all;
|
4
|
+
|
5
|
+
-- Warning : prefer bram to correctly infer BLOCK RAMS !
|
6
|
+
|
7
|
+
entity ram is
|
8
|
+
generic(
|
9
|
+
nbits_address : natural :=8;
|
10
|
+
nbits_data : natural :=32
|
11
|
+
);
|
12
|
+
port(
|
13
|
+
reset_n : in std_logic;
|
14
|
+
clk : in std_logic;
|
15
|
+
wr : in std_logic;
|
16
|
+
address : in unsigned(nbits_address-1 downto 0);
|
17
|
+
datain : in std_logic_vector(nbits_data-1 downto 0);
|
18
|
+
dataout : out std_logic_vector(nbits_data-1 downto 0)
|
19
|
+
);
|
20
|
+
end entity;
|
21
|
+
|
22
|
+
architecture rtl of ram is
|
23
|
+
|
24
|
+
type memory_type is array(0 to 2**nbits_address-1) of std_logic_vector(nbits_data-1 downto 0);
|
25
|
+
signal mem : memory_type;
|
26
|
+
signal addr_r : unsigned(nbits_address-1 downto 0);
|
27
|
+
|
28
|
+
begin
|
29
|
+
|
30
|
+
write_p : process(reset_n, clk)
|
31
|
+
begin
|
32
|
+
if reset_n = '0' then
|
33
|
+
for i in 0 to 2**nbits_address-1 loop
|
34
|
+
mem(i) <= (others => '0');
|
35
|
+
end loop;
|
36
|
+
addr_r <= to_unsigned(0, 8);
|
37
|
+
elsif rising_edge(clk) then
|
38
|
+
if wr = '1' then
|
39
|
+
mem(to_integer(address)) <= datain;
|
40
|
+
end if;
|
41
|
+
addr_r <= address;
|
42
|
+
end if;
|
43
|
+
end process;
|
44
|
+
|
45
|
+
dataout <= mem(to_integer(addr_r));
|
46
|
+
|
47
|
+
end rtl;
|
data/lib/vhdl_helper.rb
CHANGED
@@ -2,10 +2,11 @@ require 'erb'
|
|
2
2
|
require 'pp'
|
3
3
|
# compiler options
|
4
4
|
require 'optparse'
|
5
|
+
require 'similar_text'
|
5
6
|
|
6
7
|
class VhdlHelper
|
7
8
|
|
8
|
-
VERSION = "0.4.
|
9
|
+
VERSION = "0.4.3"
|
9
10
|
|
10
11
|
def initialize
|
11
12
|
puts "-- "+"="*60
|
@@ -90,8 +91,12 @@ class VhdlHelper
|
|
90
91
|
end
|
91
92
|
|
92
93
|
def generate what
|
93
|
-
|
94
|
-
|
94
|
+
concept_h=find_closer(what)
|
95
|
+
concept=concept_h.sort_by{|k,v| v}.reverse.first
|
96
|
+
concept,value=concept
|
97
|
+
# puts "closer concept : #{concept}"
|
98
|
+
filename=__dir__+"/templates/#{concept}.vhd"
|
99
|
+
unless value > 50.0
|
95
100
|
puts "Sorry...I cannot help you concerning '#{what}'"
|
96
101
|
else
|
97
102
|
template=IO.read(filename)
|
@@ -101,6 +106,11 @@ class VhdlHelper
|
|
101
106
|
end
|
102
107
|
end
|
103
108
|
|
109
|
+
def find_closer word
|
110
|
+
files=Dir[__dir__+"/templates/*.vhd"].collect{|f| File.basename(f,'.vhd')}
|
111
|
+
concept_h=files.inject({}){|h,name| h[name]=name.similar(word);h}
|
112
|
+
end
|
113
|
+
|
104
114
|
end
|
105
115
|
|
106
116
|
if $PROGRAM_NAME == __FILE__
|
metadata
CHANGED
@@ -1,16 +1,30 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: vhdl_help
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.4.
|
4
|
+
version: 0.4.3
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Jean-Christophe Le Lann
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2018-
|
12
|
-
dependencies:
|
13
|
-
|
11
|
+
date: 2018-09-11 00:00:00.000000000 Z
|
12
|
+
dependencies:
|
13
|
+
- !ruby/object:Gem::Dependency
|
14
|
+
name: similar_text
|
15
|
+
requirement: !ruby/object:Gem::Requirement
|
16
|
+
requirements:
|
17
|
+
- - "~>"
|
18
|
+
- !ruby/object:Gem::Version
|
19
|
+
version: '0'
|
20
|
+
type: :runtime
|
21
|
+
prerelease: false
|
22
|
+
version_requirements: !ruby/object:Gem::Requirement
|
23
|
+
requirements:
|
24
|
+
- - "~>"
|
25
|
+
- !ruby/object:Gem::Version
|
26
|
+
version: '0'
|
27
|
+
description: A simple snippets generator for VHDL on linux command line
|
14
28
|
email: jean-christophe.le_lann@ensta-bretagne.fr
|
15
29
|
executables:
|
16
30
|
- vhdl_help
|
@@ -18,13 +32,16 @@ extensions: []
|
|
18
32
|
extra_rdoc_files: []
|
19
33
|
files:
|
20
34
|
- bin/vhdl_help
|
35
|
+
- lib/templates/bram.vhd
|
21
36
|
- lib/templates/clock.vhd
|
22
37
|
- lib/templates/conversions.vhd
|
23
38
|
- lib/templates/counter.vhd
|
24
39
|
- lib/templates/entity.vhd
|
40
|
+
- lib/templates/fifo.vhd
|
25
41
|
- lib/templates/file_read.vhd
|
26
42
|
- lib/templates/file_write.vhd
|
27
43
|
- lib/templates/fsm.vhd
|
44
|
+
- lib/templates/generic_ram.vhd
|
28
45
|
- lib/templates/header.vhd
|
29
46
|
- lib/templates/memory.vhd
|
30
47
|
- lib/templates/procedure.vhd
|