vhdl_help 0.4.2 → 0.4.3

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 857ffe4c3fd8be5eed3fe3319514e61e8d933466
-  data.tar.gz: 7a344f4ed091dcfd84cf872c1af1685019e9d75f
+  metadata.gz: 9b7534abca726794b91b9978d84d144100c4308b
+  data.tar.gz: 6b6b47b7f915da83204a27ef734a80fe92083ad9
 SHA512:
-  metadata.gz: b2ce45e4c740368df4df2ae852bdf20d2f1111fab7bcc0dc38942dd8e775fbea616172a5c598061be86d608870f0fd3f8dc5cea4c4b7ebc91f0a72989fb64d99
-  data.tar.gz: e0db31838aff28f73d364f356a3e73489ee73a157d1fe7a4f17dd3efcfe2b42e3229c0218e967f93ba11b6a35be14ece46e1e601fe5fa87764df50edc95b19c9
+  metadata.gz: 4b33a7b116645cbc3e5bc6f4b60b17fddf08bde9b982515cd9077ba6c8a466d8a89282a0766e4a50d6b214be946c97634aea774b2a7c28b9335be8bbf23d7931
+  data.tar.gz: 5b5985a62b965ab06ef12aef4da47c5efebd76f818332ceb402a31ae9bd6a8d1a6fe6899efaad3e669b8f0f2e076b583c66ff6764e99a4edd6031866c2c0741f

data/lib/templates/bram.vhd

@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bram is
+generic(
+  data_width: integer:= 8;
+  address_width:integer := 8;
+  mem_depth: integer:= 256);
+
+port (
+  clk     : in std_logic;
+  we      : in std_logic;
+  datain  : in std_logic_vector(data_width-1 downto 0);
+  address : in unsigned(address_width-1 downto 0);
+  dataout: out std_logic_vector(data_width-1 downto 0));
+end bram;
+
+architecture rtl of bram is
+
+type mem_type is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
+signal mem: mem_type;
+signal raddress : unsigned(address_width-1 downto 0);
+
+begin
+l0: process (clk, we, address)
+  begin
+    if (clk = '1' and clk'event) then
+      raddress <= address;
+      if (we = '1') then
+        mem(to_integer(raddress)) <= datain;
+      end if;
+    end if;
+  end process;
+
+l1: process (clk, address)
+  begin
+    if (clk = '1' and clk'event) then
+      dataout <= mem(to_integer(address));
+    end if;
+  end process;
+
+end rtl;

data/lib/templates/fifo.vhd

@@ -0,0 +1,113 @@
+-- Pong Chu FIFO
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fifo is
+  generic(
+    B : natural := 8;                   -- number of bits
+    W : natural := 4                    -- number of address bits
+    );
+  port(
+    clk, reset  : in  std_logic;
+    rd, wr      : in  std_logic;
+    w_data      : in  std_logic_vector (B-1 downto 0);
+    empty, full : out std_logic;
+    r_data      : out std_logic_vector (B-1 downto 0)
+    );
+end fifo;
+
+architecture arch of fifo is
+
+  type reg_file_type is array (2**W-1 downto 0) of std_logic_vector(B-1 downto 0);
+  signal array_reg                                  : reg_file_type;
+  signal w_ptr_reg, w_ptr_next, w_ptr_succ          : std_logic_vector(W-1 downto 0);
+  signal r_ptr_reg, r_ptr_next, r_ptr_succ          : std_logic_vector(W-1 downto 0);
+  signal full_reg, empty_reg, full_next, empty_next : std_logic;
+  signal wr_op                                      : std_logic_vector(1 downto 0);
+  signal wr_en                                      : std_logic;
+
+begin
+
+  --=================================================
+  -- register file
+  --=================================================
+  process(clk, reset)
+  begin
+    if (reset = '1') then
+      array_reg <= (others => (others => '0'));
+    elsif (clk'event and clk = '1') then
+      if wr_en = '1' then
+        array_reg(to_integer(unsigned(w_ptr_reg)))
+          <= w_data;
+      end if;
+    end if;
+  end process;
+
+  -- read port
+  r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
+  -- write enabled only when FIFO is not full
+  wr_en  <= wr and (not full_reg);
+
+  --=================================================
+  -- fifo control logic
+  --=================================================
+  -- register for read and write pointers
+  process(clk, reset)
+  begin
+    if (reset = '1') then
+      w_ptr_reg <= (others => '0');
+      r_ptr_reg <= (others => '0');
+      full_reg  <= '0';
+      empty_reg <= '1';
+    elsif (clk'event and clk = '1') then
+      w_ptr_reg <= w_ptr_next;
+      r_ptr_reg <= r_ptr_next;
+      full_reg  <= full_next;
+      empty_reg <= empty_next;
+    end if;
+  end process;
+
+  -- successive pointer values
+  w_ptr_succ <= std_logic_vector(unsigned(w_ptr_reg)+1);
+  r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);
+
+  -- next-state logic for read and write pointers
+  wr_op <= wr & rd;
+  process(w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op,
+          empty_reg, full_reg)
+  begin
+    w_ptr_next <= w_ptr_reg;
+    r_ptr_next <= r_ptr_reg;
+    full_next  <= full_reg;
+    empty_next <= empty_reg;
+    case wr_op is
+      when "00" =>                      -- no op
+      when "01" =>                      -- read
+        if (empty_reg /= '1') then      -- not empty
+          r_ptr_next <= r_ptr_succ;
+          full_next  <= '0';
+          if (r_ptr_succ = w_ptr_reg) then
+            empty_next <= '1';
+          end if;
+        end if;
+      when "10" =>                      -- write
+        if (full_reg /= '1') then       -- not full
+          w_ptr_next <= w_ptr_succ;
+          empty_next <= '0';
+          if (w_ptr_succ = r_ptr_reg) then
+            full_next <= '1';
+          end if;
+        end if;
+      when others =>                    -- write/read;
+        w_ptr_next <= w_ptr_succ;
+        r_ptr_next <= r_ptr_succ;
+    end case;
+  end process;
+
+  -- output
+  full  <= full_reg;
+  empty <= empty_reg;
+
+end arch;

data/lib/templates/generic_ram.vhd

@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Warning : prefer bram to correctly infer BLOCK RAMS !
+
+entity ram is
+  generic(
+    nbits_address : natural :=8;
+    nbits_data    : natural :=32
+  );
+  port(
+    reset_n : in  std_logic;
+    clk     : in  std_logic;
+    wr      : in  std_logic;
+    address : in  unsigned(nbits_address-1 downto 0);
+    datain  : in  std_logic_vector(nbits_data-1 downto 0);
+    dataout : out std_logic_vector(nbits_data-1 downto 0)
+    );
+end entity;
+
+architecture rtl of ram is
+
+  type memory_type is array(0 to 2**nbits_address-1) of std_logic_vector(nbits_data-1 downto 0);
+  signal mem    : memory_type;
+  signal addr_r : unsigned(nbits_address-1 downto 0);
+  
+begin
+
+  write_p : process(reset_n, clk)
+  begin
+    if reset_n = '0' then
+      for i in 0 to 2**nbits_address-1 loop
+        mem(i) <= (others => '0');
+      end loop;
+      addr_r <= to_unsigned(0, 8);
+    elsif rising_edge(clk) then
+      if wr = '1' then
+        mem(to_integer(address)) <= datain;
+      end if;
+      addr_r <= address;
+    end if;
+  end process;
+
+  dataout <= mem(to_integer(addr_r));
+
+end rtl;

data/lib/vhdl_helper.rb

@@ -2,10 +2,11 @@ require 'erb'
 require 'pp'
 # compiler options
 require 'optparse'
+require 'similar_text'
 
 class VhdlHelper
 
-  VERSION = "0.4.2"
+  VERSION = "0.4.3"
 
   def initialize
     puts "-- "+"="*60
@@ -90,8 +91,12 @@ class VhdlHelper
   end
 
   def generate what
-    filename=__dir__+"/templates/#{what}.vhd"
-    unless File.exist? filename
+    concept_h=find_closer(what)
+    concept=concept_h.sort_by{|k,v| v}.reverse.first
+    concept,value=concept
+    # puts "closer concept : #{concept}"
+    filename=__dir__+"/templates/#{concept}.vhd"
+    unless value > 50.0
       puts "Sorry...I cannot help you concerning '#{what}'"
     else
       template=IO.read(filename)
@@ -101,6 +106,11 @@ class VhdlHelper
     end
   end
 
+  def find_closer word
+    files=Dir[__dir__+"/templates/*.vhd"].collect{|f| File.basename(f,'.vhd')}
+    concept_h=files.inject({}){|h,name| h[name]=name.similar(word);h}
+  end
+
 end
 
 if $PROGRAM_NAME == __FILE__

metadata

@@ -1,16 +1,30 @@
 --- !ruby/object:Gem::Specification
 name: vhdl_help
 version: !ruby/object:Gem::Version
-  version: 0.4.2
+  version: 0.4.3
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-06-01 00:00:00.000000000 Z
-dependencies: []
-description: A simple snippets generator for VHDL
+date: 2018-09-11 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: similar_text
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0'
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0'
+description: A simple snippets generator for VHDL on linux command line
 email: jean-christophe.le_lann@ensta-bretagne.fr
 executables:
 - vhdl_help
@@ -18,13 +32,16 @@ extensions: []
 extra_rdoc_files: []
 files:
 - bin/vhdl_help
+- lib/templates/bram.vhd
 - lib/templates/clock.vhd
 - lib/templates/conversions.vhd
 - lib/templates/counter.vhd
 - lib/templates/entity.vhd
+- lib/templates/fifo.vhd
 - lib/templates/file_read.vhd
 - lib/templates/file_write.vhd
 - lib/templates/fsm.vhd
+- lib/templates/generic_ram.vhd
 - lib/templates/header.vhd
 - lib/templates/memory.vhd
 - lib/templates/procedure.vhd