vhdl_help 0.4.2 → 0.4.3

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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@@ -0,0 +1,43 @@
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+ library ieee;
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+ use ieee.std_logic_1164.all;
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+ use ieee.numeric_std.all;
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+
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+ entity bram is
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+ generic(
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+ data_width: integer:= 8;
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+ address_width:integer := 8;
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+ mem_depth: integer:= 256);
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+
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+ port (
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+ clk : in std_logic;
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+ we : in std_logic;
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+ datain : in std_logic_vector(data_width-1 downto 0);
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+ address : in unsigned(address_width-1 downto 0);
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+ dataout: out std_logic_vector(data_width-1 downto 0));
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+ end bram;
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+
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+ architecture rtl of bram is
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+
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+ type mem_type is array (mem_depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
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+ signal mem: mem_type;
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+ signal raddress : unsigned(address_width-1 downto 0);
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+
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+ begin
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+ l0: process (clk, we, address)
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+ begin
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+ if (clk = '1' and clk'event) then
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+ raddress <= address;
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+ if (we = '1') then
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+ mem(to_integer(raddress)) <= datain;
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+ end if;
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+ end if;
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+ end process;
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+
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+ l1: process (clk, address)
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+ begin
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+ if (clk = '1' and clk'event) then
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+ dataout <= mem(to_integer(address));
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+ end if;
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+ end process;
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+
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+ end rtl;
@@ -0,0 +1,113 @@
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+ -- Pong Chu FIFO
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+
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+ library ieee;
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+ use ieee.std_logic_1164.all;
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+ use ieee.numeric_std.all;
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+
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+ entity fifo is
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+ generic(
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+ B : natural := 8; -- number of bits
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+ W : natural := 4 -- number of address bits
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+ );
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+ port(
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+ clk, reset : in std_logic;
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+ rd, wr : in std_logic;
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+ w_data : in std_logic_vector (B-1 downto 0);
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+ empty, full : out std_logic;
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+ r_data : out std_logic_vector (B-1 downto 0)
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+ );
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+ end fifo;
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+
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+ architecture arch of fifo is
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+
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+ type reg_file_type is array (2**W-1 downto 0) of std_logic_vector(B-1 downto 0);
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+ signal array_reg : reg_file_type;
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+ signal w_ptr_reg, w_ptr_next, w_ptr_succ : std_logic_vector(W-1 downto 0);
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+ signal r_ptr_reg, r_ptr_next, r_ptr_succ : std_logic_vector(W-1 downto 0);
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+ signal full_reg, empty_reg, full_next, empty_next : std_logic;
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+ signal wr_op : std_logic_vector(1 downto 0);
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+ signal wr_en : std_logic;
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+
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+ begin
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+
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+ --=================================================
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+ -- register file
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+ --=================================================
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+ process(clk, reset)
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+ begin
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+ if (reset = '1') then
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+ array_reg <= (others => (others => '0'));
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+ elsif (clk'event and clk = '1') then
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+ if wr_en = '1' then
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+ array_reg(to_integer(unsigned(w_ptr_reg)))
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+ <= w_data;
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+ end if;
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+ end if;
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+ end process;
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+
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+ -- read port
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+ r_data <= array_reg(to_integer(unsigned(r_ptr_reg)));
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+ -- write enabled only when FIFO is not full
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+ wr_en <= wr and (not full_reg);
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+
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+ --=================================================
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+ -- fifo control logic
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+ --=================================================
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+ -- register for read and write pointers
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+ process(clk, reset)
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+ begin
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+ if (reset = '1') then
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+ w_ptr_reg <= (others => '0');
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+ r_ptr_reg <= (others => '0');
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+ full_reg <= '0';
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+ empty_reg <= '1';
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+ elsif (clk'event and clk = '1') then
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+ w_ptr_reg <= w_ptr_next;
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+ r_ptr_reg <= r_ptr_next;
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+ full_reg <= full_next;
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+ empty_reg <= empty_next;
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+ end if;
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+ end process;
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+
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+ -- successive pointer values
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+ w_ptr_succ <= std_logic_vector(unsigned(w_ptr_reg)+1);
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+ r_ptr_succ <= std_logic_vector(unsigned(r_ptr_reg)+1);
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+
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+ -- next-state logic for read and write pointers
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+ wr_op <= wr & rd;
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+ process(w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op,
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+ empty_reg, full_reg)
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+ begin
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+ w_ptr_next <= w_ptr_reg;
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+ r_ptr_next <= r_ptr_reg;
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+ full_next <= full_reg;
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+ empty_next <= empty_reg;
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+ case wr_op is
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+ when "00" => -- no op
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+ when "01" => -- read
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+ if (empty_reg /= '1') then -- not empty
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+ r_ptr_next <= r_ptr_succ;
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+ full_next <= '0';
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+ if (r_ptr_succ = w_ptr_reg) then
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+ empty_next <= '1';
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+ end if;
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+ end if;
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+ when "10" => -- write
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+ if (full_reg /= '1') then -- not full
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+ w_ptr_next <= w_ptr_succ;
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+ empty_next <= '0';
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+ if (w_ptr_succ = r_ptr_reg) then
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+ full_next <= '1';
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+ end if;
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+ end if;
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+ when others => -- write/read;
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+ w_ptr_next <= w_ptr_succ;
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+ r_ptr_next <= r_ptr_succ;
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+ end case;
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+ end process;
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+
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+ -- output
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+ full <= full_reg;
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+ empty <= empty_reg;
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+
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+ end arch;
@@ -0,0 +1,47 @@
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+ library ieee;
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+ use ieee.std_logic_1164.all;
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+ use ieee.numeric_std.all;
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+
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+ -- Warning : prefer bram to correctly infer BLOCK RAMS !
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+
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+ entity ram is
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+ generic(
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+ nbits_address : natural :=8;
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+ nbits_data : natural :=32
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+ );
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+ port(
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+ reset_n : in std_logic;
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+ clk : in std_logic;
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+ wr : in std_logic;
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+ address : in unsigned(nbits_address-1 downto 0);
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+ datain : in std_logic_vector(nbits_data-1 downto 0);
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+ dataout : out std_logic_vector(nbits_data-1 downto 0)
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+ );
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+ end entity;
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+
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+ architecture rtl of ram is
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+
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+ type memory_type is array(0 to 2**nbits_address-1) of std_logic_vector(nbits_data-1 downto 0);
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+ signal mem : memory_type;
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+ signal addr_r : unsigned(nbits_address-1 downto 0);
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+
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+ begin
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+
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+ write_p : process(reset_n, clk)
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+ begin
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+ if reset_n = '0' then
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+ for i in 0 to 2**nbits_address-1 loop
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+ mem(i) <= (others => '0');
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+ end loop;
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+ addr_r <= to_unsigned(0, 8);
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+ elsif rising_edge(clk) then
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+ if wr = '1' then
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+ mem(to_integer(address)) <= datain;
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+ end if;
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+ addr_r <= address;
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+ end if;
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+ end process;
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+
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+ dataout <= mem(to_integer(addr_r));
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+
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+ end rtl;
data/lib/vhdl_helper.rb CHANGED
@@ -2,10 +2,11 @@ require 'erb'
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  require 'pp'
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  # compiler options
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  require 'optparse'
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+ require 'similar_text'
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  class VhdlHelper
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- VERSION = "0.4.2"
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+ VERSION = "0.4.3"
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  def initialize
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  puts "-- "+"="*60
@@ -90,8 +91,12 @@ class VhdlHelper
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  end
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  def generate what
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- filename=__dir__+"/templates/#{what}.vhd"
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- unless File.exist? filename
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+ concept_h=find_closer(what)
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+ concept=concept_h.sort_by{|k,v| v}.reverse.first
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+ concept,value=concept
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+ # puts "closer concept : #{concept}"
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+ filename=__dir__+"/templates/#{concept}.vhd"
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+ unless value > 50.0
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  puts "Sorry...I cannot help you concerning '#{what}'"
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  else
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  template=IO.read(filename)
@@ -101,6 +106,11 @@ class VhdlHelper
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  end
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  end
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+ def find_closer word
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+ files=Dir[__dir__+"/templates/*.vhd"].collect{|f| File.basename(f,'.vhd')}
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+ concept_h=files.inject({}){|h,name| h[name]=name.similar(word);h}
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+ end
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+
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  end
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  if $PROGRAM_NAME == __FILE__
metadata CHANGED
@@ -1,16 +1,30 @@
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  --- !ruby/object:Gem::Specification
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  name: vhdl_help
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  version: !ruby/object:Gem::Version
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- version: 0.4.2
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+ version: 0.4.3
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  platform: ruby
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  authors:
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  - Jean-Christophe Le Lann
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2018-06-01 00:00:00.000000000 Z
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- dependencies: []
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- description: A simple snippets generator for VHDL
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+ date: 2018-09-11 00:00:00.000000000 Z
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+ dependencies:
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+ - !ruby/object:Gem::Dependency
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+ name: similar_text
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+ requirement: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - "~>"
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+ - !ruby/object:Gem::Version
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+ version: '0'
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+ type: :runtime
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+ prerelease: false
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+ version_requirements: !ruby/object:Gem::Requirement
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+ requirements:
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+ - - "~>"
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+ - !ruby/object:Gem::Version
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+ version: '0'
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+ description: A simple snippets generator for VHDL on linux command line
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  email: jean-christophe.le_lann@ensta-bretagne.fr
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  executables:
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  - vhdl_help
@@ -18,13 +32,16 @@ extensions: []
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  extra_rdoc_files: []
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  files:
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  - bin/vhdl_help
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+ - lib/templates/bram.vhd
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  - lib/templates/clock.vhd
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  - lib/templates/conversions.vhd
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  - lib/templates/counter.vhd
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  - lib/templates/entity.vhd
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+ - lib/templates/fifo.vhd
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  - lib/templates/file_read.vhd
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  - lib/templates/file_write.vhd
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  - lib/templates/fsm.vhd
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+ - lib/templates/generic_ram.vhd
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  - lib/templates/header.vhd
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  - lib/templates/memory.vhd
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  - lib/templates/procedure.vhd