verilog_rename 0.0.1

data/spec/scratch/fixtures/TEST_ONE.v

@@ -0,0 +1,6 @@
+module TEST_ONE(
+  input rx,
+  output tx
+);
+
+endmodule

data/spec/scratch/fixtures/test_four.vh

@@ -0,0 +1,3 @@
+
+`include 'TEST_ONE.v'
+`include 'test_three.v'

data/spec/scratch/fixtures/test_three.v

@@ -0,0 +1,18 @@
+module TEST_THREE(
+  input rx,
+  output tx
+);
+
+
+TEST_ONE test_one_i0(
+  .rx  (rx),
+  .tx  (tx)
+);
+
+TEST_ONE test_two_i0;
+
+TEST_FOUR test_four_i0();
+
+TEST_FIVE test_five_i0 ();
+
+endmodule

data/spec/spec_helper.rb

@@ -0,0 +1,5 @@
+$LOAD_PATH.unshift File.join(File.dirname(__FILE__), '..', 'lib')
+
+require 'rspec'
+require 'verilog'
+require 'verilog_rename'

data/spec/temp/BETA_R4.v

@@ -0,0 +1,5 @@
+module BETA_R4 ( input x,
+input y 
+);
+
+endmodule

data/spec/temp/BETA_R4_TH.v

@@ -0,0 +1,360 @@
+// -------------------------------------------------------------
+//
+// Module: ISRC_ARIZONA_TH
+// Simulink Path: ..\..\..\VerilogD\ISRC_ARIZONA_R3
+// Created: 2011-01-26 18:45:11
+// Generated by MATLAB 7.11 and Simulink HDL Coder 2.0
+// Hierarchy Level: 1
+//
+//
+// -------------------------------------------------------------
+`timescale 1 ns / 1 ns 
+
+module BETA_R4_TH; 
+
+  `include "BETA_R4_TH_pkg.v"
+  `include "BETA_R4_TH_data.v"
+
+  parameter CLKRATE = 12; //uint32
+  parameter LATENCY = 12; //uint32
+  parameter INITIAL_LATENCY = 0; //uint32
+  parameter NO_OF_TESTS = 1667; //uint32
+  parameter MAX_TIMEOUT = 145; //uint32
+  parameter MAX_ERROR_COUNT = 5001; //uint32
+
+
+  // Signals
+  reg   clk; // boolean
+  reg   rst_an; // boolean
+  reg  clk_enable; // boolean
+  reg  signed [23:0] din; // sfix24_En20
+  reg  notch_ena; // boolean
+  wire  ce_out; // boolean
+  wire signed [23:0] dout; // sfix24_En20
+
+  integer txdataCnt; // uint32
+  integer rxdataCnt; // uint32
+  reg  tb_enb; // boolean
+  wire srcDone; // boolean
+  wire snkDone; // boolean
+  wire testFailure; // boolean
+  reg  tbenb_dly; // boolean
+  reg  [3:0] counter; // ufix4
+  wire phase_2; // boolean
+  wire phase_1; // boolean
+  wire rdEnb_phase_1; // boolean
+  wire rdEnb_phase_2; // boolean
+  wire Data_Type_Conversion2_out1_rdenb; // boolean
+  reg  [10:0] Data_Type_Conversion2_out1_addr; // ufix11
+  reg  Data_Type_Conversion2_out1_done; // boolean
+  reg  signed [23:0] holdData_din; // sfix24_En20
+  wire Data_Type_Conversion_notch_ena_out1_rdenb; // boolean
+  reg  [13:0] Data_Type_Conversion_notch_ena_out1_addr; // ufix14
+  reg  Data_Type_Conversion_notch_ena_out1_done; // boolean
+  reg  holdData_notch_ena; // boolean
+  reg  dout_testFailure; // boolean
+  integer dout_timeout; // uint32
+  integer dout_errCnt; // uint32
+  wire dout_rdenb; // boolean
+  reg  [12:0] dout_addr; // ufix13
+  reg  dout_done; // boolean
+  wire signed [23:0] dout_ref; // sfix24_En20
+  wire signed [23:0] dout_dataTable; // sfix24_En20
+  wire signed [23:0] dout_refTmp; // sfix24_En20
+  reg  signed [23:0] regout; // sfix24_En20
+  reg  check1_Done; // boolean
+
+  // Module Instances
+  BETA_R4 u_BETA
+    (
+    .clk(clk),
+    .rst_an(rst_an),
+    .clk_enable(clk_enable),
+    .din(din),
+    .notch_ena(notch_ena),
+    .ce_out(ce_out),
+    .dout(dout)
+    );
+
+
+  // Block Statements
+  // -------------------------------------------------------------
+  // Driving the test bench enable
+  // -------------------------------------------------------------
+
+  always @(rst_an, snkDone)
+  begin
+    if (rst_an == 1'b0)
+      tb_enb <= 1'b0;
+    else if (snkDone == 1'b0 )
+      tb_enb <= 1'b1;
+    else begin
+    # (clk_period * 2);
+      tb_enb <= 1'b0;
+    end
+  end
+
+  always @(posedge clk or negedge rst_an) //tb_enb_gen
+  begin
+    if (~rst_an) begin 
+       // Nothing to reset.
+    end 
+    else begin 
+      if (snkDone == 1) begin
+        if (testFailure == 0 ) 
+              $display("**************TEST COMPLETED (PASSED)**************");
+        else
+              $display("**************TEST COMPLETED (FAILED)**************");
+      end
+    end
+  end //tb_enb_gen;
+
+  // -------------------------------------------------------------
+  // System Clock (fast clock) and reset
+  // -------------------------------------------------------------
+
+  always  // clock generation
+  begin // clk_gen
+    clk <= 1'b0;
+    # clk_low;
+    clk <= 1'b1;
+    # clk_high;
+    if (snkDone == 1) begin
+      clk <= 1'b0;
+      # clk_low;
+      clk <= 1'b1;
+      # clk_high;
+      $stop;
+    end
+  end  // clk_gen
+
+  initial  // reset block
+  begin // rst_an_gen
+    rst_an <= 1'b0;
+    # (clk_period * 2);
+    @ (posedge clk);
+    # (clk_hold);
+    rst_an <= 1'b1;
+  end  // rst_an_gen
+
+  // -------------------------------------------------------------
+  // Global clock enable
+  // -------------------------------------------------------------
+
+
+  always @ (posedge clk or negedge rst_an)
+    begin: tb_enb_delay
+      if (rst_an == 1'b0) begin
+        tbenb_dly <= 1'b0;
+      end
+      else begin
+        if (tb_enb == 1'b1) begin
+          tbenb_dly <= tb_enb;
+        end
+      end
+    end // tb_enb_delay
+
+  always @(snkDone, tbenb_dly)
+  begin
+    # clk_hold;
+    if (snkDone == 0)
+      clk_enable <= tbenb_dly;
+    else
+      clk_enable <= 0;
+  end
+
+  // -------------------------------------------------------------
+  // Slow Clock (clkenb)
+  // -------------------------------------------------------------
+
+  always @ (posedge clk or negedge rst_an)
+    begin: slow_clock_enable
+      if (rst_an == 1'b0) begin
+        counter <= 4'b0001;
+      end
+      else begin
+        if (tbenb_dly == 1'b1) begin
+          if (counter == 4'b1011) begin
+            counter <= 4'b0000;
+          end
+          else begin
+            counter <= counter + 1;
+          end
+        end
+      end
+    end // slow_clock_enable
+
+  assign  phase_2 = (((counter == 4'b0001)  ||
+                      (counter == 4'b0011)  ||
+                      (counter == 4'b0101)  ||
+                      (counter == 4'b0111)  ||
+                      (counter == 4'b1001)  ||
+                      (counter == 4'b1011)) && tbenb_dly == 1'b1)? 1 : 0;
+
+  assign  phase_1 = (counter == 4'b0001 && tbenb_dly == 1'b1)? 1 : 0;
+
+      assign rdEnb_phase_1 = phase_1;
+
+      assign rdEnb_phase_2 = phase_2;
+
+  // -------------------------------------------------------------
+  // Read the data and transmit it to the DUT
+  // -------------------------------------------------------------
+
+  always @(posedge clk or negedge rst_an)
+  begin
+    Data_Type_Conversion2_out1_task(clk,rst_an,
+                                    Data_Type_Conversion2_out1_rdenb,Data_Type_Conversion2_out1_addr,
+                                    Data_Type_Conversion2_out1_done);
+  end
+
+  assign Data_Type_Conversion2_out1_rdenb = rdEnb_phase_1;
+
+  always @ (posedge Data_Type_Conversion2_out1_rdenb or negedge rst_an)
+  begin // stimuli_Data_Type_Conversion2_out1_din_reg
+    if (~rst_an) begin 
+      holdData_din <=  24'bx;
+    end
+    else begin
+      holdData_din <= Data_Type_Conversion2_out1_force[Data_Type_Conversion2_out1_addr];
+    end
+  end
+
+  always @ (Data_Type_Conversion2_out1_rdenb, Data_Type_Conversion2_out1_addr)
+  begin // stimuli_Data_Type_Conversion2_out1_din
+    if (Data_Type_Conversion2_out1_rdenb == 1) begin
+      din <= # clk_hold Data_Type_Conversion2_out1_force[Data_Type_Conversion2_out1_addr];
+    end
+    else begin 
+      din <= # clk_hold holdData_din;
+    end
+  end // stimuli_Data_Type_Conversion2_out1_din
+
+  // -------------------------------------------------------------
+  // Read the data and transmit it to the DUT
+  // -------------------------------------------------------------
+
+  always @(posedge clk or negedge rst_an)
+  begin
+    Data_Type_Conversion_notch_ena_out1_task(clk,rst_an,
+                                             Data_Type_Conversion_notch_ena_out1_rdenb,Data_Type_Conversion_notch_ena_out1_addr,
+                                             Data_Type_Conversion_notch_ena_out1_done);
+  end
+
+  assign Data_Type_Conversion_notch_ena_out1_rdenb = rdEnb_phase_2;
+
+  always @ (posedge clk or negedge rst_an)
+  begin // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena_reg
+    if (~rst_an) begin 
+      holdData_notch_ena <=  1'bx;
+    end
+    else begin
+      holdData_notch_ena <= Data_Type_Conversion_notch_ena_out1_force;
+    end
+  end
+
+  always @ (Data_Type_Conversion_notch_ena_out1_rdenb, Data_Type_Conversion_notch_ena_out1_addr)
+  begin // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena
+    if (Data_Type_Conversion_notch_ena_out1_rdenb == 1) begin
+      notch_ena <= # clk_hold Data_Type_Conversion_notch_ena_out1_force;
+    end
+    else begin 
+      notch_ena <= # clk_hold holdData_notch_ena;
+    end
+  end // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena
+
+  // -------------------------------------------------------------
+  // Create done signal for Input data
+  // -------------------------------------------------------------
+
+  assign srcDone = Data_Type_Conversion2_out1_done && Data_Type_Conversion_notch_ena_out1_done;
+
+  // -------------------------------------------------------------
+  //  Checker: Checking the data received from the DUT.
+  // -------------------------------------------------------------
+
+  always @(posedge clk or negedge rst_an)
+  begin
+    dout_task(clk,rst_an,
+              dout_rdenb,dout_addr,
+              dout_done);
+  end
+
+  assign dout_rdenb = ce_out;
+
+  assign # clk_hold dout_dataTable = dout_expected[dout_addr];
+// ---- Bypass Register ----
+  always @ (posedge clk or negedge rst_an)
+    begin: DataHoldRegister_temp_process10
+      if (rst_an == 1'b0) begin
+        regout <= 0;
+      end
+      else begin
+        if (ce_out == 1'b1) begin
+          regout <= dout_dataTable;
+        end
+      end
+    end // DataHoldRegister_temp_process10
+
+  assign dout_refTmp = (ce_out == 1'b1) ? dout_dataTable :
+                 regout;
+
+
+  assign dout_ref = dout_refTmp;
+
+
+
+  always @ (posedge clk or negedge rst_an) // checker_dout
+  begin
+    if (rst_an == 0) begin 
+      dout_timeout <= 0;
+      dout_testFailure <= 0;
+      dout_errCnt <= 0;
+    end 
+    else begin 
+      if (dout_rdenb == 1 ) begin 
+        dout_timeout <= 0;
+
+        if (dout !== dout_expected[dout_addr]) begin
+           dout_errCnt <= dout_errCnt + 1;
+           dout_testFailure <= 1;
+               $display("ERROR in dout at time %t : Expected '%h' Actual '%h'", 
+                    $time, dout_expected[dout_addr], dout);
+           if (dout_errCnt >= MAX_ERROR_COUNT) 
+             $display("Warning: Number of errors for dout have exceeded the maximum error limit");
+        end
+
+      end
+      else if (dout_timeout > MAX_TIMEOUT && dout_rdenb == 1 ) begin 
+        dout_errCnt <= dout_errCnt + 1;
+        dout_testFailure <= 1;
+        $display ("Error: Timeout - Data was not received for dout.");
+        $stop;
+      end
+      else if (dout_rdenb == 1) begin
+        dout_timeout <= dout_timeout + 1 ;
+      end
+    end
+  end // checker_dout
+
+  always @ (posedge clk or negedge rst_an) // checkDone_1
+  begin
+    if (rst_an == 0)
+      check1_Done <= 0;
+    else if ((check1_Done == 0) && (dout_done == 1) && (dout_rdenb == 1))
+      check1_Done <= 1;
+  end
+
+  // -------------------------------------------------------------
+  // Create done and test failure signal for output data
+  // -------------------------------------------------------------
+
+  assign snkDone = check1_Done;
+
+  assign testFailure = dout_testFailure;
+
+  // Assignment Statements
+
+
+
+endmodule  // ISRC_ARIZONA_TH

data/spec/temp/BETA_TH_sim.do

@@ -0,0 +1 @@
+vsub vcs -R -PP -l run.log +notimingchecks +libext+.v+.bh.v -y ./ BETA_TH.v $*

data/spec/verilog_rename_spec.rb

@@ -0,0 +1,30 @@
+require 'spec_helper'
+require 'fileutils'
+require 'pp'
+
+describe VerilogRename do
+
+  it "Open file" do
+    path = File.dirname( __FILE__ )
+
+    ## Git cant have empty folders, so create in test
+    FileUtils.mkdir_p( ::File.join( path, 'scratch') )
+
+    ## Clean Scratch Area
+    FileUtils.rm( Dir.glob( ::File.join( path, 'scratch', '*.*') ) )
+
+    ## Copy files from fixtures to scratch
+    FileUtils.cp_r( ::File.join( path, 'fixtures'), ::File.join( path, 'scratch' ) )
+
+
+    path_files = Verilog::PathFiles.new( File.join( path, 'scratch', 'fixtures') )
+    path_files.read_all
+
+    rename = Verilog::Rename.new('TEST_ONE', 'TEST_TWO', path_files)
+    rename.rename_module
+
+  end
+
+
+
+end

metadata

@@ -0,0 +1,110 @@
+--- !ruby/object:Gem::Specification 
+name: verilog_rename
+version: !ruby/object:Gem::Version 
+  hash: 29
+  prerelease: 
+  segments: 
+  - 0
+  - 0
+  - 1
+  version: 0.0.1
+platform: ruby
+authors: 
+- Morgan Prior
+autorequire: 
+bindir: bin
+cert_chain: []
+
+date: 2011-07-03 00:00:00 Z
+dependencies: 
+- !ruby/object:Gem::Dependency 
+  name: verilog
+  prerelease: false
+  requirement: &id001 !ruby/object:Gem::Requirement 
+    none: false
+    requirements: 
+    - - ">="
+      - !ruby/object:Gem::Version 
+        hash: 27
+        segments: 
+        - 0
+        - 0
+        - 2
+        version: 0.0.2
+  type: :runtime
+  version_requirements: *id001
+description: Extension to the verilog gem, adds rename functionality and updates instatiations
+email: verilog_rename_gem@amaras-tech.co.uk
+executables: []
+
+extensions: []
+
+extra_rdoc_files: []
+
+files: 
+- LICENSE.rtf
+- Rakefile
+- bin/rename-verilog
+- lib/verilog/path_files.rb
+- lib/verilog/prefix.rb
+- lib/verilog/rename-backup.rb
+- lib/verilog/rename-oldf.rb
+- lib/verilog/rename.rb
+- lib/verilog_rename.rb
+- spec/example1/beta.v
+- spec/example1/TESTHARNESS.bh.v
+- spec/example2/BETA.v
+- spec/example2/BETA_TH.v
+- spec/example2/BETA_TH_data.v
+- spec/example2/BETA_TH_pkg.v
+- spec/example2/BETA_TH_sim.do
+- spec/fixtures/test_four.vh
+- spec/fixtures/test_one.v
+- spec/fixtures/test_three.v
+- spec/run_examples1.sh
+- spec/run_examples2.sh
+- spec/scratch/fixtures/test_four.vh
+- spec/scratch/fixtures/TEST_ONE.v
+- spec/scratch/fixtures/test_three.v
+- spec/spec_helper.rb
+- spec/temp/BETA_R4.v
+- spec/temp/BETA_R4_TH.v
+- spec/temp/BETA_R4_TH_data.v
+- spec/temp/BETA_R4_TH_pkg.v
+- spec/temp/BETA_TH_sim.do
+- spec/verilog_rename_spec.rb
+homepage: http://amaras-tech.co.uk/software/verilog_rename
+licenses: []
+
+post_install_message: 
+rdoc_options: []
+
+require_paths: 
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement 
+  none: false
+  requirements: 
+  - - ">="
+    - !ruby/object:Gem::Version 
+      hash: 3
+      segments: 
+      - 0
+      version: "0"
+required_rubygems_version: !ruby/object:Gem::Requirement 
+  none: false
+  requirements: 
+  - - ">="
+    - !ruby/object:Gem::Version 
+      hash: 3
+      segments: 
+      - 0
+      version: "0"
+requirements: []
+
+rubyforge_project: 
+rubygems_version: 1.8.5
+signing_key: 
+specification_version: 3
+summary: Extension to the verilog gem for renaming verilog files
+test_files: []
+