verilog_rename 0.0.1
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- data/LICENSE.rtf +680 -0
- data/Rakefile +11 -0
- data/bin/rename-verilog +21 -0
- data/lib/verilog/path_files.rb +51 -0
- data/lib/verilog/prefix.rb +8 -0
- data/lib/verilog/rename-backup.rb +130 -0
- data/lib/verilog/rename-oldf.rb +195 -0
- data/lib/verilog/rename.rb +68 -0
- data/lib/verilog_rename.rb +10 -0
- data/spec/example1/TESTHARNESS.bh.v +8 -0
- data/spec/example1/beta.v +6 -0
- data/spec/example2/BETA.v +5 -0
- data/spec/example2/BETA_TH.v +360 -0
- data/spec/example2/BETA_TH_data.v +0 -0
- data/spec/example2/BETA_TH_pkg.v +0 -0
- data/spec/example2/BETA_TH_sim.do +1 -0
- data/spec/fixtures/test_four.vh +3 -0
- data/spec/fixtures/test_one.v +6 -0
- data/spec/fixtures/test_three.v +18 -0
- data/spec/run_examples1.sh +7 -0
- data/spec/run_examples2.sh +7 -0
- data/spec/scratch/fixtures/TEST_ONE.v +6 -0
- data/spec/scratch/fixtures/test_four.vh +3 -0
- data/spec/scratch/fixtures/test_three.v +18 -0
- data/spec/spec_helper.rb +5 -0
- data/spec/temp/BETA_R4.v +5 -0
- data/spec/temp/BETA_R4_TH.v +360 -0
- data/spec/temp/BETA_R4_TH_data.v +0 -0
- data/spec/temp/BETA_R4_TH_pkg.v +0 -0
- data/spec/temp/BETA_TH_sim.do +1 -0
- data/spec/verilog_rename_spec.rb +30 -0
- metadata +110 -0
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// -------------------------------------------------------------
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//
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// Module: ISRC_ARIZONA_TH
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// Simulink Path: ..\..\..\VerilogD\ISRC_ARIZONA_R3
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// Created: 2011-01-26 18:45:11
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// Generated by MATLAB 7.11 and Simulink HDL Coder 2.0
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// Hierarchy Level: 1
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//
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module BETA_TH;
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`include "BETA_TH_pkg.v"
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`include "BETA_TH_data.v"
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parameter CLKRATE = 12; //uint32
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parameter LATENCY = 12; //uint32
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parameter INITIAL_LATENCY = 0; //uint32
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parameter NO_OF_TESTS = 1667; //uint32
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parameter MAX_TIMEOUT = 145; //uint32
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parameter MAX_ERROR_COUNT = 5001; //uint32
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// Signals
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reg clk; // boolean
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reg rst_an; // boolean
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reg clk_enable; // boolean
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reg signed [23:0] din; // sfix24_En20
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reg notch_ena; // boolean
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wire ce_out; // boolean
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wire signed [23:0] dout; // sfix24_En20
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integer txdataCnt; // uint32
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integer rxdataCnt; // uint32
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reg tb_enb; // boolean
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wire srcDone; // boolean
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wire snkDone; // boolean
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wire testFailure; // boolean
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reg tbenb_dly; // boolean
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reg [3:0] counter; // ufix4
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wire phase_2; // boolean
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wire phase_1; // boolean
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wire rdEnb_phase_1; // boolean
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wire rdEnb_phase_2; // boolean
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wire Data_Type_Conversion2_out1_rdenb; // boolean
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reg [10:0] Data_Type_Conversion2_out1_addr; // ufix11
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reg Data_Type_Conversion2_out1_done; // boolean
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reg signed [23:0] holdData_din; // sfix24_En20
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wire Data_Type_Conversion_notch_ena_out1_rdenb; // boolean
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reg [13:0] Data_Type_Conversion_notch_ena_out1_addr; // ufix14
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reg Data_Type_Conversion_notch_ena_out1_done; // boolean
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reg holdData_notch_ena; // boolean
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reg dout_testFailure; // boolean
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integer dout_timeout; // uint32
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integer dout_errCnt; // uint32
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wire dout_rdenb; // boolean
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reg [12:0] dout_addr; // ufix13
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reg dout_done; // boolean
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wire signed [23:0] dout_ref; // sfix24_En20
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wire signed [23:0] dout_dataTable; // sfix24_En20
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wire signed [23:0] dout_refTmp; // sfix24_En20
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reg signed [23:0] regout; // sfix24_En20
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reg check1_Done; // boolean
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// Module Instances
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BETA u_BETA
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(
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.clk(clk),
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.rst_an(rst_an),
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.clk_enable(clk_enable),
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.din(din),
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.notch_ena(notch_ena),
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.ce_out(ce_out),
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.dout(dout)
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);
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// Block Statements
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// -------------------------------------------------------------
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// Driving the test bench enable
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// -------------------------------------------------------------
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always @(rst_an, snkDone)
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begin
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if (rst_an == 1'b0)
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tb_enb <= 1'b0;
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else if (snkDone == 1'b0 )
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tb_enb <= 1'b1;
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else begin
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# (clk_period * 2);
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tb_enb <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_an) //tb_enb_gen
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begin
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if (~rst_an) begin
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// Nothing to reset.
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end
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else begin
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if (snkDone == 1) begin
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if (testFailure == 0 )
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$display("**************TEST COMPLETED (PASSED)**************");
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else
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$display("**************TEST COMPLETED (FAILED)**************");
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end
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end
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end //tb_enb_gen;
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// -------------------------------------------------------------
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// System Clock (fast clock) and reset
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// -------------------------------------------------------------
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always // clock generation
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begin // clk_gen
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clk <= 1'b0;
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# clk_low;
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clk <= 1'b1;
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# clk_high;
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if (snkDone == 1) begin
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clk <= 1'b0;
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# clk_low;
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clk <= 1'b1;
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# clk_high;
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$stop;
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end
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end // clk_gen
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initial // reset block
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begin // rst_an_gen
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rst_an <= 1'b0;
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# (clk_period * 2);
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@ (posedge clk);
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# (clk_hold);
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rst_an <= 1'b1;
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end // rst_an_gen
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// -------------------------------------------------------------
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// Global clock enable
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// -------------------------------------------------------------
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always @ (posedge clk or negedge rst_an)
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begin: tb_enb_delay
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if (rst_an == 1'b0) begin
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tbenb_dly <= 1'b0;
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end
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else begin
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if (tb_enb == 1'b1) begin
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tbenb_dly <= tb_enb;
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end
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end
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end // tb_enb_delay
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always @(snkDone, tbenb_dly)
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begin
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# clk_hold;
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if (snkDone == 0)
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clk_enable <= tbenb_dly;
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else
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clk_enable <= 0;
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end
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// -------------------------------------------------------------
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// Slow Clock (clkenb)
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// -------------------------------------------------------------
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always @ (posedge clk or negedge rst_an)
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begin: slow_clock_enable
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if (rst_an == 1'b0) begin
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counter <= 4'b0001;
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end
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else begin
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if (tbenb_dly == 1'b1) begin
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if (counter == 4'b1011) begin
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counter <= 4'b0000;
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end
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else begin
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counter <= counter + 1;
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end
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end
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end
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end // slow_clock_enable
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assign phase_2 = (((counter == 4'b0001) ||
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(counter == 4'b0011) ||
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(counter == 4'b0101) ||
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(counter == 4'b0111) ||
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(counter == 4'b1001) ||
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(counter == 4'b1011)) && tbenb_dly == 1'b1)? 1 : 0;
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assign phase_1 = (counter == 4'b0001 && tbenb_dly == 1'b1)? 1 : 0;
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assign rdEnb_phase_1 = phase_1;
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assign rdEnb_phase_2 = phase_2;
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// -------------------------------------------------------------
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// Read the data and transmit it to the DUT
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// -------------------------------------------------------------
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always @(posedge clk or negedge rst_an)
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begin
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Data_Type_Conversion2_out1_task(clk,rst_an,
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Data_Type_Conversion2_out1_rdenb,Data_Type_Conversion2_out1_addr,
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Data_Type_Conversion2_out1_done);
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end
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assign Data_Type_Conversion2_out1_rdenb = rdEnb_phase_1;
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always @ (posedge Data_Type_Conversion2_out1_rdenb or negedge rst_an)
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begin // stimuli_Data_Type_Conversion2_out1_din_reg
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if (~rst_an) begin
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holdData_din <= 24'bx;
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end
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else begin
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holdData_din <= Data_Type_Conversion2_out1_force[Data_Type_Conversion2_out1_addr];
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end
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end
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always @ (Data_Type_Conversion2_out1_rdenb, Data_Type_Conversion2_out1_addr)
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begin // stimuli_Data_Type_Conversion2_out1_din
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if (Data_Type_Conversion2_out1_rdenb == 1) begin
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din <= # clk_hold Data_Type_Conversion2_out1_force[Data_Type_Conversion2_out1_addr];
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end
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else begin
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din <= # clk_hold holdData_din;
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end
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end // stimuli_Data_Type_Conversion2_out1_din
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// -------------------------------------------------------------
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// Read the data and transmit it to the DUT
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// -------------------------------------------------------------
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always @(posedge clk or negedge rst_an)
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begin
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Data_Type_Conversion_notch_ena_out1_task(clk,rst_an,
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Data_Type_Conversion_notch_ena_out1_rdenb,Data_Type_Conversion_notch_ena_out1_addr,
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Data_Type_Conversion_notch_ena_out1_done);
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end
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assign Data_Type_Conversion_notch_ena_out1_rdenb = rdEnb_phase_2;
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always @ (posedge clk or negedge rst_an)
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begin // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena_reg
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if (~rst_an) begin
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holdData_notch_ena <= 1'bx;
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end
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else begin
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holdData_notch_ena <= Data_Type_Conversion_notch_ena_out1_force;
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end
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end
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always @ (Data_Type_Conversion_notch_ena_out1_rdenb, Data_Type_Conversion_notch_ena_out1_addr)
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begin // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena
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if (Data_Type_Conversion_notch_ena_out1_rdenb == 1) begin
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notch_ena <= # clk_hold Data_Type_Conversion_notch_ena_out1_force;
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end
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else begin
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notch_ena <= # clk_hold holdData_notch_ena;
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end
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end // stimuli_Data_Type_Conversion_notch_ena_out1_notch_ena
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// -------------------------------------------------------------
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// Create done signal for Input data
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// -------------------------------------------------------------
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assign srcDone = Data_Type_Conversion2_out1_done && Data_Type_Conversion_notch_ena_out1_done;
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// -------------------------------------------------------------
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// Checker: Checking the data received from the DUT.
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// -------------------------------------------------------------
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always @(posedge clk or negedge rst_an)
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begin
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dout_task(clk,rst_an,
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dout_rdenb,dout_addr,
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dout_done);
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end
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assign dout_rdenb = ce_out;
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assign # clk_hold dout_dataTable = dout_expected[dout_addr];
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// ---- Bypass Register ----
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always @ (posedge clk or negedge rst_an)
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begin: DataHoldRegister_temp_process10
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if (rst_an == 1'b0) begin
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regout <= 0;
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end
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else begin
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if (ce_out == 1'b1) begin
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regout <= dout_dataTable;
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end
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end
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end // DataHoldRegister_temp_process10
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assign dout_refTmp = (ce_out == 1'b1) ? dout_dataTable :
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regout;
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assign dout_ref = dout_refTmp;
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always @ (posedge clk or negedge rst_an) // checker_dout
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begin
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if (rst_an == 0) begin
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dout_timeout <= 0;
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dout_testFailure <= 0;
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dout_errCnt <= 0;
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end
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else begin
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if (dout_rdenb == 1 ) begin
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dout_timeout <= 0;
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if (dout !== dout_expected[dout_addr]) begin
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dout_errCnt <= dout_errCnt + 1;
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dout_testFailure <= 1;
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$display("ERROR in dout at time %t : Expected '%h' Actual '%h'",
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$time, dout_expected[dout_addr], dout);
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if (dout_errCnt >= MAX_ERROR_COUNT)
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$display("Warning: Number of errors for dout have exceeded the maximum error limit");
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end
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end
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else if (dout_timeout > MAX_TIMEOUT && dout_rdenb == 1 ) begin
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dout_errCnt <= dout_errCnt + 1;
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dout_testFailure <= 1;
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$display ("Error: Timeout - Data was not received for dout.");
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$stop;
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end
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else if (dout_rdenb == 1) begin
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dout_timeout <= dout_timeout + 1 ;
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end
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end
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end // checker_dout
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always @ (posedge clk or negedge rst_an) // checkDone_1
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begin
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if (rst_an == 0)
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check1_Done <= 0;
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+
else if ((check1_Done == 0) && (dout_done == 1) && (dout_rdenb == 1))
|
345
|
+
check1_Done <= 1;
|
346
|
+
end
|
347
|
+
|
348
|
+
// -------------------------------------------------------------
|
349
|
+
// Create done and test failure signal for output data
|
350
|
+
// -------------------------------------------------------------
|
351
|
+
|
352
|
+
assign snkDone = check1_Done;
|
353
|
+
|
354
|
+
assign testFailure = dout_testFailure;
|
355
|
+
|
356
|
+
// Assignment Statements
|
357
|
+
|
358
|
+
|
359
|
+
|
360
|
+
endmodule // ISRC_ARIZONA_TH
|
File without changes
|
File without changes
|
@@ -0,0 +1 @@
|
|
1
|
+
vsub vcs -R -PP -l run.log +notimingchecks +libext+.v+.bh.v -y ./ BETA_TH.v $*
|