udb 0.1.0 → 0.1.1

data/.data/spec/std/isa/inst/Zabha/amomin.h.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amomin.h.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amomin.h.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amominu.b.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amominu.b.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amominu.b.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amominu.b.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amominu.h.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amominu.h.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amominu.h.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amominu.h.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoor.b.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoor.b.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoor.b.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoor.b.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoor.h.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoor.h.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoor.h.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoor.h.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoswap.b.aq.yaml

@@ -43,7 +43,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoswap.b.aqrl.yaml

@@ -43,7 +43,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoswap.b.rl.yaml

@@ -41,7 +41,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoswap.b.yaml

@@ -41,7 +41,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoswap.h.aq.yaml

@@ -43,7 +43,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoswap.h.aqrl.yaml

@@ -43,7 +43,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoswap.h.rl.yaml

@@ -41,7 +41,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoswap.h.yaml

@@ -41,7 +41,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoxor.b.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoxor.b.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoxor.b.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoxor.b.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(8, virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoxor.h.aq.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zabha/amoxor.h.aqrl.yaml

@@ -44,7 +44,7 @@ operation(): |
   memory_model_acquire();
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoxor.h.rl.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding);
 
   memory_model_release();
 

data/.data/spec/std/isa/inst/Zabha/amoxor.h.yaml

@@ -42,7 +42,7 @@ operation(): |
   }
 
   XReg virtual_address = X[xs1];
-  X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
+  X[xd] = amo(16, virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/Zalrsc/lr.SIZE.AQRL.layout

@@ -127,7 +127,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<<%= current_size[:align_bits] %>>(virtual_address)) {
+  if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -145,7 +145,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<<%= current_size[:load_reserved_bits] %>>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(<%= current_size[:load_reserved_bits] %>, virtual_address, aq, rl, $encoding);
 <%- if size == "w" -%>
   if (xlen() == 64) {
     X[xd] = load_value;

data/.data/spec/std/isa/inst/Zalrsc/lr.d.aq.yaml

@@ -81,7 +81,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -99,7 +99,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<64>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(64, virtual_address, aq, rl, $encoding);
   X[xd] = load_value;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/lr.d.aqrl.yaml

@@ -81,7 +81,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -99,7 +99,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<64>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(64, virtual_address, aq, rl, $encoding);
   X[xd] = load_value;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/lr.d.rl.yaml

@@ -81,7 +81,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -99,7 +99,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<64>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(64, virtual_address, aq, rl, $encoding);
   X[xd] = load_value;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/lr.d.yaml

@@ -81,7 +81,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -99,7 +99,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<64>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(64, virtual_address, aq, rl, $encoding);
   X[xd] = load_value;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aq.yaml

@@ -84,7 +84,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml

@@ -84,7 +84,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml

@@ -84,7 +84,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/lr.w.yaml

@@ -84,7 +84,7 @@ operation(): |
 
   XReg virtual_address = X[xs1];
 
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -102,7 +102,7 @@ operation(): |
     }
   }
 
-  XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding);
+  XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
   if (xlen() == 64) {
     X[xd] = load_value;
   } else {

data/.data/spec/std/isa/inst/Zalrsc/sc.SIZE.AQRL.layout

@@ -184,7 +184,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<<%= current_size[:align_bits] %>>(virtual_address)) {
+  if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -202,7 +202,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<<%= current_size[:operation_bits] %>>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(<%= current_size[:operation_bits] %>, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aq.yaml

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.rl.yaml

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.d.yaml

@@ -141,7 +141,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<64>(virtual_address)) {
+  if (!is_naturally_aligned(64, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -159,7 +159,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(64, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aq.yaml

@@ -143,7 +143,7 @@ operation(): |
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
-  if (!is_naturally_aligned<32>(virtual_address)) {
+  if (!is_naturally_aligned(32, virtual_address)) {
     # can raise either LoadAddressMisaligned *or* LoadAccessFault
     #
     # from the spec:
@@ -161,7 +161,7 @@ operation(): |
     }
   }
 
-  Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding);
+  Boolean success = store_conditional(32, virtual_address, value, aq, rl, $encoding);
   X[xd] = success ? 0 : 1;
 
 # SPDX-SnippetBegin