udb 0.1.0 → 0.1.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 9e3417aff756dc8df755509f12b105e5094f469841956bb3ff2713f550abf7c6
-  data.tar.gz: '0870315f611d84d85abe12374c1da87f3e3a4bcdb137723d2763db10b595705e'
+  metadata.gz: cba91646e49cff73f519ba03d2e8af8231c4452112a4ff8b897eda049210c128
+  data.tar.gz: 4678776cb3b1405c5171d6016ccaec35135cdaf5785437c77b16b7a37c8d13c9
 SHA512:
-  metadata.gz: cb45226f11771b8e061093aad2fad30409f73fa9c8217810a74d2f9bea414b7b3069f6c59b5fa0e7b3cdb1ab29fa17f0ed0423ebb19560de5ab3cd615eaf18d9
-  data.tar.gz: 4108df795658ab48fc4a8c3a077fc195178aac3865be3ceb29701447475e2308c6f23f00649c6665b6928ee9dc2964b02c9328fe0b1a9615be3ee70eccbee88f
+  metadata.gz: cbcb181aafd72f9d7fb904125f272872bfebb7c9a900d648412f01ea7b541d35cc4b27b4ae0b22b6008e45dcd565776ac49819eea4a2d9985a16d1faec938f81
+  data.tar.gz: 732cdfe4b0b6273034cae2308316991cf25f141c504221d5762250b803b0894a8ec2c47bfef646659ce3c6273ae6e83000e67e86f3955a3f28161b9ffa35986b

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mienter.nest.yaml

@@ -32,29 +32,29 @@ operation(): |
   XReg qc_mcause_val = CSR[qc.mcause].sw_read();
   XReg reserved_val = 0;
   if (CSR[mnstatus].NMIE == 1'b1) {
-    write_memory<32>(virtual_address -  4, mepc_val, $encoding);
+    write_memory(32, virtual_address -  4, mepc_val, $encoding);
   } else {
-    write_memory<32>(virtual_address -  4, mnepc_val, $encoding);
+    write_memory(32, virtual_address -  4, mnepc_val, $encoding);
   }
-  write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
-  write_memory<32>(virtual_address - 12, qc_mcause_val, $encoding);
-  write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
-  write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
-  write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
-  write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);
-  write_memory<32>(virtual_address - 36, X[10][31:0], $encoding);
-  write_memory<32>(virtual_address - 40, X[11][31:0], $encoding);
-  write_memory<32>(virtual_address - 44, X[12][31:0], $encoding);
-  write_memory<32>(virtual_address - 48, X[13][31:0], $encoding);
-  write_memory<32>(virtual_address - 52, X[14][31:0], $encoding);
-  write_memory<32>(virtual_address - 56, X[15][31:0], $encoding);
-  write_memory<32>(virtual_address - 60, X[16][31:0], $encoding);
-  write_memory<32>(virtual_address - 64, X[17][31:0], $encoding);
-  write_memory<32>(virtual_address - 68, X[28][31:0], $encoding);
-  write_memory<32>(virtual_address - 72, X[29][31:0], $encoding);
-  write_memory<32>(virtual_address - 76, X[30][31:0], $encoding);
-  write_memory<32>(virtual_address - 80, X[31][31:0], $encoding);
+  write_memory(32, virtual_address -  8, X[ 8][31:0], $encoding);
+  write_memory(32, virtual_address - 12, qc_mcause_val, $encoding);
+  write_memory(32, virtual_address - 16, X[ 1][31:0], $encoding);
+  write_memory(32, virtual_address - 20, reserved_val, $encoding);
+  write_memory(32, virtual_address - 24, X[ 5][31:0], $encoding);
+  write_memory(32, virtual_address - 28, X[ 6][31:0], $encoding);
+  write_memory(32, virtual_address - 32, X[ 7][31:0], $encoding);
+  write_memory(32, virtual_address - 36, X[10][31:0], $encoding);
+  write_memory(32, virtual_address - 40, X[11][31:0], $encoding);
+  write_memory(32, virtual_address - 44, X[12][31:0], $encoding);
+  write_memory(32, virtual_address - 48, X[13][31:0], $encoding);
+  write_memory(32, virtual_address - 52, X[14][31:0], $encoding);
+  write_memory(32, virtual_address - 56, X[15][31:0], $encoding);
+  write_memory(32, virtual_address - 60, X[16][31:0], $encoding);
+  write_memory(32, virtual_address - 64, X[17][31:0], $encoding);
+  write_memory(32, virtual_address - 68, X[28][31:0], $encoding);
+  write_memory(32, virtual_address - 72, X[29][31:0], $encoding);
+  write_memory(32, virtual_address - 76, X[30][31:0], $encoding);
+  write_memory(32, virtual_address - 80, X[31][31:0], $encoding);
   X[8] = X[2];
   X[2] = X[2] - 96;
   CSR[mstatus].MIE = 1'b1;

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mienter.yaml

@@ -32,28 +32,28 @@ operation(): |
   XReg qc_mcause_val = CSR[qc.mcause].sw_read();
   XReg reserved_val = 0;
   if (CSR[mnstatus].NMIE == 1'b1) {
-    write_memory<32>(virtual_address -  4, mepc_val, $encoding);
+    write_memory(32, virtual_address -  4, mepc_val, $encoding);
   } else {
-    write_memory<32>(virtual_address -  4, mnepc_val, $encoding);
+    write_memory(32, virtual_address -  4, mnepc_val, $encoding);
   }
-  write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
-  write_memory<32>(virtual_address - 12, qc_mcause_val, $encoding);
-  write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
-  write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
-  write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
-  write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);
-  write_memory<32>(virtual_address - 36, X[10][31:0], $encoding);
-  write_memory<32>(virtual_address - 40, X[11][31:0], $encoding);
-  write_memory<32>(virtual_address - 44, X[12][31:0], $encoding);
-  write_memory<32>(virtual_address - 48, X[13][31:0], $encoding);
-  write_memory<32>(virtual_address - 52, X[14][31:0], $encoding);
-  write_memory<32>(virtual_address - 56, X[15][31:0], $encoding);
-  write_memory<32>(virtual_address - 60, X[16][31:0], $encoding);
-  write_memory<32>(virtual_address - 64, X[17][31:0], $encoding);
-  write_memory<32>(virtual_address - 68, X[28][31:0], $encoding);
-  write_memory<32>(virtual_address - 72, X[29][31:0], $encoding);
-  write_memory<32>(virtual_address - 76, X[30][31:0], $encoding);
-  write_memory<32>(virtual_address - 80, X[31][31:0], $encoding);
+  write_memory(32, virtual_address -  8, X[ 8][31:0], $encoding);
+  write_memory(32, virtual_address - 12, qc_mcause_val, $encoding);
+  write_memory(32, virtual_address - 16, X[ 1][31:0], $encoding);
+  write_memory(32, virtual_address - 20, reserved_val, $encoding);
+  write_memory(32, virtual_address - 24, X[ 5][31:0], $encoding);
+  write_memory(32, virtual_address - 28, X[ 6][31:0], $encoding);
+  write_memory(32, virtual_address - 32, X[ 7][31:0], $encoding);
+  write_memory(32, virtual_address - 36, X[10][31:0], $encoding);
+  write_memory(32, virtual_address - 40, X[11][31:0], $encoding);
+  write_memory(32, virtual_address - 44, X[12][31:0], $encoding);
+  write_memory(32, virtual_address - 48, X[13][31:0], $encoding);
+  write_memory(32, virtual_address - 52, X[14][31:0], $encoding);
+  write_memory(32, virtual_address - 56, X[15][31:0], $encoding);
+  write_memory(32, virtual_address - 60, X[16][31:0], $encoding);
+  write_memory(32, virtual_address - 64, X[17][31:0], $encoding);
+  write_memory(32, virtual_address - 68, X[28][31:0], $encoding);
+  write_memory(32, virtual_address - 72, X[29][31:0], $encoding);
+  write_memory(32, virtual_address - 76, X[30][31:0], $encoding);
+  write_memory(32, virtual_address - 80, X[31][31:0], $encoding);
   X[8] = X[2];
   X[2] = X[2] - 96;

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.c.mileaveret.yaml

@@ -27,30 +27,30 @@ encoding:
 operation(): |
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);
   XReg virtual_address = virtual_address_sp + 96;
-  XReg prev_retpc = read_memory<32>(virtual_address -  4, $encoding);
-  XReg qc_mcause_val = read_memory<32>(virtual_address - 12, $encoding);
+  XReg prev_retpc = read_memory(32, virtual_address -  4, $encoding);
+  XReg qc_mcause_val = read_memory(32, virtual_address - 12, $encoding);
   Bits<1> nmie_val = CSR[mnstatus].NMIE;
   XReg qc_mcause_prev_val = CSR[qc.mcause].sw_read();
   XReg qc_mcause_nmip_excp_mask = (32'b1 << 24) | (32'b1 << 25);
   XReg qc_mcause_new_val = (qc_mcause_val & ~qc_mcause_nmip_excp_mask) | (qc_mcause_prev_val & qc_mcause_nmip_excp_mask);
   CSR[qc.mcause].sw_write(qc_mcause_new_val);
-  X[ 8] = read_memory<32>(virtual_address -  8, $encoding);
-  X[ 1] = read_memory<32>(virtual_address - 16, $encoding);
-  X[ 5] = read_memory<32>(virtual_address - 24, $encoding);
-  X[ 6] = read_memory<32>(virtual_address - 28, $encoding);
-  X[ 7] = read_memory<32>(virtual_address - 32, $encoding);
-  X[10] = read_memory<32>(virtual_address - 36, $encoding);
-  X[11] = read_memory<32>(virtual_address - 40, $encoding);
-  X[12] = read_memory<32>(virtual_address - 44, $encoding);
-  X[13] = read_memory<32>(virtual_address - 48, $encoding);
-  X[14] = read_memory<32>(virtual_address - 52, $encoding);
-  X[15] = read_memory<32>(virtual_address - 56, $encoding);
-  X[16] = read_memory<32>(virtual_address - 60, $encoding);
-  X[17] = read_memory<32>(virtual_address - 64, $encoding);
-  X[28] = read_memory<32>(virtual_address - 68, $encoding);
-  X[29] = read_memory<32>(virtual_address - 72, $encoding);
-  X[30] = read_memory<32>(virtual_address - 76, $encoding);
-  X[31] = read_memory<32>(virtual_address - 80, $encoding);
+  X[ 8] = read_memory(32, virtual_address -  8, $encoding);
+  X[ 1] = read_memory(32, virtual_address - 16, $encoding);
+  X[ 5] = read_memory(32, virtual_address - 24, $encoding);
+  X[ 6] = read_memory(32, virtual_address - 28, $encoding);
+  X[ 7] = read_memory(32, virtual_address - 32, $encoding);
+  X[10] = read_memory(32, virtual_address - 36, $encoding);
+  X[11] = read_memory(32, virtual_address - 40, $encoding);
+  X[12] = read_memory(32, virtual_address - 44, $encoding);
+  X[13] = read_memory(32, virtual_address - 48, $encoding);
+  X[14] = read_memory(32, virtual_address - 52, $encoding);
+  X[15] = read_memory(32, virtual_address - 56, $encoding);
+  X[16] = read_memory(32, virtual_address - 60, $encoding);
+  X[17] = read_memory(32, virtual_address - 64, $encoding);
+  X[28] = read_memory(32, virtual_address - 68, $encoding);
+  X[29] = read_memory(32, virtual_address - 72, $encoding);
+  X[30] = read_memory(32, virtual_address - 76, $encoding);
+  X[31] = read_memory(32, virtual_address - 80, $encoding);
   X[2] = X[2] + 96;
   if (nmie_val == 1'b1) {
     XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lb.yaml

@@ -34,4 +34,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8);
+  X[rd] = sext(read_memory(8, virtual_address, $encoding), 8);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lbu.yaml

@@ -34,4 +34,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  X[rd] = read_memory<8>(virtual_address, $encoding);
+  X[rd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lh.yaml

@@ -34,4 +34,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16);
+  X[rd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lhu.yaml

@@ -34,4 +34,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  X[rd] = read_memory<16>(virtual_address, $encoding);
+  X[rd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.lw.yaml

@@ -34,4 +34,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  X[rd] = read_memory<32>(virtual_address, $encoding);
+  X[rd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sb.yaml

@@ -33,4 +33,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  write_memory<8>(virtual_address, X[rs2][7:0], $encoding);
+  write_memory(8, virtual_address, X[rs2][7:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sh.yaml

@@ -33,4 +33,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  write_memory<16>(virtual_address, X[rs2][15:0], $encoding);
+  write_memory(16, virtual_address, X[rs2][15:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.e.sw.yaml

@@ -33,4 +33,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + $signed(imm);
-  write_memory<32>(virtual_address, X[rs2][31:0], $encoding);
+  write_memory(32, virtual_address, X[rs2][31:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrb.yaml

@@ -37,4 +37,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8);
+  X[rd] = sext(read_memory(8, virtual_address, $encoding), 8);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrbu.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  X[rd] = read_memory<8>(virtual_address, $encoding);
+  X[rd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrh.yaml

@@ -37,4 +37,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16);
+  X[rd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrhu.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  X[rd] = read_memory<16>(virtual_address, $encoding);
+  X[rd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lrw.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  X[rd] = read_memory<32>(virtual_address, $encoding);
+  X[rd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lwm.yaml

@@ -41,6 +41,6 @@ operation(): |
   XReg num_words = X[rs2][4:0];
   raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + num_words) > 32);
   for (U32 i = 0; i < num_words; i++) {
-    X[rd + i] = read_memory<32>(vaddr, $encoding);
+    X[rd + i] = read_memory(32, vaddr, $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.lwmi.yaml

@@ -40,6 +40,6 @@ operation(): |
   XReg vaddr = X[rs1] + imm;
   raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + length) > 32);
   for (U32 i = 0; i < length; i++) {
-    X[rd + i] = read_memory<32>(vaddr, $encoding);
+    X[rd + i] = read_memory(32, vaddr, $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.setwm.yaml

@@ -40,6 +40,6 @@ operation(): |
   Bits<32> write_value = X[rs3][31:0];
   XReg num_words = X[rs2][4:0];
   for (U32 i = 0; i < num_words; i++) {
-    write_memory<32>(vaddr, write_value, $encoding);
+    write_memory(32, vaddr, write_value, $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.setwmi.yaml

@@ -39,6 +39,6 @@ operation(): |
   XReg vaddr = X[rs1] + imm;
   Bits<32> write_value = X[rs3][31:0];
   for (U32 i = 0; i < length; i++) {
-    write_memory<32>(vaddr, write_value, $encoding);
+    write_memory(32, vaddr, write_value, $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srb.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  write_memory<8>(virtual_address, X[rs3][7:0], $encoding);
+  write_memory(8, virtual_address, X[rs3][7:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srh.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  write_memory<16>(virtual_address, X[rs3][15:0], $encoding);
+  write_memory(16, virtual_address, X[rs3][15:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.srw.yaml

@@ -36,4 +36,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + (X[rs2] << shamt);
-  write_memory<32>(virtual_address, X[rs3][31:0], $encoding);
+  write_memory(32, virtual_address, X[rs3][31:0], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.swm.yaml

@@ -41,6 +41,6 @@ operation(): |
   XReg num_words = X[rs2][4:0];
   raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + num_words) > 32);
   for (U32 i = 0; i < num_words; i++) {
-    write_memory<32>(vaddr, X[rs3 + i], $encoding);
+    write_memory(32, vaddr, X[rs3 + i], $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/custom/isa/qc_iu/inst/Xqci/qc.swmi.yaml

@@ -40,6 +40,6 @@ operation(): |
   XReg vaddr = X[rs1] + imm;
   raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + length) > 32);
   for (U32 i = 0; i < length; i++) {
-    write_memory<32>(vaddr, X[rs3 + i], $encoding);
+    write_memory(32, vaddr, X[rs3 + i], $encoding);
     vaddr = vaddr + 4;
   }

data/.data/spec/std/isa/inst/C/c.ld.yaml

@@ -56,7 +56,7 @@ operation(): |
 
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zclsd)) {
-      Bits<64> val = read_memory<64>(X[creg2reg(xs1)] + imm, $encoding);
+      Bits<64> val = read_memory(64, X[creg2reg(xs1)] + imm, $encoding);
       X[creg2reg(xd)] = val[31:0];
       X[creg2reg(xd + 1)] = val[63:32];
     } else {
@@ -64,7 +64,7 @@ operation(): |
     }
   } else {
     XReg virtual_address = X[creg2reg(xs1)] + imm;
-    X[creg2reg(xd)] = sext(read_memory<64>(virtual_address, $encoding), 64);
+    X[creg2reg(xd)] = sext(read_memory(64, virtual_address, $encoding), 64);
   }
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -54,7 +54,7 @@ operation(): |
   }
 
   XReg virtual_address = X[2] + imm;
-  Bits<64> value = read_memory<64>(virtual_address, $encoding);
+  Bits<64> value = read_memory(64, virtual_address, $encoding);
 
   if (xlen()== 64) {
     X[creg2reg(xd)] = value;

data/.data/spec/std/isa/inst/C/c.lw.yaml

@@ -38,7 +38,7 @@ operation(): |
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  X[creg2reg(xd)] = sext(read_memory<32>(virtual_address, $encoding), 32);
+  X[creg2reg(xd)] = sext(read_memory(32, virtual_address, $encoding), 32);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/C/c.lwsp.yaml

@@ -38,4 +38,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  X[xd] = sext(read_memory<32>(virtual_address, $encoding), 32);
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/C/c.sd.yaml

@@ -58,10 +58,10 @@ operation(): |
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zclsd)) {
       Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]};
-      write_memory<64>(virtual_address, data, $encoding);
+      write_memory(64, virtual_address, data, $encoding);
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   } else {
-    write_memory<64>(virtual_address, X[creg2reg(xs2)], $encoding);
+    write_memory(64, virtual_address, X[creg2reg(xs2)], $encoding);
   }

data/.data/spec/std/isa/inst/C/c.sdsp.yaml

@@ -54,10 +54,10 @@ operation(): |
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zclsd)) {
       Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]};
-      write_memory<64>(virtual_address, data, $encoding);
+      write_memory(64, virtual_address, data, $encoding);
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   } else {
-    write_memory<64>(virtual_address, X[creg2reg(xs2)], $encoding);
+    write_memory(64, virtual_address, X[creg2reg(xs2)], $encoding);
   }

data/.data/spec/std/isa/inst/C/c.sw.yaml

@@ -38,4 +38,4 @@ operation(): |
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  write_memory<32>(virtual_address, X[creg2reg(xs2)][31:0], $encoding);
+  write_memory(32, virtual_address, X[creg2reg(xs2)][31:0], $encoding);

data/.data/spec/std/isa/inst/C/c.swsp.yaml

@@ -36,4 +36,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory<32>(virtual_address, X[xs2][31:0], $encoding);
+  write_memory(32, virtual_address, X[xs2][31:0], $encoding);

data/.data/spec/std/isa/inst/F/flw.yaml

@@ -35,10 +35,10 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  Bits<32> sp_value = read_memory<32>(virtual_address, $encoding);
+  Bits<32> sp_value = read_memory(32, virtual_address, $encoding);
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box<32, 64>(sp_value);
+    f[fd] = nan_box(32, 64, sp_value);
   } else {
     f[fd] = sp_value;
   }

data/.data/spec/std/isa/inst/F/fmv.w.x.yaml

@@ -34,7 +34,7 @@ operation(): |
   Bits<32> sp_value = X[xs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box<32, 64>(sp_value);
+    f[fd] = nan_box(32, 64, sp_value);
   } else {
     f[fd] = sp_value;
   }

data/.data/spec/std/isa/inst/F/fsgnj.s.yaml

@@ -42,7 +42,7 @@ operation(): |
   Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box<32, 64>(sp_value);
+    f[fd] = nan_box(32, 64, sp_value);
   } else {
     f[fd] = sp_value;
   }

data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml

@@ -41,7 +41,7 @@ operation(): |
   Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box<32, 64>(sp_value);
+    f[fd] = nan_box(32, 64, sp_value);
   } else {
     f[fd] = sp_value;
   }

data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml

@@ -40,7 +40,7 @@ operation(): |
   Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box<32, 64>(sp_value);
+    f[fd] = nan_box(32, 64, sp_value);
   } else {
     f[fd] = sp_value;
   }

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -35,7 +35,7 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<32>(virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lb.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<8>(virtual_address, $encoding), 8);
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lbu.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<8>(virtual_address, $encoding);
+  X[xd] = read_memory(8, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -53,7 +53,7 @@ operation(): |
 
   if (xlen() == 32) {
     if (implemented?(ExtensionName::Zilsd)) {
-      Bits<64> data = read_memory<64>(virtual_address, $encoding);
+      Bits<64> data = read_memory(64, virtual_address, $encoding);
 
       X[xd] = data[31:0];
       X[xd+1] = data[63:32];
@@ -61,7 +61,7 @@ operation(): |
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   } else {
-    X[xd] = read_memory<64>(virtual_address, $encoding);
+    X[xd] = read_memory(64, virtual_address, $encoding);
   }
 
 # SPDX-SnippetBegin

data/.data/spec/std/isa/inst/I/lh.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<16>(virtual_address, $encoding), 16);
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lhu.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<16>(virtual_address, $encoding);
+  X[xd] = read_memory(16, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lw.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = sext(read_memory<32>(virtual_address, $encoding), 32);
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/lwu.yaml

@@ -34,7 +34,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<32>(virtual_address, $encoding);
+  X[xd] = read_memory(32, virtual_address, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sb.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<8>(virtual_address, X[xs2][7:0], $encoding);
+  write_memory(8, virtual_address, X[xs2][7:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -59,7 +59,7 @@ operation(): |
     data = X[xs2];
   }
 
-  write_memory<64>(virtual_address, data, $encoding);
+  write_memory(64, virtual_address, data, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sh.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<16>(virtual_address, X[xs2][15:0], $encoding);
+  write_memory(16, virtual_address, X[xs2][15:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

data/.data/spec/std/isa/inst/I/sw.yaml

@@ -31,7 +31,7 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<32>(virtual_address, X[xs2][31:0], $encoding);
+  write_memory(32, virtual_address, X[xs2][31:0], $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>