sunxi_gpio 0.0.3

checksums.yaml

@@ -0,0 +1,7 @@
+---
+SHA1:
+  metadata.gz: 6c50611c24ebb118b677a76ef041ec5e26a65faf
+  data.tar.gz: 7743b9dce6dcabc6ce586d3734c832caa745ce53
+SHA512:
+  metadata.gz: 7cda901080750937c67c20de0155891e4694ed3928485bfe168f8030ce798e3a4359dc6ec97809463a1cea422fd49b0c7ccc1e3d3915ae6122221ca0d4d5b955
+  data.tar.gz: 9bdc783d08856e7f83ce8ed4c1dd3f4060d8a93bdfe700c4fc239ec19e533019af4772e52a328f538e7dad54077a2fd56375697998865f64593a0e64a14ef44f

data/README.md

@@ -0,0 +1,45 @@
+sunxi_gpio gem
+===============
+
+Native Ruby Extension to work with Sunxi GPIO. This gem is currently **beta**. It supports writing, reading, watching.  
+
+
+
+## Installtion
+
+```
+gem install sunxi_gpio
+```
+
+
+## Usage
+
+### Simple writing
+
+```ruby
+require 'sunxi_gpio/pin'
+
+pin = SunxiGPIO::Pin.new(pin: :PB2, direction: :out)
+pin.on
+sleep 1
+pin.off
+```
+
+
+### Watching
+
+```ruby
+require 'sunxi_gpio/pin'
+
+pin = SunxiGPIO::Pin.new(pin: :PB2, direction: :out)
+
+pin.watch do
+  puts "Pin changed from #{last_value} to #{value}"
+end
+```
+
+
+## Contributors
+
+* [phortx](https://github.com/phortx)
+* [happychriss](https://github.com/happychriss)

data/ext/sunxi_gpio/extconf.rb

@@ -0,0 +1,3 @@
+require 'mkmf'
+
+create_makefile 'sunxi_gpio'

data/ext/sunxi_gpio/gpio_lib.c

@@ -0,0 +1,177 @@
+/*
+ * gpio_lib.c
+ *
+ * Copyright 2013 Stefan Mavrodiev <support@olimex.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+
+#include <ctype.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <math.h>
+#include <time.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/select.h>
+#include <pthread.h>
+#include <unistd.h>
+#include <sched.h>
+
+#include "gpio_lib.h"
+
+
+unsigned int SUNXI_PIO_BASE = 0;
+static volatile long int *gpio_map = NULL;
+
+int sunxi_gpio_init(void) {
+    int fd;
+    unsigned int addr_start, addr_offset;
+    unsigned int PageSize, PageMask;
+
+
+    fd = open("/dev/mem", O_RDWR);
+    if(fd < 0) {
+        return SETUP_DEVMEM_FAIL;
+    }
+
+    PageSize = sysconf(_SC_PAGESIZE);
+    PageMask = (~(PageSize-1));
+
+    addr_start = SW_PORTC_IO_BASE & PageMask;
+    addr_offset = SW_PORTC_IO_BASE & ~PageMask;
+
+    gpio_map = (void *)mmap(0, PageSize*2, PROT_READ|PROT_WRITE, MAP_SHARED, fd, addr_start);
+    if(gpio_map == MAP_FAILED) {
+        return SETUP_MMAP_FAIL;
+    }
+
+    SUNXI_PIO_BASE = (unsigned int)gpio_map;
+    SUNXI_PIO_BASE += addr_offset;
+
+    close(fd);
+    return SETUP_OK;
+}
+
+int sunxi_gpio_set_cfgpin(unsigned int pin, unsigned int val) {
+
+    unsigned int cfg;
+    unsigned int bank = GPIO_BANK(pin);
+    unsigned int index = GPIO_CFG_INDEX(pin);
+    unsigned int offset = GPIO_CFG_OFFSET(pin);
+
+    if(SUNXI_PIO_BASE == 0) {
+        return -1;
+    }
+
+    struct sunxi_gpio *pio =
+        &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+
+    cfg = *(&pio->cfg[0] + index);
+    cfg &= ~(0xf << offset);
+    cfg |= val << offset;
+
+    *(&pio->cfg[0] + index) = cfg;
+
+    return 0;
+}
+
+int sunxi_gpio_get_cfgpin(unsigned int pin) {
+
+    unsigned int cfg;
+    unsigned int bank = GPIO_BANK(pin);
+    unsigned int index = GPIO_CFG_INDEX(pin);
+    unsigned int offset = GPIO_CFG_OFFSET(pin);
+    if(SUNXI_PIO_BASE == 0)
+    {
+        return -1;
+    }
+    struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+    cfg = *(&pio->cfg[0] + index);
+    cfg >>= offset;
+    return (cfg & 0xf);
+}
+int sunxi_gpio_output(unsigned int pin, unsigned int val) {
+
+    unsigned int bank = GPIO_BANK(pin);
+    unsigned int num = GPIO_NUM(pin);
+
+    if(SUNXI_PIO_BASE == 0)
+    {
+        return -1;
+    }
+    struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+    if(val)
+        *(&pio->dat) |= 1 << num;
+    else
+        *(&pio->dat) &= ~(1 << num);
+
+    return 0;
+}
+
+int sunxi_gpio_input(unsigned int pin) {
+
+    unsigned int dat;
+    unsigned int bank = GPIO_BANK(pin);
+    unsigned int num = GPIO_NUM(pin);
+
+    if(SUNXI_PIO_BASE == 0)
+    {
+        return -1;
+    }
+
+    struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+    dat = *(&pio->dat);
+    dat >>= num;
+
+    return (dat & 0x1);
+}
+
+// http://www.cubieforums.com/index.php?topic=2881.15
+int sunxi_gpio_set_pull(unsigned int pin, unsigned int val) {
+    unsigned int pull;
+    unsigned int bank = GPIO_BANK(pin);
+    unsigned int index = GPIO_PULL_INDEX(pin);
+    unsigned int offset = GPIO_PULL_OFFSET(pin);
+    struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+    pull = *(&pio->pull[0] + index);
+    pull &= ~(0x3 << offset);
+    pull |= val << offset;
+
+    *(&pio->pull[0] + index) = pull;
+
+    return 0;
+}
+
+void sunxi_gpio_cleanup(void)
+{
+    unsigned int PageSize;
+    if (gpio_map == NULL)
+        return;
+
+    PageSize = sysconf(_SC_PAGESIZE);
+    munmap((void*)gpio_map, PageSize*2);
+}
+

data/ext/sunxi_gpio/gpio_lib.h

@@ -0,0 +1,160 @@
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+
+#define SW_PORTC_IO_BASE 0x01c20800
+
+
+#define SUNXI_GPIO_A	0
+#define SUNXI_GPIO_B	1
+#define SUNXI_GPIO_C	2
+#define SUNXI_GPIO_D	3
+#define SUNXI_GPIO_E	4
+#define SUNXI_GPIO_F	5
+#define SUNXI_GPIO_G	6
+#define SUNXI_GPIO_H	7
+#define SUNXI_GPIO_I	8
+
+#define SETUP_OK            0
+#define SETUP_DEVMEM_FAIL   1
+#define SETUP_MALLOC_FAIL   2
+#define SETUP_MMAP_FAIL     3
+
+#define HIGH    1
+#define LOW     0
+
+#define INPUT   0
+#define OUTPUT  1
+#define PER     2
+
+
+struct sunxi_gpio {
+    unsigned int cfg[4];
+    unsigned int dat;
+    unsigned int drv[2];
+    unsigned int pull[2];
+};
+
+/* gpio interrupt control */
+struct sunxi_gpio_int {
+    unsigned int cfg[3];
+    unsigned int ctl;
+    unsigned int sta;
+    unsigned int deb;
+};
+
+struct sunxi_gpio_reg {
+    struct sunxi_gpio gpio_bank[9];
+    unsigned char res[0xbc];
+    struct sunxi_gpio_int gpio_int;
+};
+
+#define GPIO_BANK(pin)	((pin) >> 5)
+#define GPIO_NUM(pin)	((pin) & 0x1F)
+
+#define GPIO_CFG_INDEX(pin)	(((pin) & 0x1F) >> 3)
+#define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1F) & 0x7) << 2)
+
+#define GPIO_PULL_INDEX(pin)	(((pin) & 0x1F) >> 4)
+#define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1F) & 0xf) << 1)
+
+
+/* GPIO bank sizes */
+#define SUNXI_GPIO_A_NR		(32)
+#define SUNXI_GPIO_B_NR		(32)
+#define SUNXI_GPIO_C_NR		(32)
+#define SUNXI_GPIO_D_NR		(32)
+#define SUNXI_GPIO_E_NR		(32)
+#define SUNXI_GPIO_F_NR		(32)
+#define SUNXI_GPIO_G_NR		(32)
+#define SUNXI_GPIO_H_NR		(32)
+#define SUNXI_GPIO_I_NR		(32)
+
+#define SUNXI_GPIO_NEXT(__gpio) ((__gpio##_START)+(__gpio##_NR)+0)
+
+enum sunxi_gpio_number {
+    SUNXI_GPIO_A_START = 0,
+    SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),	//32
+    SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),	//64
+    SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),	//96
+    SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),	//128
+    SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),	//160
+    SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),	//192
+    SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),	//224
+    SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H)	//256
+};
+
+/* SUNXI GPIO number definitions */
+#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
+#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
+#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
+#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
+#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
+#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
+#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
+#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
+#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
+
+/* GPIO pin function config */
+
+#define SUNXI_GPIO_INPUT (0)
+#define SUNXI_GPIO_OUTPUT (1)
+#define SUNXI_GPIO_PER (2)
+
+#define SUNXI_GPA0_ERXD3 (2)
+#define SUNXI_GPA0_SPI1_CS0 (3)
+#define SUNXI_GPA0_UART2_RTS (4)
+
+#define SUNXI_GPA1_ERXD2 (2)
+#define SUNXI_GPA1_SPI1_CLK	(3)
+#define SUNXI_GPA1_UART2_CTS	(4)
+
+#define SUNXI_GPA2_ERXD1	(2)
+#define SUNXI_GPA2_SPI1_MOSI	(3)
+#define SUNXI_GPA2_UART2_TX	(4)
+
+#define SUNXI_GPA10_UART1_TX	(4)
+#define SUNXI_GPA11_UART1_RX	(4)
+
+#define SUN4I_GPB22_UART0_TX	(2)
+#define SUN4I_GPB23_UART0_RX	(2)
+
+#define SUN5I_GPG3_UART0_TX	(4)
+#define SUN5I_GPG4_UART0_RX	(4)
+
+#define SUNXI_GPC2_NCLE	(2)
+#define SUNXI_GPC2_SPI0_CLK	(3)
+
+#define SUNXI_GPC6_NRB0	(2)
+#define SUNXI_GPC6_SDC2_CMD	(3)
+
+#define SUNXI_GPC7_NRB1	(2)
+#define SUNXI_GPC7_SDC2_CLK	(3)
+
+#define SUNXI_GPC8_NDQ0	(2)
+#define SUNXI_GPC8_SDC2_D0	(3)
+
+#define SUNXI_GPC9_NDQ1	(2)
+#define SUNXI_GPC9_SDC2_D1	(3)
+
+#define SUNXI_GPC10_NDQ2	(2)
+#define SUNXI_GPC10_SDC2_D2	(3)
+
+#define SUNXI_GPC11_NDQ3	(2)
+#define SUNXI_GPC11_SDC2_D3	(3)
+
+#define SUNXI_GPF2_SDC0_CLK	(2)
+#define SUNXI_GPF2_UART0_TX	(4)
+
+#define SUNXI_GPF4_SDC0_D3	(2)
+#define SUNXI_GPF4_UART0_RX	(4)
+
+extern int sunxi_gpio_input(unsigned int pin);
+extern int sunxi_gpio_init(void);
+extern int sunxi_gpio_set_cfgpin(unsigned int pin, unsigned int val);
+extern int sunxi_gpio_get_cfgpin(unsigned int pin);
+extern int sunxi_gpio_output(unsigned int pin, unsigned int val);
+extern void sunxi_gpio_cleanup(void);
+extern int sunxi_gpio_set_pull(unsigned int pin, unsigned int val);
+extern unsigned int SUNXI_PIO_BASE;
+#endif