scs 0.2.0

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Files changed (106) hide show
  1. checksums.yaml +7 -0
  2. data/CHANGELOG.md +3 -0
  3. data/LICENSE.txt +22 -0
  4. data/README.md +84 -0
  5. data/ext/scs/Rakefile +11 -0
  6. data/lib/scs/ffi.rb +117 -0
  7. data/lib/scs/solver.rb +178 -0
  8. data/lib/scs/version.rb +3 -0
  9. data/lib/scs.rb +17 -0
  10. data/vendor/scs/LICENSE.txt +21 -0
  11. data/vendor/scs/Makefile +164 -0
  12. data/vendor/scs/README.md +220 -0
  13. data/vendor/scs/include/aa.h +56 -0
  14. data/vendor/scs/include/cones.h +46 -0
  15. data/vendor/scs/include/ctrlc.h +33 -0
  16. data/vendor/scs/include/glbopts.h +177 -0
  17. data/vendor/scs/include/linalg.h +26 -0
  18. data/vendor/scs/include/linsys.h +64 -0
  19. data/vendor/scs/include/normalize.h +18 -0
  20. data/vendor/scs/include/rw.h +17 -0
  21. data/vendor/scs/include/scs.h +161 -0
  22. data/vendor/scs/include/scs_blas.h +51 -0
  23. data/vendor/scs/include/util.h +65 -0
  24. data/vendor/scs/linsys/amatrix.c +305 -0
  25. data/vendor/scs/linsys/amatrix.h +36 -0
  26. data/vendor/scs/linsys/amatrix.o +0 -0
  27. data/vendor/scs/linsys/cpu/direct/private.c +366 -0
  28. data/vendor/scs/linsys/cpu/direct/private.h +26 -0
  29. data/vendor/scs/linsys/cpu/direct/private.o +0 -0
  30. data/vendor/scs/linsys/cpu/indirect/private.c +256 -0
  31. data/vendor/scs/linsys/cpu/indirect/private.h +31 -0
  32. data/vendor/scs/linsys/cpu/indirect/private.o +0 -0
  33. data/vendor/scs/linsys/external/amd/LICENSE.txt +934 -0
  34. data/vendor/scs/linsys/external/amd/SuiteSparse_config.c +469 -0
  35. data/vendor/scs/linsys/external/amd/SuiteSparse_config.h +254 -0
  36. data/vendor/scs/linsys/external/amd/SuiteSparse_config.o +0 -0
  37. data/vendor/scs/linsys/external/amd/amd.h +400 -0
  38. data/vendor/scs/linsys/external/amd/amd_1.c +180 -0
  39. data/vendor/scs/linsys/external/amd/amd_1.o +0 -0
  40. data/vendor/scs/linsys/external/amd/amd_2.c +1842 -0
  41. data/vendor/scs/linsys/external/amd/amd_2.o +0 -0
  42. data/vendor/scs/linsys/external/amd/amd_aat.c +184 -0
  43. data/vendor/scs/linsys/external/amd/amd_aat.o +0 -0
  44. data/vendor/scs/linsys/external/amd/amd_control.c +64 -0
  45. data/vendor/scs/linsys/external/amd/amd_control.o +0 -0
  46. data/vendor/scs/linsys/external/amd/amd_defaults.c +37 -0
  47. data/vendor/scs/linsys/external/amd/amd_defaults.o +0 -0
  48. data/vendor/scs/linsys/external/amd/amd_dump.c +179 -0
  49. data/vendor/scs/linsys/external/amd/amd_dump.o +0 -0
  50. data/vendor/scs/linsys/external/amd/amd_global.c +16 -0
  51. data/vendor/scs/linsys/external/amd/amd_global.o +0 -0
  52. data/vendor/scs/linsys/external/amd/amd_info.c +119 -0
  53. data/vendor/scs/linsys/external/amd/amd_info.o +0 -0
  54. data/vendor/scs/linsys/external/amd/amd_internal.h +304 -0
  55. data/vendor/scs/linsys/external/amd/amd_order.c +199 -0
  56. data/vendor/scs/linsys/external/amd/amd_order.o +0 -0
  57. data/vendor/scs/linsys/external/amd/amd_post_tree.c +120 -0
  58. data/vendor/scs/linsys/external/amd/amd_post_tree.o +0 -0
  59. data/vendor/scs/linsys/external/amd/amd_postorder.c +206 -0
  60. data/vendor/scs/linsys/external/amd/amd_postorder.o +0 -0
  61. data/vendor/scs/linsys/external/amd/amd_preprocess.c +118 -0
  62. data/vendor/scs/linsys/external/amd/amd_preprocess.o +0 -0
  63. data/vendor/scs/linsys/external/amd/amd_valid.c +92 -0
  64. data/vendor/scs/linsys/external/amd/amd_valid.o +0 -0
  65. data/vendor/scs/linsys/external/amd/changes +11 -0
  66. data/vendor/scs/linsys/external/qdldl/LICENSE +201 -0
  67. data/vendor/scs/linsys/external/qdldl/README.md +120 -0
  68. data/vendor/scs/linsys/external/qdldl/changes +4 -0
  69. data/vendor/scs/linsys/external/qdldl/qdldl.c +298 -0
  70. data/vendor/scs/linsys/external/qdldl/qdldl.h +177 -0
  71. data/vendor/scs/linsys/external/qdldl/qdldl.o +0 -0
  72. data/vendor/scs/linsys/external/qdldl/qdldl_types.h +21 -0
  73. data/vendor/scs/linsys/gpu/gpu.c +41 -0
  74. data/vendor/scs/linsys/gpu/gpu.h +85 -0
  75. data/vendor/scs/linsys/gpu/indirect/private.c +304 -0
  76. data/vendor/scs/linsys/gpu/indirect/private.h +36 -0
  77. data/vendor/scs/scs.mk +181 -0
  78. data/vendor/scs/src/aa.c +224 -0
  79. data/vendor/scs/src/aa.o +0 -0
  80. data/vendor/scs/src/cones.c +802 -0
  81. data/vendor/scs/src/cones.o +0 -0
  82. data/vendor/scs/src/ctrlc.c +77 -0
  83. data/vendor/scs/src/ctrlc.o +0 -0
  84. data/vendor/scs/src/linalg.c +84 -0
  85. data/vendor/scs/src/linalg.o +0 -0
  86. data/vendor/scs/src/normalize.c +93 -0
  87. data/vendor/scs/src/normalize.o +0 -0
  88. data/vendor/scs/src/rw.c +167 -0
  89. data/vendor/scs/src/rw.o +0 -0
  90. data/vendor/scs/src/scs.c +975 -0
  91. data/vendor/scs/src/scs.o +0 -0
  92. data/vendor/scs/src/scs_version.c +5 -0
  93. data/vendor/scs/src/scs_version.o +0 -0
  94. data/vendor/scs/src/util.c +196 -0
  95. data/vendor/scs/src/util.o +0 -0
  96. data/vendor/scs/test/data/small_random_socp +0 -0
  97. data/vendor/scs/test/minunit.h +13 -0
  98. data/vendor/scs/test/problem_utils.h +93 -0
  99. data/vendor/scs/test/problems/rob_gauss_cov_est.h +85 -0
  100. data/vendor/scs/test/problems/small_lp.h +50 -0
  101. data/vendor/scs/test/problems/small_random_socp.h +33 -0
  102. data/vendor/scs/test/random_socp_prob.c +171 -0
  103. data/vendor/scs/test/run_from_file.c +69 -0
  104. data/vendor/scs/test/run_tests +2 -0
  105. data/vendor/scs/test/run_tests.c +32 -0
  106. metadata +203 -0
@@ -0,0 +1,180 @@
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+ /* ========================================================================= */
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+ /* === AMD_1 =============================================================== */
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+ /* ========================================================================= */
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+
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+ /* ------------------------------------------------------------------------- */
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+ /* AMD, Copyright (c) Timothy A. Davis, */
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+ /* Patrick R. Amestoy, and Iain S. Duff. See ../README.txt for License. */
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+ /* email: DrTimothyAldenDavis@gmail.com */
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+ /* ------------------------------------------------------------------------- */
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+
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+ /* AMD_1: Construct A+A' for a sparse matrix A and perform the AMD ordering.
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+ *
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+ * The n-by-n sparse matrix A can be unsymmetric. It is stored in MATLAB-style
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+ * compressed-column form, with sorted row indices in each column, and no
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+ * duplicate entries. Diagonal entries may be present, but they are ignored.
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+ * Row indices of column j of A are stored in Ai [Ap [j] ... Ap [j+1]-1].
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+ * Ap [0] must be zero, and nz = Ap [n] is the number of entries in A. The
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+ * size of the matrix, n, must be greater than or equal to zero.
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+ *
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+ * This routine must be preceded by a call to AMD_aat, which computes the
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+ * number of entries in each row/column in A+A', excluding the diagonal.
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+ * Len [j], on input, is the number of entries in row/column j of A+A'. This
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+ * routine constructs the matrix A+A' and then calls AMD_2. No error checking
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+ * is performed (this was done in AMD_valid).
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+ */
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+
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+ #include "amd_internal.h"
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+
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+ GLOBAL void AMD_1
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+ (
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+ Int n, /* n > 0 */
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+ const Int Ap [ ], /* input of size n+1, not modified */
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+ const Int Ai [ ], /* input of size nz = Ap [n], not modified */
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+ Int P [ ], /* size n output permutation */
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+ Int Pinv [ ], /* size n output inverse permutation */
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+ Int Len [ ], /* size n input, undefined on output */
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+ Int slen, /* slen >= sum (Len [0..n-1]) + 7n,
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+ * ideally slen = 1.2 * sum (Len) + 8n */
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+ Int S [ ], /* size slen workspace */
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+ scs_float Control [ ], /* input array of size AMD_CONTROL */
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+ scs_float Info [ ] /* output array of size AMD_INFO */
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+ )
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+ {
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+ Int i, j, k, p, pfree, iwlen, pj, p1, p2, pj2, *Iw, *Pe, *Nv, *Head,
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+ *Elen, *Degree, *s, *W, *Sp, *Tp ;
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+
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+ /* --------------------------------------------------------------------- */
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+ /* construct the matrix for AMD_2 */
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+ /* --------------------------------------------------------------------- */
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+
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+ ASSERT (n > 0) ;
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+
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+ iwlen = slen - 6*n ;
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+ s = S ;
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+ Pe = s ; s += n ;
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+ Nv = s ; s += n ;
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+ Head = s ; s += n ;
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+ Elen = s ; s += n ;
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+ Degree = s ; s += n ;
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+ W = s ; s += n ;
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+ Iw = s ; s += iwlen ;
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+
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+ ASSERT (AMD_valid (n, n, Ap, Ai) == AMD_OK) ;
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+
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+ /* construct the pointers for A+A' */
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+ Sp = Nv ; /* use Nv and W as workspace for Sp and Tp [ */
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+ Tp = W ;
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+ pfree = 0 ;
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+ for (j = 0 ; j < n ; j++)
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+ {
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+ Pe [j] = pfree ;
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+ Sp [j] = pfree ;
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+ pfree += Len [j] ;
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+ }
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+
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+ /* Note that this restriction on iwlen is slightly more restrictive than
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+ * what is strictly required in AMD_2. AMD_2 can operate with no elbow
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+ * room at all, but it will be very slow. For better performance, at
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+ * least size-n elbow room is enforced. */
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+ ASSERT (iwlen >= pfree + n) ;
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+
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+ #ifndef NDEBUG
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+ for (p = 0 ; p < iwlen ; p++) Iw [p] = EMPTY ;
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+ #endif
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+
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+ for (k = 0 ; k < n ; k++)
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+ {
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+ AMD_DEBUG1 (("Construct row/column k= "ID" of A+A'\n", k)) ;
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+ p1 = Ap [k] ;
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+ p2 = Ap [k+1] ;
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+
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+ /* construct A+A' */
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+ for (p = p1 ; p < p2 ; )
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+ {
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+ /* scan the upper triangular part of A */
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+ j = Ai [p] ;
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+ ASSERT (j >= 0 && j < n) ;
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+ if (j < k)
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+ {
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+ /* entry A (j,k) in the strictly upper triangular part */
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+ ASSERT (Sp [j] < (j == n-1 ? pfree : Pe [j+1])) ;
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+ ASSERT (Sp [k] < (k == n-1 ? pfree : Pe [k+1])) ;
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+ Iw [Sp [j]++] = k ;
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+ Iw [Sp [k]++] = j ;
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+ p++ ;
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+ }
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+ else if (j == k)
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+ {
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+ /* skip the diagonal */
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+ p++ ;
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+ break ;
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+ }
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+ else /* j > k */
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+ {
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+ /* first entry below the diagonal */
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+ break ;
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+ }
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+ /* scan lower triangular part of A, in column j until reaching
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+ * row k. Start where last scan left off. */
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+ ASSERT (Ap [j] <= Tp [j] && Tp [j] <= Ap [j+1]) ;
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+ pj2 = Ap [j+1] ;
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+ for (pj = Tp [j] ; pj < pj2 ; )
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+ {
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+ i = Ai [pj] ;
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+ ASSERT (i >= 0 && i < n) ;
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+ if (i < k)
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+ {
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+ /* A (i,j) is only in the lower part, not in upper */
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+ ASSERT (Sp [i] < (i == n-1 ? pfree : Pe [i+1])) ;
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+ ASSERT (Sp [j] < (j == n-1 ? pfree : Pe [j+1])) ;
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+ Iw [Sp [i]++] = j ;
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+ Iw [Sp [j]++] = i ;
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+ pj++ ;
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+ }
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+ else if (i == k)
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+ {
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+ /* entry A (k,j) in lower part and A (j,k) in upper */
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+ pj++ ;
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+ break ;
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+ }
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+ else /* i > k */
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+ {
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+ /* consider this entry later, when k advances to i */
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+ break ;
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+ }
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+ }
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+ Tp [j] = pj ;
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+ }
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+ Tp [k] = p ;
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+ }
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+
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+ /* clean up, for remaining mismatched entries */
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+ for (j = 0 ; j < n ; j++)
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+ {
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+ for (pj = Tp [j] ; pj < Ap [j+1] ; pj++)
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+ {
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+ i = Ai [pj] ;
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+ ASSERT (i >= 0 && i < n) ;
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+ /* A (i,j) is only in the lower part, not in upper */
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+ ASSERT (Sp [i] < (i == n-1 ? pfree : Pe [i+1])) ;
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+ ASSERT (Sp [j] < (j == n-1 ? pfree : Pe [j+1])) ;
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+ Iw [Sp [i]++] = j ;
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+ Iw [Sp [j]++] = i ;
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+ }
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+ }
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+
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+ #ifndef NDEBUG
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+ for (j = 0 ; j < n-1 ; j++) ASSERT (Sp [j] == Pe [j+1]) ;
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+ ASSERT (Sp [n-1] == pfree) ;
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+ #endif
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+
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+ /* Tp and Sp no longer needed ] */
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+
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+ /* --------------------------------------------------------------------- */
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+ /* order the matrix */
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+ /* --------------------------------------------------------------------- */
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+
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+ AMD_2 (n, Pe, Iw, Len, iwlen, pfree,
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+ Nv, Pinv, P, Head, Elen, Degree, W, Control, Info) ;
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+ }