ruby_rtl 0.0.1

data/lib/ruby_rtl/vhdl_generator.rb

@@ -0,0 +1,564 @@
+require_relative 'code'
+
+module RubyRTL
+
+  class VhdlGenerator < Visitor
+
+    attr_accessor :entity
+    attr_accessor :ios
+    attr_accessor :archi_elements
+
+    def generate circuit
+      puts "[+] VHDL code generation"
+
+      code=Code.new
+      @circuit=circuit
+      @ios,@archi_elements=[],[]
+      @sigs={}
+      @fsm_defs=[]
+      @sequentials=[]
+      @states={}
+      gen_ruby_rtl_type_package
+      root=circuit.ast
+      return unless root
+
+      gen_type_package()
+      #root.ios.each{|io| io.accept(self)}
+      @typedecls=root.decls.select{|decl| decl.is_a? TypeDecl}
+      non_typedecls=root.decls.reject{|decl| decl.is_a? TypeDecl}
+      non_typedecls.each{|decl| decl.accept(self)}
+
+      code << gen_ieee_header()
+      code << gen_ruby_rtl_package_call()
+      code << gen_package_call(circuit)
+      code << gen_entity(circuit)
+      code.newline
+      code << gen_archi(circuit)
+      code=clean_vhdl(code)
+      puts code.finalize
+      code.save_as "#{name=circuit.name.downcase}.vhd"
+    end
+
+    def clean_vhdl(code)
+      txt=code.finalize
+      txt.gsub! /;(\s*)\)/,")"
+      txt.gsub! /,(\s*)\)/,")"
+      (code=Code.new) << txt
+      return code
+    end
+
+    def gen_ruby_rtl_package_call
+      code=Code.new
+      code << "library ruby_rtl;"
+      code << "use ruby_rtl.ruby_rtl_package.all;"
+      code.newline
+      code
+    end
+
+    def gen_ruby_rtl_type_package
+      code=Code.new
+      code << gen_ieee_header
+      code << "package ruby_rtl_type_package is "
+      code.newline
+      code.indent=2
+      $typedefs.each do |name,definition|
+        case definition
+        when RecordType
+          code << definition_s=definition.accept(self,name)
+        else
+          definition_s=definition.accept(self)
+          case definition
+          when IntType,UIntType,BitType
+            header="sub"
+          else
+            header=""
+          end
+          code << "#{header}type #{name} is #{definition_s};"
+        end
+        code.newline
+      end
+      code.indent=0
+      code << "end package;"
+      code.save_as "ruby_rtl_type_package.vhd"
+    end
+
+    def gen_type_package
+      name=@circuit.name.downcase
+      return unless ast=@circuit.ast
+      typdecls=ast.decls.select{|decl| decl.is_a?(TypeDecl)}
+      package=Code.new
+      package << gen_ieee_header
+      package << "package #{name}_package is"
+      package.indent=2
+      package.newline
+      typdecls.each do |decl|
+        definition=decl.definition.accept(self,decl.name)
+        package << definition
+        package.newline
+      end
+      package.indent=0
+      package << "end package;"
+      puts package.finalize
+      package.save_as "#{name}_package.vhd"
+    end
+
+    def gen_ieee_header
+      header=Code.new
+      header << "-- automatically generated by RubyRTL"
+      header << "library ieee;"
+      header << "use ieee.std_logic_1164.all;"
+      header << "use ieee.numeric_std.all;"
+      header.newline
+      header
+    end
+
+    def gen_package_call circuit
+      name=circuit.name.downcase
+      code=Code.new
+      code << "library #{name}_lib;"
+      code << "use #{name}_lib.#{name}_package.all;"
+      code.newline
+      code
+    end
+
+    def gen_entity circuit
+      entity=Code.new
+      entity << "entity #{name=circuit.name.downcase}_c is"
+      entity.indent=2
+      entity << "port ("
+      entity.indent=4
+      if circuit.has_sequential_statements
+        entity << "reset_n : in std_logic;"
+        entity << "clk     : in std_logic;"
+      end
+      ios.each{|io| entity << io}
+      entity.indent=2
+      entity << ");"
+      entity.indent=0
+      entity << "end #{name}_c;"
+    end
+
+    def gen_archi circuit
+      body=circuit.ast.body
+      archi_elements=body.stmts.collect{|stmt| stmt.accept(self)}
+      archi=Code.new
+      archi << "architecture rtl of #{circuit.name.downcase}_c is"
+      archi.indent=2
+      @fsm_defs.each do |decl|
+        archi << decl
+      end
+      @typedecls.each do |typedecl|
+        archi << typedecl.accept(self)
+      end
+      @sigs.each do |sig,name|
+        archi << "signal #{name} : #{sig.type.accept(self)};"
+      end
+      archi.indent=0
+      archi << "begin"
+      archi.indent=2
+      archi.newline
+      archi_elements.each do |element|
+        archi << element
+        archi.newline
+      end
+      archi.indent=0
+      archi.newline
+      archi << "end rtl;"
+      archi
+    end
+
+    def visitComment comment,args=nil
+      "-- #{comment.str}"
+    end
+
+    def visitInput input,args=nil
+      name=@sigs[input] || input.name
+      adapt_name(name,args)
+    end
+
+    def visitOutput output,args=nil
+      name=@sigs[output] || output.name
+      adapt_name(name,args)
+    end
+
+    def visitSigDecl decl,args=nil
+      name=decl.name
+      name.sub!(/@/,'')
+      type=decl.sig.type.accept(self)
+      case decl.sig
+      when Input
+        ios << "#{name} : in  #{type};"
+      when Output
+        ios << "#{name} : out #{type};"
+      when Sig
+        @sigs.merge!(decl.sig => name)
+      else
+        raise "ERROR : visitSigDecl : neither input ou output"
+      end
+    end
+
+    def visitSig sig,args=nil
+      name=sig.name
+      adapt_name(name,args)
+    end
+
+    def adapt_name name,kind
+      name=name.to_s
+      case kind
+      when :comb
+        name+="_c"
+      when :reg
+        name+="_r"
+      when :var
+        name+="_v"
+      end
+      name
+    end
+
+    def visitTypeDecl decl,args=nil
+      definition=decl.definition.accept(self,decl.name)
+      "type #{decl.name} is #{definition};"
+    end
+
+    def visitEnumType enum_type,name
+      if name
+        "type #{name} is (#{enum_type.items.join(',')});"
+      else
+        idx=$typedefs.values.index(enum_type)
+        $typedefs.keys[idx]
+      end
+    end
+
+    def visitRecordType rectype,name
+      if name
+        code=Code.new
+        code << "record"
+        code.indent=2
+        rectype.hash.each do |name,type|
+          type_s=type.accept(self)
+          code << "#{name} : #{type_s};"
+        end
+        code.indent=0
+        code << "end record;"
+        code
+      else
+        idx=$typedefs.values.index(rectype)
+        $typedefs.keys[idx]
+      end
+    end
+
+    def visitMemoryType memtype,name
+      if name
+        range="0 to #{memtype.size-1}"
+        type=memtype.type.accept(self)
+        "array(#{range}) of #{type}"
+      else
+        idx=$typedefs.values.index(memtype)
+        $typedefs.keys[idx]
+      end
+    end
+    # ====== body stuff ========
+    # === statements ===
+    def visitAssign assign,args=nil
+      lhs=assign.lhs.accept(self)
+      rhs=assign.rhs.accept(self)
+      "#{lhs} <= #{rhs};"
+    end
+
+    def visitCompDecl comp_decl,args=nil
+      comp=comp_decl.comp
+      instance_name=comp_decl.name
+      sig_decls=comp.ast.decls.select{|node| node.is_a? SigDecl}
+      inputs =sig_decls.select{|decl| decl.sig.is_a? Input}.map(&:sig)
+      outputs=sig_decls.select{|decl| decl.sig.is_a? Output}.map(&:sig)
+
+      instanciation=Code.new
+      instanciation << "#{instance_name} : entity work.#{comp.name}_c"
+      instanciation.indent=2
+      instanciation << "port map("
+      instanciation.indent=4
+      inputs.each do |input|
+        actual_sig_name="#{instance_name}_#{input.name}"
+        @sigs.merge!({input => actual_sig_name})
+        instanciation << "#{input.name} => #{actual_sig_name},"
+      end
+      outputs.each do |output|
+        actual_sig_name="#{instance_name}_#{output.name}"
+        @sigs.merge!(output => actual_sig_name)
+        instanciation << "#{output.name} => #{actual_sig_name},"
+      end
+      instanciation.indent=2
+      instanciation << ");"
+      instanciation.indent=0
+      instanciation.newline
+      instanciation
+    end
+
+    def visitCombinatorial comb,args=nil
+      code=Code.new
+      label=comb.label
+      code << "#{label} : process(all) --VHDL'08"
+      code << "begin"
+      code.indent=2
+      code << comb.body.accept(self)
+      code.indent=0
+      code << "end process;"
+      code
+    end
+
+    def visitSequential sequential,args=nil
+      code=Code.new
+      label=sequential.label
+      code << "#{label} : process(clk)"
+      code << "begin"
+      code.indent=2
+      code << "if rising_edge(clk) then"
+      code.indent=4
+      code << sequential.body.accept(self)
+      code.indent=2
+      code << "end if;"
+      code.indent=0
+      code << "end process;"
+      code
+    end
+
+    # statement
+    def visitBody body,args=nil
+      code=Code.new
+      body.stmts.each{|stmt| code << stmt.accept(self)}
+      code
+    end
+
+    def visitIf if_,args=nil
+      cond=if_.cond.accept(self)
+      if_body=if_.body.accept(self)
+      code=Code.new
+      code << "if #{cond} then"
+      code.indent=2
+      code << if_body
+      code.indent=0
+      if_.elsifs.each{|elsif_|
+        code << elsif_.accept(self)
+      }
+      code << if_.else.accept(self) if if_.else
+      code << "end if;"
+      code
+    end
+
+    def visitElsif elsif_,args=nil
+      cond=elsif_.cond.accept(self)
+      body=elsif_.body.accept(self)
+      code=Code.new
+      code << "elsif #{cond} then"
+      code.indent=2
+      code << body
+      code.indent=0
+      code
+    end
+
+    def visitElse else_,args=nil
+      body=else_.body.accept(self)
+      code=Code.new
+      code << "else "
+      code.indent=2
+      code << body
+      code.indent=0
+      code
+    end
+    # case / switch
+    def visitCase case_,args=nil
+      cond=case_.cond.accept(self)
+      code=Code.new
+      code << "case #{cond} is"
+      code.indent=2
+      code << case_.body.accept(self)
+      code.indent=0
+      code << "end case;"
+      code
+    end
+
+    def visitWhen when_,args=nil
+      unless (value=when_.value).is_a? Symbol
+        value=when_.value.accept(self)
+      end
+      code=Code.new
+      code << "when #{value} =>"
+      code.indent=2
+      code << when_.body.accept(self)
+      code.indent=0
+      code
+    end
+
+    # === FSM ===
+    def visitFsm fsm,args=nil
+      @fsm=fsm
+      state_names=fsm.states.map{|state| state.name}.join(",")
+      @fsm_defs << "type #{fsm.name}_state_t is (#{state_names});"
+      @fsm_defs << "signal #{fsm.name}_state : #{fsm.name}_state_t;"
+      body=Code.new
+      body << "#{fsm.name}_update : process(reset_n,clk)"
+      body << "begin"
+      body.indent=2
+      body << "if reset_n='0' then"
+      body.indent=4
+      body << "#{fsm.name}_state <= #{fsm.states.first.name};"
+      fsm.assignments.each do |assign|
+        lhs=assign.lhs.accept(self)
+        rhs=default_init(assign.lhs.type)
+        body << "#{lhs} <= #{rhs};"
+      end
+      body.indent=2
+      body << "elsif rising_edge(clk) then"
+      body.indent=4
+      body << "if sreset='1' then"
+      body.indent=6
+      body << "#{fsm.name}_state <= #{fsm.states.first.name};"
+      fsm.assignments.each do |assign|
+        lhs=assign.lhs.accept(self)
+        rhs=default_init(assign.lhs.type)
+        body << "#{lhs} <= #{rhs};"
+      end
+      body.indent=4
+      body << "else "
+      body.indent=6
+      body << state_cases(fsm)
+      body.indent=4
+      body << "end if;"
+      body.indent=2
+      body << "end if;"
+      body.indent=0
+      body << "end process;"
+      body
+    end
+
+    def state_cases fsm
+      code=Code.new
+      code << "case #{fsm.name}_state is"
+      code.indent=2
+      fsm.states.each do |state|
+        code << "when #{state.name} =>"
+        code.indent=4
+        code << state_body(state)
+        code.indent=2
+      end
+      code << "when others =>"
+      code << "  null;"
+      code.indent=0
+      code << "end case;"
+      code
+    end
+
+    def state_body state
+      code=Code.new
+      state.body.each{|stmt| code << stmt.accept(self)}
+      code
+    end
+
+    def visitState state,args=nil
+      code << "when #{state.name}"
+      code
+    end
+
+    def visitNext next_state,args=nil
+      "#{@fsm.name}_state <= #{next_state.name};"
+    end
+
+    # === expressions ===
+    VHDL_OP={
+      "&" => "and",
+      "|" => "or",
+      "^" => "xor",
+      "=="=> "=",
+      "%" => "mod",
+      "!=" => "/="
+    }
+    def visitBinary bin,args=nil
+      lhs=bin.lhs.accept(self)
+      op=VHDL_OP[bin.op] || bin.op
+      rhs=bin.rhs.accept(self)
+      "(#{lhs} #{op} #{rhs})"
+    end
+
+    def visitFuncCall func,args=nil
+      name=func.name
+      argus=func.args.map{|arg| arg.accept(self)}.join(',')
+      "#{name}(#{argus})"
+    end
+
+    def visitIndexed indexed,args=nil
+      lhs=indexed.lhs.accept(self)
+      rhs=indexed.rhs.accept(self)
+      case indexed.rhs
+      when RUIntLit
+      else
+        conv_int_start="to_integer("
+        conv_int_end  =")"
+      end
+      puts indexed.rhs
+      "#{lhs}(#{conv_int_start}#{rhs}#{conv_int_end})"
+    end
+
+    # === types
+    def visitBitType bit,args=nil
+      "std_logic"
+    end
+
+    def visitBitVectorType bv,args=nil
+      range="#{bv.bitwidth-1} downto 0"
+      "std_logic_vector(#{range})"
+    end
+
+    def visitUIntType uint,args=nil
+      range="#{uint.bitwidth-1} downto 0"
+      "unsigned(#{range})"
+    end
+
+    def visitIntType int,args=nil
+      range="#{int.bitwidth-1} downto 0"
+      "signed(#{range})"
+    end
+
+
+
+    def default_init type
+      case type
+      when BitType
+        return "'0'"
+      when BitVectorType
+        return "(others=>'0')"
+      when UintType
+        return "to_unsigned(0,#{type.bitwidth})"
+      when IntType
+        return "to_signed(0,#{type.bitwidth})"
+      else
+        raise "Cannot provide default init value for type #{type}"
+      end
+      ret
+    end
+
+    # === literals
+    def visitIntLit int,args=nil
+      "to_signed(#{int.val},#{int.type.bitwidth})"
+    end
+
+    def visitUIntLit uint,args=nil
+      "to_unsigned(#{uint.val},#{uint.type.bitwidth})"
+    end
+
+    def visitBitLit bit_lit,args=nil
+      "'#{bit_lit.val}'"
+    end
+
+    def visitBitVectorLit bit_lit,args=nil
+      "\"#{bit_lit.val}\""
+    end
+
+    def visitRIntLit lit,args=nil
+      lit.val
+    end
+
+    def visitRUIntLit lit,args=nil
+      lit.val
+    end
+  end
+end

data/lib/ruby_rtl/visitor.rb

@@ -0,0 +1,163 @@
+
+module RubyRTL
+  class Visitor
+
+    def visit circuit
+      circuit.ast.each{|node| node.accept(self)}
+    end
+
+    def visitComment node,args=nil
+    end
+
+    def visitSig node,args=nil
+    end
+
+    def visitPort node,args=nil
+    end
+
+    def visitInput node,args=nil
+    end
+
+    def visitOutput node,args=nil
+    end
+
+    def visitTypeDecl node,args=nil
+    end
+
+    def visitSigDecl node,args=nil
+    end
+
+    def visitCompDecl node,args=nil
+    end
+
+    def visitCircuitPart node,args=nil
+    end
+
+    def visitCombinatorial comb,args=nil
+      puts comb.body.class
+      comb.body.accept(self)
+    end
+
+    def visitSequential seq,args=nil
+      puts seq.body.class
+      seq.body.accept(self)
+    end
+
+    # === statements
+    def visitBody body,args=nil
+      body.each{|stmt| stmt.accept(self,args)}
+    end
+
+    def visitAssign node,args=nil
+      node.lhs.accept(self)
+      node.rhs.accept(self)
+    end
+
+    def visitIf node,args=nil
+      node.cond.accept(self)
+      node.body.accept(self)
+      node.elsifs.each{|elsif_| elsif_.accept(self)}
+      node.else.accept(self) if node.else
+    end
+
+    def visitElse else_,args=nil
+      else_.body.accept(self)
+    end
+
+    def visitElsif elsif_,args=nil
+      elsif_.cond.accept(self)
+      elsif_.body.accept(self)
+    end
+
+    def visitCase case_,args=nil
+      case_.cond.accept(self)
+      case_.body.accept(self)
+    end
+
+    def visitWhen when_,args=nil
+      when_.value.accept(self) unless when_.value.is_a?(Symbol)
+      when_.body.accept(self)
+    end
+
+    # === fsm
+    def visitFsm fsm,args=nil
+      fsm.body.accept(self)
+    end
+
+    def visitState state,args=nil
+      state.body.accept(self)
+    end
+
+    def visitNext node,args=nil
+    end
+
+    # === expr ===
+    def visitBinary node,args=nil
+      node.lhs.accept(self)
+      node.rhs.accept(self)
+    end
+
+    def visitUnary node,args=nil
+      node.expr.accept(self)
+    end
+
+    def visitIndexed indexed,args=nil
+      lhs=indexed.lhs.accept(self)
+      rhs=indexed.rhs.accept(self)
+    end
+    # === literals ===
+    def visitLiteral node,args=nil
+      node
+    end
+
+    def visitBitLit node,args=nil
+      node
+    end
+
+    def visitIntLit lit,args=nil
+      lit
+    end
+
+    def visitUIntLit lit,args=nil
+      lit
+    end
+
+    def visitRIntLit lit,args=nil
+      lit
+    end
+
+    def visitRUIntLit lit,args=nil
+      lit
+    end
+    # === types ===
+    def visitInteger int,args=nil
+      int
+    end
+
+    def visitType node,args=nil
+    end
+
+    def visitBitType node,args=nil
+    end
+
+    def visitBitVectorType node,args=nil
+    end
+
+    def visitIntType node,args=nil
+    end
+
+
+    def visitUIntType node,args=nil
+    end
+
+    def visitRIntType node,args=nil
+    end
+
+    def visitRUintType node,args=nil
+    end
+
+    def visitRecordType node,args=nil
+    end
+
+  end
+end

data/lib/ruby_rtl.rb

@@ -0,0 +1,5 @@
+require_relative "ruby_rtl/ast"
+require_relative "ruby_rtl/dsl"
+require_relative "ruby_rtl/compiler"
+require_relative "ruby_rtl/visitor"
+require_relative "ruby_rtl/vhdl_generator"