ruby-vpi 13.0.0 → 14.0.0

data/Rakefile

@@ -164,7 +164,12 @@ end
 desc 'Generate release announcement.'
 task :ann => 'doc/history.rb' do |t|
   require t.prerequisites[0]
-  text = format_history_entry @history.first
+  text = [
+    PROJECT_DETAIL,
+    "* " + PROJECT_URL,
+    "---",
+    format_history_entry(@history.first)
+  ].join "\n\n"
 
   require 'doc/lib/doc_format'
   html = text.redcloth

data/bin/generate_test_tpl/bench.rb

@@ -1,6 +1,89 @@
+<%
+  clock = aOutputInfo.designClassName + '.' + aModuleInfo.ports.first.name
+%>
 # This file is the Ruby side of the bench.
 
 require 'rubygems'
 require 'ruby-vpi'
 
-RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %>
+RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %> do
+  ##
+  # This block is executed whenever Vpi::simulate is invoked.
+  #
+  # It simulates the design under test. This is typically done
+  # by toggling the clock signal, as demonstrated below.
+  ##
+
+  ##
+  # We are currently here (marked by the ! signs):
+  #
+  #    !
+  #    !
+  #    ! ____      ____      ____      ____
+  # ___!/    \____/    \____/    \____/    \
+  #    !
+  #    !
+  #
+  ##
+
+  <%= clock %>.intVal = 1
+
+  ##
+  # After setting the clock signal to high, we are here:
+  #
+  #      !
+  #      !
+  #      !____      ____      ____      ____
+  # ____/!    \____/    \____/    \____/    \
+  #      !
+  #      !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #          !
+  #          !
+  #      ____!      ____      ____      ____
+  # ____/    !\____/    \____/    \____/    \
+  #          !
+  #          !
+  #
+  ##
+
+  <%= clock %>.intVal = 0
+
+  ##
+  # After setting the clock signal to low, we are here:
+  #
+  #           !
+  #           !
+  #      ____ !     ____      ____      ____
+  # ____/    \!____/    \____/    \____/    \
+  #           !
+  #           !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #
+  #               !
+  #               !
+  #      ____     ! ____      ____      ____
+  # ____/    \____!/    \____/    \____/    \
+  #               !
+  #               !
+  #
+  ##
+
+  ##
+  # This process repeats when Vpi::simulate is invoked again.
+  ##
+end

data/bin/generate_test_tpl/bench.v

@@ -5,31 +5,22 @@
       ".#{param.name}(#{param.name})"
     end.join(', ')
   end
-
-  clockSignal = aModuleInfo.ports.first.name
 %>
 // This file is the Verilog side of the bench.
 module <%= aOutputInfo.verilogBenchName %>;
-
-  // instantiate the design under test
 <% aModuleInfo.parameters.each do |param| %>
-    parameter <%= param.decl %>;
+  parameter <%= param.decl %>;
 <% end %>
 <% aModuleInfo.ports.each do |port| %>
-    <%= port.input? ? 'reg' : 'wire' %> <%= port.size %> <%= port.name %>;
+  <%= port.input? ? 'reg' : 'wire' %> <%= port.size %> <%= port.name %>;
 <% end %>
 
-    <%= aModuleInfo.name %> <%
-      instConfigDecl = make_inst_param_decl(aModuleInfo.parameters)
-
-      unless instConfigDecl.empty?
-      %>#(<%= instConfigDecl %>)<%
-      end
-
-    %> <%= aOutputInfo.verilogBenchName %>_design(<%= make_inst_param_decl(aModuleInfo.ports) %>);
+  <%= aModuleInfo.name %> <%
+    instConfigDecl = make_inst_param_decl(aModuleInfo.parameters)
 
-  // generate clock for the design under test
-    initial <%= clockSignal %> = 0;
-    always #5 <%= clockSignal %> = !<%= clockSignal %>;
+    unless instConfigDecl.empty?
+    %>#(<%= instConfigDecl %>)<%
+    end
 
+  %> <%= aOutputInfo.verilogBenchName %>_design(<%= make_inst_param_decl(aModuleInfo.ports) %>);
 endmodule

data/bin/generate_test_tpl/proto.rb

@@ -1,6 +1,6 @@
 # This is a prototype of the design under test.
 
-# When prototyping is enabled, relay_verilog invokes this method
+# When prototyping is enabled, Vpi::simulate invokes this method
 # instead of transferring control to the Verilog simulator.
 def <%= aOutputInfo.designClassName %>.simulate!
   # discard old outputs

data/doc/common.css

@@ -1,9 +1,8 @@
 body {
   font-family: sans-serif;
 
-  margin-left: 275px;
-  margin-right: 50px;
-  margin-bottom: 5em;
+  margin: 1em;
+  margin-left: 30%;
   max-width: 600px;
 }
 
@@ -16,26 +15,7 @@ th, h1, h2, h3, h4, h5, h6, .title {
 
 h1, h2, h3, h4, h5, h6 {
   margin-top: 3em;
-  padding: 0.5em;
-}
-
-h1, h2, h3 {
-  text-align: center;
-  -moz-border-radius: 1em;
-  border-radius: 1em;
-}
-
-h1 {
-  padding: 1em;
-  background-color: mistyrose;
-}
-
-h2 {
-  background-color: bisque;
-}
-
-h3 {
-  background-color: oldlace;
+  border-bottom: thin solid silver;
 }
 
 
@@ -47,19 +27,17 @@ h3 {
   top: 0px;
   bottom: 0px;
 
-  max-width: 200px;
+  max-width: 25%;
   padding: 1em;
   overflow: auto;
-
-  background-color: white;
 }
 
 #navigation h1, #navigation h2, #navigation h3, #navigation h4, #navigation h5, #navigation h6 {
   font-size: smaller;
 }
 
-#navigation li {
-  margin-left: -1.25em;
+#navigation ul {
+  margin-left: -1.75em;
 }
 
 
@@ -69,7 +47,10 @@ h3 {
   border: thin solid steelblue;
   background-color: aliceblue;
   padding: 1em;
-  padding-top: 0px;
+  margin-bottom: 1em;
+  margin-top: 1em;
+
+  min-height: 170px;
 }
 
 .admonition img {
@@ -80,8 +61,7 @@ h3 {
 /* source code */
 
 tt {
-  font-weight: bold;
-  background-color: lemonchiffon;
+  background-color: #cfc;
 }
 
 pre, blockquote .code {
@@ -144,10 +124,6 @@ th {
 
 /* misc. */
 
-.cover-page {
-  text-align: center;
-}
-
 a img {
   border: none;
 }
@@ -156,9 +132,6 @@ em, strong {
   font-family: serif;
 }
 
-
-  /* extra spacing before big block elements */
-
-  .admonition, .figure {
-    margin-top: 3em;
-  }
+.formal .title {
+  margin-top: 3em;
+}

data/doc/common.tpl

@@ -24,7 +24,7 @@
       <h1>Contents</h1>
       <%=
         @headings.map do |h|
-          %{#{'*' * h.depth} "#{h.title}":##{h.anchor}}
+          %{#{'*' * h.depth} #{h.index} "#{h.title}":##{h.anchor}}
         end.join("\n").redcloth
       %>