ruby-vpi 13.0.0 → 14.0.0

data/samp/counter/counter_xunit_bench.v

@@ -1,16 +1,9 @@
 // This file is the Verilog side of the bench.
 module counter_xunit_bench;
+  parameter Size = 5;
+  reg  clock;
+  reg  reset;
+  wire [Size - 1 : 0] count;
 
-  // instantiate the design under test
-    parameter Size = 5;
-    reg  clock;
-    reg  reset;
-    wire [Size - 1 : 0] count;
-
-    counter #(.Size(Size)) counter_xunit_bench_design(.clock(clock), .reset(reset), .count(count));
-
-  // generate clock for the design under test
-    initial clock = 0;
-    always #5 clock = !clock;
-
+  counter #(.Size(Size)) counter_xunit_bench_design(.clock(clock), .reset(reset), .count(count));
 endmodule

data/samp/counter/counter_xunit_design.rb

@@ -2,8 +2,7 @@
 
 # This method resets the design under test.
 def Counter.reset!
-  # assert the reset signal for two clock cycles
   reset.intVal = 1
-  2.times {relay_verilog}
+  simulate
   reset.intVal = 0
 end

data/samp/counter/counter_xunit_proto.rb

@@ -1,6 +1,6 @@
 # This is a prototype of the design under test.
 
-# When prototyping is enabled, relay_verilog invokes this method
+# When prototyping is enabled, Vpi::simulate invokes this method
 # instead of transferring control to the Verilog simulator.
 def Counter.simulate!
   if reset.intVal == 1

data/samp/counter/counter_xunit_spec.rb

@@ -18,7 +18,7 @@ class ResettedCounterValue < Test::Unit::TestCase
   def test_increment
     LIMIT.times do |i|
       assert_equal i, Counter.count.intVal
-      relay_verilog # increment the counter
+      simulate # increment the counter
     end
   end
 end
@@ -28,12 +28,12 @@ class MaximumCounterValue < Test::Unit::TestCase
     Counter.reset!
 
     # increment the counter to maximum value
-    MAX.times {relay_verilog}
+    MAX.times {simulate}
     assert_equal MAX, Counter.count.intVal
   end
 
   def test_overflow
-    relay_verilog # increment the counter
+    simulate # increment the counter
     assert_equal 0, Counter.count.intVal
   end
 end

data/samp/pipelined_alu/hw5_unit_test_bench.rb

@@ -3,4 +3,84 @@
 require 'rubygems'
 require 'ruby-vpi'
 
-RubyVpi.init_bench :Hw5_unit, :xUnit
+RubyVpi.init_bench :Hw5_unit, :xUnit do
+  ##
+  # This block is executed whenever Vpi::simulate is invoked.
+  #
+  # It simulates the design under test by (typically) toggling
+  # the clock signal, as demonstrated below.
+  ##
+
+  ##
+  # We are currently here (marked by the ! signs):
+  #
+  #    !
+  #    !
+  #    ! ____      ____      ____      ____
+  # ___!/    \____/    \____/    \____/    \
+  #    !
+  #    !
+  #
+  ##
+
+  Hw5_unit.clk.intVal = 1
+
+  ##
+  # After setting the clock signal to high, we are here:
+  #
+  #      !
+  #      !
+  #      !____      ____      ____      ____
+  # ____/!    \____/    \____/    \____/    \
+  #      !
+  #      !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #          !
+  #          !
+  #      ____!      ____      ____      ____
+  # ____/    !\____/    \____/    \____/    \
+  #          !
+  #          !
+  #
+  ##
+
+  Hw5_unit.clk.intVal = 0
+
+  ##
+  # After setting the clock signal to low, we are here:
+  #
+  #           !
+  #           !
+  #      ____ !     ____      ____      ____
+  # ____/    \!____/    \____/    \____/    \
+  #           !
+  #           !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #
+  #               !
+  #               !
+  #      ____     ! ____      ____      ____
+  # ____/    \____!/    \____/    \____/    \
+  #               !
+  #               !
+  #
+  ##
+
+  ##
+  # This process repeats when Vpi::simulate is invoked again.
+  ##
+end

data/samp/pipelined_alu/hw5_unit_test_bench.v

@@ -1,21 +1,14 @@
 // This file is the Verilog side of the bench.
 module hw5_unit_test_bench;
-
-  // instantiate the design under test
-    reg  clk;
-    reg  reset;
-    reg [`DATABITS-1:0] in_databits;
-    reg [`WIDTH-1:0] a;
-    reg [`WIDTH-1:0] b;
-    reg [1:0] in_op;
-    wire [`WIDTH-1:0] res;
-    wire [`DATABITS-1:0] out_databits;
-    wire [1:0] out_op;
-
-    hw5_unit  hw5_unit_test_bench_design(.clk(clk), .reset(reset), .in_databits(in_databits), .a(a), .b(b), .in_op(in_op), .res(res), .out_databits(out_databits), .out_op(out_op));
-
-  // generate clock for the design under test
-    initial clk = 0;
-    always #5 clk = !clk;
-
+  reg  clk;
+  reg  reset;
+  reg [`DATABITS-1:0] in_databits;
+  reg [`WIDTH-1:0] a;
+  reg [`WIDTH-1:0] b;
+  reg [1:0] in_op;
+  wire [`WIDTH-1:0] res;
+  wire [`DATABITS-1:0] out_databits;
+  wire [1:0] out_op;
+
+  hw5_unit  hw5_unit_test_bench_design(.clk(clk), .reset(reset), .in_databits(in_databits), .a(a), .b(b), .in_op(in_op), .res(res), .out_databits(out_databits), .out_op(out_op));
 endmodule

data/samp/pipelined_alu/hw5_unit_test_design.rb

@@ -23,7 +23,7 @@ def Hw5_unit.reset!
   reset.intVal = 1
 
   RESET_DELAY.times do
-    relay_verilog
+    simulate
   end
 
   reset.intVal = 0

data/samp/pipelined_alu/hw5_unit_test_proto.rb

@@ -1,6 +1,6 @@
 # This is a prototype of the design under test.
 
-# When prototyping is enabled, relay_verilog invokes this method
+# When prototyping is enabled, Vpi::simulate invokes this method
 # instead of transferring control to the Verilog simulator.
 def Hw5_unit.simulate!
   raise NotImplementedError, "Prototype is not yet implemented."

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -60,7 +60,7 @@ class Hw5_unit_test_spec < Test::Unit::TestCase
           numIssued += 1
         end
 
-      relay_verilog
+      simulate
 
       # verify result of finished operation
         unless Hw5_unit.out_databits.x?

metadata

@@ -3,8 +3,8 @@ rubygems_version: 0.9.0
 specification_version: 1
 name: ruby-vpi
 version: !ruby/object:Gem::Version 
-  version: 13.0.0
-date: 2006-12-27 00:00:00 -08:00
+  version: 14.0.0
+date: 2006-12-30 00:00:00 -08:00
 summary: Ruby interface to IEEE 1364-2005 Verilog VPI
 require_paths: 
 - lib
@@ -53,7 +53,6 @@ files:
 - ext/relay.c
 - ext/Doxyfile
 - ext/vpi_user.h
-- ext/swig_vpi.h
 - ext/swig_wrap.cin
 - bin/generate_test.rb
 - bin/generate_test_tpl
@@ -97,7 +96,6 @@ files:
 - doc/readme.html
 - doc/rss.xml
 - doc/figures/figures.dia
-- doc/figures/ruby_init.png
 - doc/figures/ruby_relay.png
 - doc/figures/organization.png
 - doc/figures/organization_detailed.png
@@ -239,6 +237,7 @@ files:
 - ref/ruby/classes/ERB.src
 - ref/ruby/classes/FileUtils.src
 - ref/ruby/classes/RubyVpi.src
+- ref/ruby/classes/Vpi.src
 - ref/ruby/classes/Vpi
 - ref/ruby/classes/RDoc.src
 - ref/ruby/classes/VerilogParser.html
@@ -285,19 +284,23 @@ files:
 - ref/ruby/classes/FileUtils.src/M000027.html
 - ref/ruby/classes/FileUtils.src/M000028.html
 - ref/ruby/classes/RubyVpi.src/M000029.html
+- ref/ruby/classes/Vpi.src/M000030.html
+- ref/ruby/classes/Vpi.src/M000031.html
+- ref/ruby/classes/Vpi.src/M000032.html
+- ref/ruby/classes/Vpi.src/M000033.html
 - ref/ruby/classes/Vpi/Handle.src
 - ref/ruby/classes/Vpi/Handle.html
-- ref/ruby/classes/Vpi/Handle.src/M000030.html
-- ref/ruby/classes/Vpi/Handle.src/M000031.html
-- ref/ruby/classes/Vpi/Handle.src/M000032.html
-- ref/ruby/classes/Vpi/Handle.src/M000033.html
 - ref/ruby/classes/Vpi/Handle.src/M000034.html
 - ref/ruby/classes/Vpi/Handle.src/M000035.html
 - ref/ruby/classes/Vpi/Handle.src/M000036.html
 - ref/ruby/classes/Vpi/Handle.src/M000037.html
 - ref/ruby/classes/Vpi/Handle.src/M000038.html
+- ref/ruby/classes/Vpi/Handle.src/M000039.html
 - ref/ruby/classes/Vpi/Handle.src/M000040.html
-- ref/ruby/classes/RDoc.src/M000041.html
+- ref/ruby/classes/Vpi/Handle.src/M000041.html
+- ref/ruby/classes/Vpi/Handle.src/M000042.html
+- ref/ruby/classes/Vpi/Handle.src/M000044.html
+- ref/ruby/classes/RDoc.src/M000045.html
 - ref/ruby/classes/RubyVpi/Config.html
 test_files: []