ruby-vpi 12.1.0 → 13.0.0

data/bin/generate_test.rb

@@ -1,4 +1,3 @@
-#!/usr/bin/ruby -w
 # Generates Ruby-VPI tests from Verilog 2001 module declarations.
 # * The standard input stream is read if no input files are specified.
 # * The first input signal in a module's declaration is assumed to be the clocking signal.
@@ -39,12 +38,12 @@ require 'digest/md5'
 
 
 # Notify the user about some action being performed.
-def notify *args
+def notify *args # :nodoc:
   printf "%8s  %s\n", *args
 end
 
 # Writes the given contents to the file at the given path. If the given path already exists, then a backup is created before invoking the merging tool.
-def write_file aPath, aContent
+def write_file aPath, aContent # :nodoc:
   if File.exist? aPath
     oldDigest = Digest::MD5.digest(File.read(aPath))
     newDigest = Digest::MD5.digest(aContent)
@@ -72,7 +71,7 @@ end
 require 'ruby-vpi/erb'
 
 # Template used for generating output.
-class Template < ERB
+class Template < ERB # :nodoc:
   TEMPLATE_PATH = __FILE__.sub %r{\.rb$}, '_tpl'
 
   def initialize aName
@@ -83,7 +82,7 @@ end
 
 
 # Holds information about the output destinations of a parsed Verilog module.
-class OutputInfo
+class OutputInfo # :nodoc:
   RUBY_EXT = '.rb'
   VERILOG_EXT = '.v'
   RUNNER_EXT = '.rake'

data/bin/generate_test_tpl/bench.rb

@@ -1,4 +1,6 @@
 # This file is the Ruby side of the bench.
 
+require 'rubygems'
 require 'ruby-vpi'
+
 RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %>

data/bin/generate_test_tpl/bench.v

@@ -8,7 +8,7 @@
 
   clockSignal = aModuleInfo.ports.first.name
 %>
-/* This file is the Verilog side of the bench. */
+// This file is the Verilog side of the bench.
 module <%= aOutputInfo.verilogBenchName %>;
 
   // instantiate the design under test
@@ -28,15 +28,8 @@ module <%= aOutputInfo.verilogBenchName %>;
 
     %> <%= aOutputInfo.verilogBenchName %>_design(<%= make_inst_param_decl(aModuleInfo.ports) %>);
 
-  // connect to the Ruby side of this bench
-    initial begin
-      $ruby_init("ruby", "-rubygems", <%= aOutputInfo.rubyBenchPath.inspect %>);
-    end
-
-    always begin
-      #1 <%= clockSignal %> = 0;
-      #1 $ruby_relay;
-      #1 <%= clockSignal %> = 1;
-    end
+  // generate clock for the design under test
+    initial <%= clockSignal %> = 0;
+    always #5 <%= clockSignal %> = !<%= clockSignal %>;
 
 endmodule

data/bin/header_to_ruby.rb

@@ -1,4 +1,3 @@
-#!/usr/bin/ruby -w
 # Transforms Verilog header files into Ruby.
 # * The standard input stream is read if no input files are specified.
 # * Output is written to the standard output stream.