ruby-vpi 11.1.1 → 12.0.0
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- data/bin/generate_test.rb +12 -11
- data/bin/generate_test_tpl/bench.rb +0 -4
- data/bin/generate_test_tpl/bench.v +3 -6
- data/bin/generate_test_tpl/runner.rake +20 -4
- data/bin/generate_test_tpl/spec.rb +5 -7
- data/doc/common.css +110 -95
- data/doc/common.tpl +16 -17
- data/doc/history.html +350 -330
- data/doc/history.yml +49 -0
- data/doc/intro.inc +18 -4
- data/doc/lib/doc_proxy.rb +22 -32
- data/doc/manual.erb +90 -83
- data/doc/manual.html +298 -266
- data/doc/memo.html +31 -10
- data/doc/readme.html +26 -6
- data/ext/relay.c +24 -28
- data/ext/vlog.c +4 -15
- data/lib/ruby-vpi/rspec.rb +1 -1
- data/lib/ruby-vpi/runner.rb +12 -10
- data/lib/ruby-vpi/runner_proxy.rb +17 -6
- data/lib/ruby-vpi/verilog_parser.rb +11 -7
- data/lib/ruby-vpi/vpi.rb +11 -1
- data/lib/ruby-vpi.rb +4 -0
- data/ref/c/annotated.html +2 -2
- data/ref/c/common_8h.html +1 -1
- data/ref/c/files.html +1 -1
- data/ref/c/functions.html +1 -1
- data/ref/c/functions_vars.html +1 -1
- data/ref/c/globals.html +1 -1
- data/ref/c/globals_0x63.html +1 -1
- data/ref/c/globals_0x65.html +1 -1
- data/ref/c/globals_0x66.html +1 -1
- data/ref/c/globals_0x70.html +1 -1
- data/ref/c/globals_0x72.html +1 -1
- data/ref/c/globals_0x73.html +1 -1
- data/ref/c/globals_0x74.html +1 -1
- data/ref/c/globals_0x76.html +2 -2
- data/ref/c/globals_0x78.html +1 -1
- data/ref/c/globals_defs.html +1 -1
- data/ref/c/globals_defs_0x65.html +1 -1
- data/ref/c/globals_defs_0x70.html +1 -1
- data/ref/c/globals_defs_0x76.html +2 -2
- data/ref/c/globals_defs_0x78.html +1 -1
- data/ref/c/globals_enum.html +1 -1
- data/ref/c/globals_eval.html +1 -1
- data/ref/c/globals_func.html +2 -2
- data/ref/c/globals_type.html +1 -1
- data/ref/c/globals_vars.html +1 -1
- data/ref/c/index.html +1 -1
- data/ref/c/relay_8c.html +2 -1
- data/ref/c/relay_8h.html +1 -1
- data/ref/c/structrelay____RubyOptions____def.html +8 -2
- data/ref/c/structt__cb__data.html +1 -1
- data/ref/c/structt__vpi__delay.html +1 -1
- data/ref/c/structt__vpi__error__info.html +1 -1
- data/ref/c/structt__vpi__strengthval.html +1 -1
- data/ref/c/structt__vpi__systf__data.html +1 -1
- data/ref/c/structt__vpi__time.html +1 -1
- data/ref/c/structt__vpi__value.html +1 -1
- data/ref/c/structt__vpi__vecval.html +1 -1
- data/ref/c/structt__vpi__vlog__info.html +1 -1
- data/ref/c/swig_8c.html +1 -1
- data/ref/c/swig_8h.html +1 -1
- data/ref/c/verilog_8h.html +1 -1
- data/ref/c/vlog_8c.html +15 -15
- data/ref/c/vlog_8h.html +1 -1
- data/ref/c/vpi__user_8h.html +1 -1
- data/ref/ruby/classes/OutputInfo.html +1 -1
- data/ref/ruby/classes/OutputInfo.src/M000030.html +30 -30
- data/ref/ruby/classes/RDoc.html +5 -5
- data/ref/ruby/classes/RDoc.src/{M000097.html → M000099.html} +0 -0
- data/ref/ruby/classes/RubyVpi.src/M000085.html +43 -39
- data/ref/ruby/classes/String.src/M000033.html +26 -26
- data/ref/ruby/classes/String.src/M000034.html +4 -4
- data/ref/ruby/classes/Template.src/M000032.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Parameter.src/M000011.html +5 -5
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000007.html +7 -7
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000008.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000009.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000010.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module.src/M000006.html +15 -11
- data/ref/ruby/classes/Vpi/Handle/Property.html +5 -5
- data/ref/ruby/classes/Vpi/Handle/Property.src/{M000096.html → M000098.html} +61 -61
- data/ref/ruby/classes/Vpi/Handle.html +78 -43
- data/ref/ruby/classes/Vpi/Handle.src/M000088.html +3 -3
- data/ref/ruby/classes/Vpi/Handle.src/M000089.html +4 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000090.html +5 -31
- data/ref/ruby/classes/Vpi/Handle.src/M000091.html +9 -74
- data/ref/ruby/classes/Vpi/Handle.src/M000092.html +31 -17
- data/ref/ruby/classes/Vpi/Handle.src/M000093.html +74 -11
- data/ref/ruby/classes/Vpi/Handle.src/M000094.html +30 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000095.html +11 -55
- data/ref/ruby/classes/Vpi/Handle.src/M000097.html +68 -0
- data/ref/ruby/created.rid +1 -1
- data/ref/ruby/files/bin/generate_test_rb.html +8 -11
- data/ref/ruby/files/bin/generate_test_rb.src/M000001.html +4 -4
- data/ref/ruby/files/bin/generate_test_rb.src/M000002.html +22 -24
- data/ref/ruby/files/bin/header_to_ruby_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/float_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/integer_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rspec_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_proxy_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.html +2 -2
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.src/M000003.html +10 -10
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.src/M000004.html +12 -12
- data/ref/ruby/files/lib/ruby-vpi/verilog_parser_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/vpi_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi_rb.html +2 -1
- data/ref/ruby/fr_method_index.html +20 -18
- data/samp/counter/counter_rspec_bench.v +3 -6
- data/samp/counter/counter_rspec_design.rb +2 -1
- data/samp/counter/counter_rspec_runner.rake +20 -4
- data/samp/counter/counter_rspec_spec.rb +4 -4
- data/samp/counter/counter_xunit_bench.v +3 -6
- data/samp/counter/counter_xunit_design.rb +2 -1
- data/samp/counter/counter_xunit_runner.rake +20 -4
- data/samp/pipelined_alu/hw5_unit_test_bench.v +3 -6
- data/samp/pipelined_alu/hw5_unit_test_runner.rake +20 -4
- metadata +21 -20
- data/doc/manual.rb +0 -5
data/doc/memo.html
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<li><a href="#anchor3">Notes</a></li>
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<h1>Formals</h1>
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data/doc/readme.html
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<title>Welcome to Ruby-VPI</title>
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<ul>
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<li>Works with all <a href="manual.html#setup.reqs">major Verilog simulators</a> available today
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<li>Works with all <a href="manual.html#setup.reqs">major Verilog simulators</a> available today.
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<ul>
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<li>Compile <em>once</em> (during <a href="manual.html#setup.installation">installation</a>) and use forever!</li>
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<li>Enables <a href="http://
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<li>Enables <a href="http://agilemanifesto.org/">agile practices</a> such as
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<ul>
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<li><a href="http://www.testdriven.com">test-driven</a> development</li>
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<li><a href="http://behaviour-driven.org">behavior-driven</a> development</li>
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<li>Regular expressions</li>
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<li>Multi-threading</li>
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<li><a href="http://rubyforge.org"><em>ad
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<li><a href="http://rubyforge.org"><em>ad infinitum</em></a></li>
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<h3 id="intro.applications">Applications</h3>
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<p>Here is a modest sampling of tasks, paraphrased from <a href="http://embedded.eecs.berkeley.edu/Alumni/pinhong/scriptEDA/">Pin Hong</a>, that Ruby-VPI can be used to perform.</p>
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<ul>
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<li>Writing hardware models in Ruby</li>
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<li>Dumping/processing netlist data from Verilog database</li>
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<li>Dumping/processing simulation data</li>
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<li>Feeding dynamic simulation stimuli</li>
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<li>Back-annotating delay information</li>
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<li>Interactive logic simulation</li>
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<li>Building a distributed simulation</li>
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</ul>
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<h3 id="intro.appetizers">Appetizers</h3>
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<p>Here is a modest sampling to whet your appetite.</p>
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<p>Here is a modest sampling of code to whet your appetite.</p>
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data/ext/relay.c
CHANGED
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pthread_mutex_lock(&relay__rubyLock);
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}
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/**
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Stores command-line options for the Ruby interpreter.
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*/
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typedef struct {
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PLI_BYTE8** mArgs; /// Array of command-line arguments.
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unsigned int mCount; /// Number of command-line arguments.
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@note The structure will be freed *deeply* after use.
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*/
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void* ruby_run_handshake(void* apRubyOptions) {
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// initialize Ruby interpreter
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ruby_init();
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ruby_init_loadpath();
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swig_init();
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// pass command-line arguments to the interpreter
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relay__RubyOptions__def* pRubyOptions = (relay__RubyOptions__def*) apRubyOptions;
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PLI_BYTE8** argv = pRubyOptions->mArgs;
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ruby_options(argc, argv);
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// free the memory used by command-line options
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free(argv);
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free(pRubyOptions);
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// start Ruby interpreter
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ruby_run();
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// Ruby interpreter is now finished, so clean it up before terminating this thread
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return NULL;
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}
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pRubyOptions->mCount = 0;
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// transform the arguments passed to this function by Verilog into command-line arguments for Ruby interpeter
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if (vCall) {
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vpiHandle vCallArgs = vpi_iterate(vpiArgument, vCall);
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if (vCallArgs) {
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vpiHandle vArg;
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s_vpi_value argVal;
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argVal.format = vpiStringVal;
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vpiHandle vCall = vpi_handle(vpiSysTfCall, NULL);
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if (vCall) {
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vpiHandle vCallArgs = vpi_iterate(vpiArgument, vCall);
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if (vCallArgs) {
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vpiHandle vArg;
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s_vpi_value argVal;
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argVal.format = vpiStringVal;
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while (vArg = vpi_scan(vCallArgs)) {
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pRubyOptions->mCount++;
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// grow the options struct to hold more options
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if (pRubyOptions->mArgs == NULL)
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pRubyOptions->mArgs = malloc(sizeof(PLI_BYTE8*) * pRubyOptions->mCount);
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else
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pRubyOptions->mArgs = realloc(pRubyOptions->mArgs, sizeof(PLI_BYTE8*) * pRubyOptions->mCount);
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assert(pRubyOptions->mArgs != NULL);
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vpi_get_value(vArg, &argVal);
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pRubyOptions->mArgs[pRubyOptions->mCount - 1] = strdup(argVal.value.str);
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}
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}
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}
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}
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pthread_create(&relay__rubyThread, 0, ruby_run_handshake, pRubyOptions);
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return;
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data/ext/vlog.c
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#include <stdlib.h>
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verilog_tf_funcSig(vlog_ruby_relay) {
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// transfer control to ruby
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relay_ruby();
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// transfer control to verilog
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verilog_tf_funcReturn(0);
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}
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verilog_tf_funcSig(vlog_ruby_init) {
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// setup control transfer mechanism
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relay_init();
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// start ruby interpreter and transfer control to it
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relay_ruby_run();
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verilog_tf_funcReturn(0);
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}
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verilog_tf_funcSig(vlog_ruby_relay) {
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relay_ruby();
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verilog_tf_funcReturn(0);
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}
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data/lib/ruby-vpi/rspec.rb
CHANGED
data/lib/ruby-vpi/runner.rb
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# = Required variables
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# SIMULATOR_SOURCES:: Array of paths to source files needed by the simulator.
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# SIMULATOR_TARGET:: Name of the Verilog module to be simulated.
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#
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# SIMULATOR_ARGUMENTS:: A hash containing keys for each simulator task (same as Rakefile task names) and values containing command-line arguments for each simulator.
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=begin
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Copyright 2006 Suraj N. Kurapati
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raise ArgumentError, "All required variables must be defined." unless
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defined?(SIMULATOR_SOURCES) &&
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defined?(SIMULATOR_TARGET) &&
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defined?(
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defined?(SIMULATOR_ARGUMENTS)
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SIMULATOR_INCLUDES = [] unless defined? SIMULATOR_INCLUDES
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task :setup
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# resolve paths to sources by searching include directories
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SIMULATOR_SOURCES.map! do |src|
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unless File.exist? src
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task :cver do
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task :cver => :setup do
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task :ivl => :setup do
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|
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sh %w(vcs -R +v2k +vpi),
|
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task :vcs => :setup do
|
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sh %w(vcs -R +v2k +vpi), SIMULATOR_ARGUMENTS[:vcs], '-load', "#{object_file_path(:vcs)}:#{BOOTSTAP_FUNC}", expand_include_dir_options(:vcs), SIMULATOR_SOURCES
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task :vsim => :setup do
|
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sh 'vsim',
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|
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|
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|
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|
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|
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|
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|
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#
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|
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|
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unless ARGV.empty?
|
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|
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|
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|
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cd parent do
|
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sh 'rake', '-f', runner, *ARGV
|
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+
end
|
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|
+
end
|
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|
+
end
|
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|
+
end
|
@@ -52,13 +52,17 @@ class VerilogParser
|
|
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|
def initialize aDecl
|
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|
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|
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|
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|
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|
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@name, paramDecls, portDecls = $1, $
|
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|
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@decl =~ %r{module\s+(\w+)\s*(?:\#\((.*?)\))?\s*\((.*?)\)\s*;}m
|
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|
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@name, paramDecls, portDecls = $1, $2, $3
|
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|
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|
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|
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|
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|
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end
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|
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|
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CHANGED
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|
|
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|
}
|
50
50
|
end
|
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|
|
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|
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# Tests if the logic value of this handle is
|
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|
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# Tests if the logic value of this handle is unknown (x).
|
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|
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|
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|
self.hexStrVal =~ /x/i
|
55
55
|
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|
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|
|
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|
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def x!
|
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|
+
self.hexStrVal = 'x'
|
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|
+
end
|
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|
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|
# Tests if the logic value of this handle is high impedance (z).
|
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63
|
def z?
|
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|
self.hexStrVal =~ /z/i
|
60
65
|
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|
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|
|
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|
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# Sets the logic value of this handle to high impedance (z).
|
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def z!
|
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|
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self.hexStrVal = 'z'
|
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|
+
end
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
<h3><a class="anchor" name="index_e">- e -</a></h3><ul>
|
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|
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|
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|
|
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|
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|
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