ruby-vpi 11.1.1 → 12.0.0
Sign up to get free protection for your applications and to get access to all the features.
- data/bin/generate_test.rb +12 -11
- data/bin/generate_test_tpl/bench.rb +0 -4
- data/bin/generate_test_tpl/bench.v +3 -6
- data/bin/generate_test_tpl/runner.rake +20 -4
- data/bin/generate_test_tpl/spec.rb +5 -7
- data/doc/common.css +110 -95
- data/doc/common.tpl +16 -17
- data/doc/history.html +350 -330
- data/doc/history.yml +49 -0
- data/doc/intro.inc +18 -4
- data/doc/lib/doc_proxy.rb +22 -32
- data/doc/manual.erb +90 -83
- data/doc/manual.html +298 -266
- data/doc/memo.html +31 -10
- data/doc/readme.html +26 -6
- data/ext/relay.c +24 -28
- data/ext/vlog.c +4 -15
- data/lib/ruby-vpi/rspec.rb +1 -1
- data/lib/ruby-vpi/runner.rb +12 -10
- data/lib/ruby-vpi/runner_proxy.rb +17 -6
- data/lib/ruby-vpi/verilog_parser.rb +11 -7
- data/lib/ruby-vpi/vpi.rb +11 -1
- data/lib/ruby-vpi.rb +4 -0
- data/ref/c/annotated.html +2 -2
- data/ref/c/common_8h.html +1 -1
- data/ref/c/files.html +1 -1
- data/ref/c/functions.html +1 -1
- data/ref/c/functions_vars.html +1 -1
- data/ref/c/globals.html +1 -1
- data/ref/c/globals_0x63.html +1 -1
- data/ref/c/globals_0x65.html +1 -1
- data/ref/c/globals_0x66.html +1 -1
- data/ref/c/globals_0x70.html +1 -1
- data/ref/c/globals_0x72.html +1 -1
- data/ref/c/globals_0x73.html +1 -1
- data/ref/c/globals_0x74.html +1 -1
- data/ref/c/globals_0x76.html +2 -2
- data/ref/c/globals_0x78.html +1 -1
- data/ref/c/globals_defs.html +1 -1
- data/ref/c/globals_defs_0x65.html +1 -1
- data/ref/c/globals_defs_0x70.html +1 -1
- data/ref/c/globals_defs_0x76.html +2 -2
- data/ref/c/globals_defs_0x78.html +1 -1
- data/ref/c/globals_enum.html +1 -1
- data/ref/c/globals_eval.html +1 -1
- data/ref/c/globals_func.html +2 -2
- data/ref/c/globals_type.html +1 -1
- data/ref/c/globals_vars.html +1 -1
- data/ref/c/index.html +1 -1
- data/ref/c/relay_8c.html +2 -1
- data/ref/c/relay_8h.html +1 -1
- data/ref/c/structrelay____RubyOptions____def.html +8 -2
- data/ref/c/structt__cb__data.html +1 -1
- data/ref/c/structt__vpi__delay.html +1 -1
- data/ref/c/structt__vpi__error__info.html +1 -1
- data/ref/c/structt__vpi__strengthval.html +1 -1
- data/ref/c/structt__vpi__systf__data.html +1 -1
- data/ref/c/structt__vpi__time.html +1 -1
- data/ref/c/structt__vpi__value.html +1 -1
- data/ref/c/structt__vpi__vecval.html +1 -1
- data/ref/c/structt__vpi__vlog__info.html +1 -1
- data/ref/c/swig_8c.html +1 -1
- data/ref/c/swig_8h.html +1 -1
- data/ref/c/verilog_8h.html +1 -1
- data/ref/c/vlog_8c.html +15 -15
- data/ref/c/vlog_8h.html +1 -1
- data/ref/c/vpi__user_8h.html +1 -1
- data/ref/ruby/classes/OutputInfo.html +1 -1
- data/ref/ruby/classes/OutputInfo.src/M000030.html +30 -30
- data/ref/ruby/classes/RDoc.html +5 -5
- data/ref/ruby/classes/RDoc.src/{M000097.html → M000099.html} +0 -0
- data/ref/ruby/classes/RubyVpi.src/M000085.html +43 -39
- data/ref/ruby/classes/String.src/M000033.html +26 -26
- data/ref/ruby/classes/String.src/M000034.html +4 -4
- data/ref/ruby/classes/Template.src/M000032.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Parameter.src/M000011.html +5 -5
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000007.html +7 -7
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000008.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000009.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000010.html +4 -4
- data/ref/ruby/classes/VerilogParser/Module.src/M000006.html +15 -11
- data/ref/ruby/classes/Vpi/Handle/Property.html +5 -5
- data/ref/ruby/classes/Vpi/Handle/Property.src/{M000096.html → M000098.html} +61 -61
- data/ref/ruby/classes/Vpi/Handle.html +78 -43
- data/ref/ruby/classes/Vpi/Handle.src/M000088.html +3 -3
- data/ref/ruby/classes/Vpi/Handle.src/M000089.html +4 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000090.html +5 -31
- data/ref/ruby/classes/Vpi/Handle.src/M000091.html +9 -74
- data/ref/ruby/classes/Vpi/Handle.src/M000092.html +31 -17
- data/ref/ruby/classes/Vpi/Handle.src/M000093.html +74 -11
- data/ref/ruby/classes/Vpi/Handle.src/M000094.html +30 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000095.html +11 -55
- data/ref/ruby/classes/Vpi/Handle.src/M000097.html +68 -0
- data/ref/ruby/created.rid +1 -1
- data/ref/ruby/files/bin/generate_test_rb.html +8 -11
- data/ref/ruby/files/bin/generate_test_rb.src/M000001.html +4 -4
- data/ref/ruby/files/bin/generate_test_rb.src/M000002.html +22 -24
- data/ref/ruby/files/bin/header_to_ruby_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/float_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/integer_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rspec_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_proxy_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.html +2 -2
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.src/M000003.html +10 -10
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.src/M000004.html +12 -12
- data/ref/ruby/files/lib/ruby-vpi/verilog_parser_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/vpi_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi_rb.html +2 -1
- data/ref/ruby/fr_method_index.html +20 -18
- data/samp/counter/counter_rspec_bench.v +3 -6
- data/samp/counter/counter_rspec_design.rb +2 -1
- data/samp/counter/counter_rspec_runner.rake +20 -4
- data/samp/counter/counter_rspec_spec.rb +4 -4
- data/samp/counter/counter_xunit_bench.v +3 -6
- data/samp/counter/counter_xunit_design.rb +2 -1
- data/samp/counter/counter_xunit_runner.rake +20 -4
- data/samp/pipelined_alu/hw5_unit_test_bench.v +3 -6
- data/samp/pipelined_alu/hw5_unit_test_runner.rake +20 -4
- metadata +21 -20
- data/doc/manual.rb +0 -5
data/doc/manual.html
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<p>Ruby-VPI presents an open-ended interface to <span class="caps">VPI</span>. Thus, you can use any methodology you wish when writing tests. However, being an agile language, Ruby makes it <em>very</em> easy to use agile development practies such as <a href="#glossary.TDD"><span class="caps">TDD</span></a> and <a href="#glossary.BDD"><span class="caps">BDD</span></a>.</p>
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<p>As a newcomer into the world of Verilog, I often heard the term <strong>test bench</strong>: “I ran the test bench, but it didn’t work!” or “Are you crazy?!! You <em>still</em> haven’t written the test bench?”, for example. I
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<p>As a newcomer into the world of Verilog, I often heard the term <strong>test bench</strong>: “I ran the test bench, but it didn’t work!” or “Are you crazy?!! You <em>still</em> haven’t written the test bench?”, for example. I poured through my textbook for a definition of the term, but it was to no avail. Instead, it nonchalantly employed the term <em>throughout</em> its being, as if mocking my ignorance of what seems to be universal knowledge.</p>
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<p>Defeated, I turned to my inner faculties to determine the answer. Let’s see, the term <em>test bench</em> has the word <em>test</em>—so it has something to do with testing—and it has the word <em>bench</em>—so maybe it’s referring to a table where the testing should occur. This reasoning grew increasingly familiar as my mind rummaged through towering stores of obsolescence and ultimately revealed dreaded memories of sleepless anguish: debugging electronics in the robotics laboratory.</p>
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<p>Aha! I exclaimed, hesitantly, rushing to dismiss the past. The term has its roots in the testing of electronic devices, where an engineer would sit at a bench in an electronics laboratory and verify that an electronic component satisfies some criteria. The bench would be furnished with tools of measurement and manipulation—such as oscilloscopes, voltmeters, soldering irons, and so on—which help the engineer to verify the electronic component or locate the sources of defects in the component.</p>
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<p>Alright, now I remember what a laboratory bench is, but how does that compare with the term test bench? Surely they cannot have the same meaning, because it doesn’t make sense to <em>run</em> a laboratory bench or to <em>write</em> one. Thus, to avoid propagating such confusion into this manual, I have attempted to clarify the terminology by <a href="#glossary">simplifying and reintroducing it in a new light</a>.</p>
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<p>As <a href="#fig..organization">the figure named “Overall organization of a test”</a> shows, a <a href="#glossary.test">test</a> is composed of a <a href="#glossary.bench">bench</a>, a <a href="#glossary.design">design</a>, and a <a href="#glossary.specification">specification</a>.</p>
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<p>To extend the <a href="#background.vocab">analogy of an electronics laboratory</a>, the <em>bench</em> acts as the laboratory bench which provides measurement and manipulation tools. The <em>design</em> acts as the electronic component being verified by the engineer. And the <em>specification</em> acts as the engineer who measures, manipulates, and verifies the electronic component.</p>
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<p>Notice that Ruby-VPI encapsulates all communication between the Ruby interpreter and <span class="caps">VPI</span>. This allows the specification, or any Ruby program in general, to access <span class="caps">VPI</span> using nothing more than the Ruby language! Thus, Ruby-VPI removes the burden of having to write C programs in order to access <span class="caps">VPI</span>.</p>
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<p>Unlike an engineer who can verify an electronic component in real-time, the Verilog simulator and the Ruby interpreter (see <a href="#fig..organization.detail">the figure named “Detailed organization of a test”</a>) take turns working with <a href="#glossary.handle">handles</a> when a <a href="#glossary.test">test</a> is run. In particular, they take turns manipulating the Verilog <a href="#glossary.design">design</a> and transfer control to each other when appropriate.</p>
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<p>A test is first initialized before it is <a href="#background.running-tests.exec">executed</a>. <a href="#fig..ruby_init">the figure named “Initialization of a test”</a> illustrates the initialization process <a href="#proc..ruby_init">described below</a>.</p>
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<p>After a <a href="#glossary.test">test</a> is <a href="#background.running-tests.init">initialized</a>, it is executed such that the design is verified against the <a href="#glossary.specification">specification</a>. This process is illustrated by <a href="#fig..ruby_relay">the figure named “Execution of a test”</a>.</p>
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<p><img src="figures/ruby_relay.png" alt="" /></p>
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<li>The Verilog simulator transfers control to the Ruby interpreter by invoking the <code class="code"><span style="color:#d70; font-weight:bold">$ruby_relay</span>;</code> system task/function.</li>
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<li>The Verilog simulator is paused and the Ruby interpreter is given control.</li>
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<h1 id="setup">Setup</h1>
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<li><a href="http://www.pragmatic-c.com/gpl-cver/"><span class="caps">GPL</span> Cver</a>
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– version 2.11a or newer is acceptable.</li>
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<li><a href="http://www.icarus.com/eda/Verilog/">Icarus Verilog</a>
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– version 0.8
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– version 0.8 is <em>mostly</em> acceptable—you <strong>will not</strong> be able to <a href="#background.org.vpi.util">access child handles through method calls</a>. The reason for this limitation is explained in <a href="#problems.ivl.vpi_handle_by_name.absolute-paths">the section named “Give full paths to Verilog objects”</a>.</li>
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<li><a href="http://www.synopsys.com/products/simulation/simulation.html">Synopsys <span class="caps">VCS</span></a>
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– any version that supports the <tt>-load</tt> option is acceptable.</li>
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<li><a href="http://www.model.com">Mentor Modelsim</a>
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</ul>
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<p style="float:left"><img src="images/tip.png" title="tip" alt="tip" /></p>
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<p class="title">Tip: Add support for your Verilog simulator</p>
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<p>Write a <a href="http://rubyforge.org/tracker/?group_id=1339">support request</a> for your simulator, while providing a sample transcript of the commands you use to run a test with your simulator, and we will add support for your simulator in the next release!</p>
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– any distribution should be acceptable.</li>
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<li>Search for object files whose names end with <tt>.so</tt>, <tt>.o</tt>, or <tt>.dll</tt> in your Verilog simulator’s installation directory.</li>
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</ul>
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<ul>
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<li>Determine which object files, among those found in the previous step, contain symbols whose names begin with “_vpi” by running the <pre>for x in *.{o,so,dll}; do nm $x | grep -q '[Tt] _vpi' > /dev/null && echo $x; done</pre> command in Cygwin.
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<ul>
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<li>If you are using Mentor Modelsim, the desired object file can be found at a path similar to <tt>C:\Modeltech\win32\libvsim.dll</tt>.</li>
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<li>If you are using <span class="caps">GPL</span> Cver, the desired object file can be found at a path similar to <tt>C:\gplcver\objs\v_vpi.o</tt>.</li>
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</ul></li>
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</ul>
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<p class="title">Note
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<p class="title">Note: Undefined symbols in Windows</p>
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<p>After Ruby-VPI is compiled, it is linked to symbols whose names begin with <tt>_vpi</tt>. In <span class="caps">GNU</span>/Linux and similar operating systems, these symbols are allowed to be undefined. However, one <a href="http://sourceware.org/ml/cygwin/2001-12/msg01293.html">cannot compile a shared object file with references to undefined symbols in Windows</a>.</p>
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<p>One solution is to supply the Verilog simulator’s <span class="caps">VPI</span> object file, which contains definitions of all <span class="caps">VPI</span> symbols, to the linker. The following steps illustrate this process.</p>
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<li>Search for object files whose names end with <tt>.so</tt>, <tt>.o</tt>, or <tt>.dll</tt> in your Verilog simulator’s installation directory.</li>
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</ul>
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<li>Determine which object files, among those found in the previous step, contain symbols whose names begin with “_vpi” by running the <pre>for x in *.{o,so,dll}; do nm $x | grep -q '[Tt] _vpi' && echo $x; done</pre> command in Cygwin.
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<ul>
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<li>If you are using Mentor Modelsim, the desired object file can be found at a path similar to <tt>C:\Modeltech\win32\libvsim.dll</tt>.</li>
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<li>If you are using <span class="caps">GPL</span> Cver, the desired object file can be found at a path similar to <tt>C:\gplcver\objs\v_vpi.o</tt>.</li>
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</ul></li>
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</ul>
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<li>Assign the path of the object file (determined in the previous step) to the <code class="code"><span style="color:#036; font-weight:bold">LDFLAGS</span></code> environment variable. For example, if the object file’s path is <tt>/foo/bar/vpi.so</tt>, then you would run the <pre>export LDFLAGS=/foo/bar/vpi.so</pre> command in Cygwin.</li>
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@@ -1213,7 +1231,7 @@ $ ls -d /usr/lib/ruby/gems/1.8/gems/ruby-vpi*
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<h2 id="usage.tools">Tools</h2>
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<p>The <tt>bin</tt> directory contains various utilities which ease the process of writing tests. Each tool provides help and usage information invoked with the <tt
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<p>The <tt>bin</tt> directory contains various utilities which ease the process of writing tests. Each tool provides help and usage information invoked with the <tt>-h</tt> option.</p>
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<h3 id="usage.tools.generate-test">Automated test generation</h3>
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<ul>
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<li>Runner
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– written in Rake
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– written in <a href="#glossary.rake">Rake</a>, this file builds and runs the test.</li>
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<li>Bench
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– written in Verilog and Ruby, these files define the testing environment.</li>
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<li>Design
|
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@@ -1236,7 +1254,7 @@ $ ls -d /usr/lib/ruby/gems/1.8/gems/ruby-vpi*
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</ul>
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<p>The reason for dividing a single test into these parts is mainly to decouple the design from the specification. This allows you to focus on writing the specification while the remainder is automatically generated by the tool. For example, when the interface of a Verilog module changes, you would simply re-run this tool and incorporate those changes (using a <a href="#setup.recom">text merging tool</a>) into the test without diverting your focus from the specification.</p>
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<p>The reason for dividing a single test into these parts is mainly to decouple the design from the specification. This allows you to focus on writing the specification while the remainder is automatically generated by the tool. For example, when the interface of a Verilog module changes, you would simply re-run this tool and incorporate those changes (using a <a href="#setup.recom.merger">text merging tool</a>) into the test without diverting your focus from the specification.</p>
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<div class="admonition">
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@@ -1261,7 +1279,7 @@ kdiff3 --auto --output <span style="background-color:#fff0f0"><span style="color
|
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</ol>
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<p>From now on, <strong>kdiff3</strong> will be invoked to help you transfer your changes between generated files. When you are finished transferring changes, simply issue the “save the file” command and
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+
<p>From now on, <strong>kdiff3</strong> will be invoked to help you transfer your changes between generated files. When you are finished transferring changes, simply issue the “save the file” command and quit <strong>kdiff3</strong>. Or, if you do not want to transfer any changes, simply quit <strong>kdiff3</strong> <em>without</em> saving the file.</p>
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|
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<p>The <strong>header_to_ruby.rb</strong> tool can be used to convert Verilog header files into Ruby. You can try it by running the <pre>header_to_ruby.rb --help</pre> command.</p>
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<p>By converting Verilog header files into Ruby, your <a href="#glossary.test">test</a> can utilize the same <code class="code"><span style="background-color:#f0fff0"><span style="color:#161">`</span><span style="color:#2B2">define</span></span></code> constants that are used in the Verilog <a href="#glossary.design">design</a>.</p>
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<h2 id="usage.tutorial">Tutorial</h2>
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@@ -1353,10 +1374,24 @@ Each format represents a different software development methodology:
|
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</ul>
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<div class="admonition">
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<div class="note" id="note4">
|
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<p style="float:left"><img src="images/note.png" title="note" alt="note" /></p>
|
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<p class="title">Note:</p>
|
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|
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|
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<p>Both rSpec and xUnit formats are presented in this tutorial.</p>
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</div>
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</div>
|
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|
-
<p>Once we have decided how we want to implement our specification, we can proceed to generate a test for our design. <a href="#fig..generate-test.rspec">the example named “Generating a test with specification in rSpec format”</a> and <a href="#fig..generate-test.unit-test">the example named “Generating a test with specification in xUnit format”</a
|
|
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|
+
<p>Once we have decided how we want to implement our specification, we can proceed to generate a test for our design. This process is illustrated by <a href="#fig..generate-test.rspec">the example named “Generating a test with specification in rSpec format”</a> and <a href="#fig..generate-test.unit-test">the example named “Generating a test with specification in xUnit format”</a>.</p>
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<div class="formal">
|
|
@@ -1419,7 +1454,7 @@ Here are some reasonable expectations for our simple counter:
|
|
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|
</ul>
|
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|
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|
|
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|
-
<p>Now that we have identified a set of expectations for our design, we are ready to implement them in our specification. <a href="#fig..counter_rspec_spec.rb">the example named “Specification implemented in rSpec format”</a> and <a href="#fig..counter_xunit_spec.rb">the example named “Specification implemented in xUnit format”</a
|
|
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|
+
<p>Now that we have identified a set of expectations for our design, we are ready to implement them in our specification. This process is illustrated by <a href="#fig..counter_rspec_spec.rb">the example named “Specification implemented in rSpec format”</a> and <a href="#fig..counter_xunit_spec.rb">the example named “Specification implemented in xUnit format”</a>.</p>
|
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<div class="formal">
|
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@@ -1443,12 +1478,12 @@ context <span style="background-color:#fff0f0"><span style="color:#710">"</
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
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|
|
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|
specify <span style="background-color:#fff0f0"><span style="color:#710">"</span><span style="color:#D20">should be zero</span><span style="color:#710">"</span></span> <span style="color:#080; font-weight:bold">do</span>
|
|
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|
-
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.
|
|
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|
+
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.should == <span style="color:#00D; font-weight:bold">0</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
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|
|
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specify <span style="background-color:#fff0f0"><span style="color:#710">"</span><span style="color:#D20">should increment by one count upon each rising clock edge</span><span style="color:#710">"</span></span> <span style="color:#080; font-weight:bold">do</span>
|
|
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|
<span style="color:#036; font-weight:bold">LIMIT</span>.times <span style="color:#080; font-weight:bold">do</span> |i|
|
|
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|
-
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.
|
|
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|
+
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.should == i
|
|
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|
relay_verilog <span style="color:#888"># increment the counter</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
|
@@ -1460,12 +1495,12 @@ context <span style="background-color:#fff0f0"><span style="color:#710">"</
|
|
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|
|
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|
<span style="color:#888"># increment the counter to maximum value</span>
|
|
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|
<span style="color:#036; font-weight:bold">MAX</span>.times {relay_verilog}
|
|
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|
-
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.
|
|
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|
+
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.should == <span style="color:#036; font-weight:bold">MAX</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
|
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|
|
|
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|
specify <span style="background-color:#fff0f0"><span style="color:#710">"</span><span style="color:#D20">should overflow upon increment</span><span style="color:#710">"</span></span> <span style="color:#080; font-weight:bold">do</span>
|
|
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|
relay_verilog <span style="color:#888"># increment the counter</span>
|
|
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|
-
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.
|
|
1503
|
+
<span style="color:#036; font-weight:bold">Counter</span>.count.intVal.should == <span style="color:#00D; font-weight:bold">0</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
|
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|
<span style="color:#080; font-weight:bold">end</span>
|
|
1471
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|
</pre>
|
|
@@ -1539,13 +1574,13 @@ context <span style="background-color:#fff0f0"><span style="color:#710">"</
|
|
|
1539
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|
<ol>
|
|
1540
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|
<li>Replace the contents of the file named <tt>counter_rspec_spec.rb</tt> with the source code shown in <a href="#fig..counter_rspec_spec.rb">the example named “Specification implemented in rSpec format”</a>.</li>
|
|
1541
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|
<li>Replace the contents of the file named <tt>counter_xunit_spec.rb</tt> with the source code shown in <a href="#fig..counter_xunit_spec.rb">the example named “Specification implemented in xUnit format”</a>.</li>
|
|
1542
|
-
<li>Replace the contents of the files named <tt>counter_rspec_design.rb</tt> and <tt>counter_xunit_design.rb</tt> with the following code.
|
|
1577
|
+
<li>Replace the contents of the files named <tt>counter_rspec_design.rb</tt> and <tt>counter_xunit_design.rb</tt> with the following code. <pre class="code"><span style="color:#888"># This is a Ruby interface to the design under test.</span>
|
|
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|
+
|
|
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|
+
<span style="color:#888"># This method resets the design under test.</span>
|
|
1543
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<p>Now that we have a <a href="#glossary.specification">specification</a> against which to verify our <a href="#glossary.design">design</a>, let us build a prototype of our design. By doing so, we exercise our specification, experience potential problems that may arise when we later implement our design in Verilog, and gain confidence in our work. <a href="#fig..counter_proto.rb">the example named “Ruby prototype of our Verilog design”</a
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<p>Now that we have a <a href="#glossary.specification">specification</a> against which to verify our <a href="#glossary.design">design</a>, let us build a prototype of our design. By doing so, we exercise our specification, experience potential problems that may arise when we later implement our design in Verilog, and gain confidence in our work. The result of this proceess is illustrated by <a href="#fig..counter_proto.rb">the example named “Ruby prototype of our Verilog design”</a>.</p>
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<p>Now that we have implemented our prototype, we are ready to verify it against our <a href="#glossary.specification">specification</a> by running the <a href="#glossary.test">test</a>. <a href="#fig..test-proto.rspec">the example named “Running a test with specification in rSpec format”</a> and <a href="#fig..test-proto.unit-test">the example named “Running a test with specification in xUnit format”</a
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<p>Now that we have implemented our prototype, we are ready to verify it against our <a href="#glossary.specification">specification</a> by running the <a href="#glossary.test">test</a>. This process is illustrated by <a href="#fig..test-proto.rspec">the example named “Running a test with specification in rSpec format”</a> and <a href="#fig..test-proto.unit-test">the example named “Running a test with specification in xUnit format”</a>.</p>
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<p>The <em>same</em> specification can be used to verify both prototype and design.</p>
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<p>Here, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is assigned a non-empty value while running the test, so that, instead of our design, our prototype is verified against our specification. You can also assign a value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> before running the test, by using your shell’s <strong>export</strong> or <strong>setenv</strong> command. Finally, the Icarus Verilog simulator, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is assigned a non-empty value while running the test so that, instead of our design, our prototype is verified against our specification. You can also assign a value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> before running the test, by using your shell’s <strong>export</strong> or <strong>setenv</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>If you invoke the test runner (1) without any arguments or (2) with the <tt>-T</tt> option, it will show you a list of tasks that it can perform for you.</p>
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<p>Now that we have implemented and verified our prototype, we are ready to implement our <a href="#glossary.design">design</a>. This is often quite simple because we translate <em>existing</em> code from Ruby (our prototype) into Verilog (our design). <a href="#fig..counter.v_impl">the example named “Implementation of a simple up-counter with synchronous reset”</a
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<p>Now that we have implemented and verified our prototype, we are ready to implement our <a href="#glossary.design">design</a>. This is often quite simple because we translate <em>existing</em> code from Ruby (our prototype) into Verilog (our design). The result of this process is illustrated by <a href="#fig..counter.v_impl">the example named “Implementation of a simple up-counter with synchronous reset”</a>.</p>
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<p>Now that we have implemented our <a href="#glossary.design">design</a>, we are ready to verify it against our <a href="#glossary.specification">specification</a> by running the <a href="#glossary.test">test</a>. <a href="#fig..test-design.rspec">the example named “Running a test with specification in rSpec format”</a> and <a href="#fig..test-design.unit-test">the example named “Running a test with specification in xUnit format”</a> illustrate this process.</p>
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<p>Here, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is <em>not</em> specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code>, or by using your shell’s <strong>unset</strong> command. Finally, the <span class="caps">GPL</span> Cver Verilog simulator, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>Now you can invoke all test runners in the current directory simply by executing <pre>rake cver</pre> (where <em>cver</em> denotes the <span class="caps">GPL</span> Cver simulator).</p>
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<
|
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is <em>not</em> specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code>, or by using your shell’s <strong>unset</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p class="title">Tip: Running multiple tests at once.</p>
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<p>Create a file named <tt>Rakefile</tt> containing the following line.</p>
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<p><code class="code">require <span style="background-color:#fff0f0"><span style="color:#710">'</span><span style="color:#D20">ruby-vpi/runner_proxy</span><span style="color:#710">'</span></span></code></p>
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<p>Now you can invoke all test runners in the current directory simply by executing <pre>rake cver</pre> (where <em>cver</em> denotes the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>).</p>
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<h2 id="usage.examples">Examples</h2>
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<p>The <tt>samp</tt> directory contains several example tests which illustrate how Ruby-VPI can be used. Each example has an associated <tt>Rakefile</tt> which simplifies the process of running it. Therefore, simply navigate into an example directory and run the <pre>rake</pre> command to get started.</p>
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<p>In addition to the <a href="
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<p>In addition to the <a href="#setup.reqs">normal requirements</a>, you need the following software to build release packages:</p>
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<p>This problem was fixed in release 2.0.0 (2006-04-17).</p>
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<p>This problem was fixed in release 2.0.0 (2006-04-17).</p>
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<h4 id="problems.ivl.vpi_handle_by_name.absolute-paths">Give full paths to Verilog objects</h4>
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<p>In version 0.8 and snapshot 20061009 of Icarus Verilog, the <code class="code">vpi_handle_by_name</code> function requires an <em>absolute</em> path (including the name of the bench which instantiates the design) to a Verilog object. In addition, <code class="code">vpi_handle_by_name</code>
|
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<p>In version 0.8 and snapshot 20061009 of Icarus Verilog, the <code class="code">vpi_handle_by_name</code> function requires an <em>absolute</em> path (including the name of the bench which instantiates the design) to a Verilog object. In addition, <code class="code">vpi_handle_by_name</code> always returns <code class="code"><span style="color:#038; font-weight:bold">nil</span></code> when its second parameter is specified.</p>
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<p>For example, consider <a href="#ex..TestFoo">the example named “Part of a bench which instantiates a Verilog design”</a
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<p>For example, consider <a href="#ex..TestFoo">the example named “Part of a bench which instantiates a Verilog design”</a>. Here, one must write <code class="code">vpi_handle_by_name(<span style="background-color:#fff0f0"><span style="color:#710">"</span><span style="color:#D20">TestFoo.my_foo.clk</span><span style="color:#710">"</span></span>, <span style="color:#038; font-weight:bold">nil</span>)</code> instead of <code class="code">vpi_handle_by_name(<span style="background-color:#fff0f0"><span style="color:#710">"</span><span style="color:#D20">my_foo.clk</span><span style="color:#710">"</span></span>, <span style="color:#036; font-weight:bold">TestFoo</span>)</code> in order to access the <code class="code">clk</code> input of the <code class="code">my_foo</code> module instance.</p>
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<p>This problem was fixed in release 2.0.0 (2006-04-17).</p>
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<p>An environment in which a <a href="#glossary.design">design</a> is verified against a <a href="#glossary.specification">specification</a>. Often, it is used to emulate conditions in which the design will be eventually deployed.</p>
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<h2 id="glossary.BDD">Behavior driven development (BDD)</h2>
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<p>An <a href="http://agilemanifesto.org/">agile software development methodology</a> which emphasizes thinking in terms of behavior when designing, implementing, and verifying software.</p>
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<p>See the <a href="http://behaviour-driven.org/">official wiki</a> for more information.</p>
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<p>A Verilog module that is verified against a <a href="#glossary.specification">specification</a> in order to ensure correctness or soundness of its being. In other words, it is the thing being checked: does it work or not?</p>
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<p>A reference to an object inside the Verilog simulation that was obtained through the <code class="code">vpi_handle_by_name</code> function.</p>
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<p>Rake is a build tool, written in Ruby, using Ruby as a build language. Rake is similar to <strong>make</strong> in scope and purpose.</p>
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<p style="text-align:right;">—<a href="http://docs.rubyrake.org">Rake documentation</a></p>
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<p>See the <a href="http://rspec.rubyforge.org">rSpec website</a> and <a href="http://rspec.rubyforge.org/tutorials/index.html">tutorial</a> for more information.</p>
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<p>A set of <a href="#glossary.expectations">expectations</a> which define the desired behavior of a <a href="#glossary.design">design</a> when it is subjected to certain stimulus.</p>
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<h2 id="glossary.TDD">Test driven development (TDD)</h2>
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<p>An <a href="http://agilemanifesto.org/">agile software development methodology</a> which emphasizes (1) testing functionality before implementing it and (2) refactoring.</p>
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<p>See <a href="http://www.agiledata.org/essays/tdd.html">this introductory article</a> for more information.</p>
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<h2 id="glossary.test">Test</h2>
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