ruby-adept 0.0.1

data/.gitignore

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+*.gem
+*.rbc
+.bundle
+.config
+.yardoc
+Gemfile.lock
+InstalledFiles
+_yardoc
+coverage
+doc/
+lib/bundler/man
+pkg
+rdoc
+spec/reports
+test/tmp
+test/version_tmp
+tmp

data/.travis.yml

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+language: ruby
+rvm:
+  - 1.9.2
+  - 1.9.3
+  - jruby-19mode # JRuby in 1.9 mode
+  - rbx-19mode

data/Gemfile

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+source 'https://rubygems.org'
+
+gem "ffi"
+gem "bindata"
+gem "trollop"
+gem "smart_colored"
+gem "progressbar"
+
+# Specify your gem's dependencies in adept.gemspec
+gemspec

data/LICENSE.txt

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+Copyright (c) 2012 Kyle J. Temkin
+
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

data/README.md

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+# Adept
+
+TODO: Write a gem description
+
+## Installation
+
+Add this line to your application's Gemfile:
+
+    gem 'adept'
+
+And then execute:
+
+    $ bundle
+
+Or install it yourself as:
+
+    $ gem install adept
+
+## Usage
+
+TODO: Write usage instructions here
+
+## Contributing
+
+1. Fork it
+2. Create your feature branch (`git checkout -b my-new-feature`)
+3. Commit your changes (`git commit -am 'Add some feature'`)
+4. Push to the branch (`git push origin my-new-feature`)
+5. Create new Pull Request

data/Rakefile

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+require "bundler/gem_tasks"
+
+task :default => [:test_offline]
+
+#Offline tests only: don't perform tests that require live hardware. 
+task :test_offline do
+  sh "rspec -Ilib --tag=~online"
+end
+
+task :test do
+  sh "rspec -Ilib"
+end
+
+task :install_adept do
+
+end

data/adept.gemspec

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+# -*- encoding: utf-8 -*-
+lib = File.expand_path('../lib', __FILE__)
+$LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
+require 'adept/version'
+
+Gem::Specification.new do |gem|
+  gem.name          = "ruby-adept"
+  gem.version       = Adept::VERSION
+  gem.authors       = ["Kyle J. Temkin"]
+  gem.email         = ["ktemkin@binghamton.edu"]
+  gem.description   = 
+    'Ruby library for working with Digilent devices via the Adept SDK.
+     Provides both low-level wrappers for the Adept SDK elements and high-level
+     interfaces, including simple programming and configuration routines.'
+  gem.summary       = "Framework for working with Digilent Adept devices."
+  gem.homepage      = "http://www.github.com/ktemkin/ruby-adept"
+
+  gem.add_runtime_dependency 'bindata'
+  gem.add_runtime_dependency 'ruby-ise'
+  gem.add_runtime_dependency 'trollop'
+  gem.add_runtime_dependency 'smart_colored'
+  gem.add_runtime_dependency 'ffi'
+  gem.add_runtime_dependency 'require_all'
+
+  gem.add_development_dependency 'rspec'
+  gem.add_development_dependency 'fakefs'
+
+
+  gem.files         = `git ls-files`.split($/)
+  gem.executables   = gem.files.grep(%r{^bin/}).map{ |f| File.basename(f) }
+  gem.test_files    = gem.files.grep(%r{^(test|spec|features)/})
+  gem.require_paths = ["lib"]
+end

data/autotest/discover.rb

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+#./autotest/discover.rb
+Autotest.add_discovery {"rspec2"}

data/bin/bprog

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+#!/usr/bin/env ruby
+
+require 'ise'
+require 'adept'
+
+require 'trollop'
+require 'smart_colored/extend'
+
+include Adept
+
+#Add some separation before and after the output, to make it more visible.
+puts
+at_exit { puts }
+
+#
+#Output a formatted warning message.
+#
+def warn(message)
+  puts message.yellow
+end
+
+#
+#Output a formatted error message.
+#
+def error(message, title="Oops!")
+  puts "#{title.bold} #{message}".red
+end
+
+#
+# Output a formatted error message, and quit.
+#
+def fatal_error(message, title="Oops!")
+  error "#{message}", title
+  exit
+end
+
+#
+# Get the currently connected device.
+#
+def get_target_connection(opts={})
+
+  #Ensure that we have a plugged-in board.
+  fatal_error "It doesn't look like there's a Digilent board plugged in, on or off." if Device::connected_devices.empty? 
+
+  #By default, use the first connected device.
+  device = Device::open_first_connected_device
+  at_exit { device.close }
+
+  #If the device doesn't support JTAG, we can't program it.
+  fatal_error "This device isn't supported." unless device.supported_connections.include?(JTAG::Connection)
+
+  jtag = JTAG::Connection.new(device)
+  fatal_error "The power switch is off on your connected board! Turn it on, and try again." if jtag.connected_devices.empty?
+
+  jtag
+
+end
+
+#
+# Get the target file.
+# 
+def get_target_file(opts={})
+
+  #If a file was provided on the command line, use it.
+  file = ARGV.shift if ARGV
+
+  #Attempt to determine the target file automagically.
+  unless file
+
+    #Attempt to determine the file.
+    file = ISE::ProjectNavigator::most_recent_project.bit_file
+    fatal_error "You didn't specify a file to program, and I couldn't figure out a likely candidate.\n      Perhaps you still need to generate a programming file?"  unless file
+
+    #And warn the user of the file we chose.
+    warn "You didn't specify a file to program, so I assumed you wanted me to program:"
+    puts "#{File::dirname(file)}/#{File::basename(file).bold}"
+
+  end
+
+  fatal_error "The file you asked me to program doesn't seem to exist." unless File::exists?(file)
+
+  #Return the ascertained file.
+  file
+
+end
+
+def configure_fpga(jtag, bitfile_path)
+
+  #Find the first connected FPGA.
+  fpga = jtag.connected_devices.find { |device| device.is_a? JTAG::Devices::FPGA }
+  fatal_error "This board doesn't feature a supported FPGA!" unless fpga
+
+  #Get the bit-file in question.
+  bitstream = Adept::DataFormats::Bitstream.from_file(bitfile_path)
+  fpga.configure(bitstream)
+
+end
+
+connection = get_target_connection
+file = get_target_file
+
+begin
+  configure_fpga(connection, file)
+rescue Error => e
+  puts
+  fatal_error e.message
+end
+
+
+

data/firmware/.gitignore

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+# intermediate build files
+*.bgn
+*.bit
+*.bld
+*.cmd_log
+*.drc
+*.ll
+*.lso
+*.msd
+*.msk
+*.ncd
+*.ngc
+*.ngd
+*.ngr
+*.pad
+*.par
+*.pcf
+*.prj
+*.ptwx
+*.rbb
+*.rbd
+*.stx
+*.syr
+*.twr
+*.twx
+*.unroutes
+*.ut
+*.xpi
+*.xst
+*_bitgen.xwbt
+*_envsettings.html
+*_map.map
+*_map.mrp
+*_map.ngm
+*_map.xrpt
+*_ngdbuild.xrpt
+*_pad.csv
+*_pad.txt
+*_par.xrpt
+*_summary.html
+*_summary.xml
+*_usage.xml
+*_xst.xrpt
+*.xmsgs
+
+# IP-core-related generated files
+xaw2vhdl.log
+
+# project-wide generated files
+*.gise
+par_usage_statistics.html
+usage_statistics_webtalk.html
+webtalk.log
+webtalk_pn.xml
+
+# generated folders
+iseconfig/
+xlnx_auto_0_xdb/
+xst/
+_ngo/
+_xmsgs/
+
+#Simulation generated files
+*isim_*.exe
+*isim_*.wdb
+fuse.log
+fuse.log
+fuse.xmsgs
+fuseRelaunch.cmd
+isim.cmd
+isim.log
+isim/
+xilinxsim.ini

data/firmware/epp_stream/Basys2_100_250General.ucf

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+#Basys Board on-board clock.
+NET "clk"             LOC = "B8"; # Bank = 0, Signal name = MCLK
+
+#Reset button.
+NET "reset"           LOC = "G12"; #PB12
+
+#EPP Control Signals
+NET "eppAddrStrobe"   LOC = "F2"; # Bank = 3
+NET "eppDataStrobe"   LOC = "F1"; # Bank = 3
+NET "eppReadNotWrite" LOC = "C2"; # Bank = 3
+NET "eppAck"          LOC = "D2"; # Bank = 3
+
+#EPP Data Signals
+NET "eppDataBus<0>"   LOC = "N2"; # Bank = 2
+NET "eppDataBus<1>"   LOC = "M2"; # Bank = 2
+NET "eppDataBus<2>"   LOC = "M1"; # Bank = 3
+NET "eppDataBus<3>"   LOC = "L1"; # Bank = 3
+NET "eppDataBus<4>"   LOC = "L2"; # Bank = 3
+NET "eppDataBus<5>"   LOC = "H2"; # Bank = 3
+NET "eppDataBus<6>"   LOC = "H1"; # Bank = 3
+NET "eppDataBus<7>"   LOC = "H3"; # Bank = 3

data/firmware/epp_stream/epp_controller.vhd

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+
+----------------------------------------------------------------------------------
+-- EPP Controller
+--
+-- Original Author: Chris McClelland
+-- Altered for use with EPP periperhals by Kyle Temkin
+--
+-- Portions copyright (c) 2013 Binghamton University
+-- Copyright (c) 2011 Chris McClelland
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.-
+--
+----------------------------------------------------------------------------------
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity TopLevel is
+	port(
+		-- Main 50MHz clock
+		clk             : in    std_logic;
+
+		-- Reset button (BTN0)
+		reset           : in   std_logic;
+	
+		-- Host interface signals
+		eppDataBus      : inout std_logic_vector(7 downto 0);
+		eppAddrStrobe   : in    std_logic;
+		eppDataStrobe   : in    std_logic;
+		eppReadNotWrite : in    std_logic;
+		eppAck          : out   std_logic
+	);
+end TopLevel;
+
+architecture Behavioural of TopLevel is
+	type State is (-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+
+		STATE_IDLE,
+
+		STATE_ADDR_WRITE_EXEC,
+		STATE_ADDR_WRITE_ACK,
+
+		STATE_DATA_WRITE_EXEC,
+		STATE_DATA_WRITE_ACK,
+
+		STATE_DATA_READ_EXEC,
+		STATE_DATA_READ_ACK
+	);
+
+	-- State and next-state
+	signal iThisState, iNextState : State;
+
+	-- Synchronised versions of asynchronous inputs
+	signal iSyncAddrStrobe              : std_logic;
+	signal iSyncDataStrobe              : std_logic;
+	signal iSyncReadNotWrite            : std_logic;
+	
+	-- Data to be mux'd back to host
+	signal iDataOutput                  : std_logic_vector(7 downto 0);
+
+	-- Registers
+	signal iThisRegAddr, iNextRegAddr   : std_logic_vector(1 downto 0);
+	signal iThisAck, iNextAck           : std_logic;
+	signal iThisR0, iNextR0             : std_logic_vector(7 downto 0);
+	signal iThisR1, iNextR1             : std_logic_vector(7 downto 0);
+	signal iThisR2, iNextR2             : std_logic_vector(7 downto 0);
+	signal iThisR3, iNextR3             : std_logic_vector(7 downto 0);
+
+begin
+
+	-- Drive the outputs
+	eppAck <= iThisAck;
+
+	-- EPP operation
+	eppDataBus <=
+		iDataOutput when ( eppReadNotWrite = '1' ) else
+		"ZZZZZZZZ";
+
+	with ( iThisRegAddr ) select
+		iDataOutput <=
+			iThisR0 when "00",
+			iThisR1 when "01",
+			iThisR2 when "10",
+			iThisR3 when others;
+
+	-- Infer registers
+	process(clk, reset)
+	begin
+		if ( reset = '1' ) then
+			iThisState        <= STATE_IDLE;
+			iThisRegAddr      <= (others => '0');
+			iThisR0           <= (others => '0');
+			iThisR1           <= (others => '0');
+			iThisR2           <= (others => '0');
+			iThisR3           <= (others => '0');
+			iThisAck          <= '0';
+			iSyncAddrStrobe   <= '1';
+			iSyncDataStrobe   <= '1';
+			iSyncReadNotWrite <= '1';
+		elsif ( clk'event and clk = '1' ) then
+			iThisState        <= iNextState;
+			iThisRegAddr      <= iNextRegAddr;
+			iThisR0           <= iNextR0;
+			iThisR1           <= iNextR1;
+			iThisR2           <= iNextR2;
+			iThisR3           <= iNextR3;
+			iThisAck          <= iNextAck;
+			iSyncAddrStrobe   <= eppAddrStrobe;
+			iSyncDataStrobe   <= eppDataStrobe;
+			iSyncReadNotWrite <= eppReadNotWrite;
+		end if;
+	end process;
+
+	-- Next state logic
+	process(
+		eppDataBus, iThisState, iThisRegAddr,
+		iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
+		iThisR0, iThisR1, iThisR2, iThisR3)
+	begin
+		iNextAck        <= '0';
+		iNextState      <= STATE_IDLE;
+		iNextRegAddr    <= iThisRegAddr;
+		iNextR0         <= iThisR0;
+		iNextR1         <= iThisR1;
+		iNextR2         <= iThisR2;
+		iNextR3         <= iThisR3;
+		case iThisState is
+			when STATE_IDLE =>
+				if ( iSyncAddrStrobe = '0' ) then
+					-- Address can only be written, not read
+					if ( iSyncReadNotWrite = '0' ) then
+						iNextState <= STATE_ADDR_WRITE_EXEC;
+					end if;
+				elsif ( iSyncDataStrobe = '0' ) then
+					-- Register read or write
+					if ( iSyncReadNotWrite = '0' ) then
+						iNextState <= STATE_DATA_WRITE_EXEC;
+					else
+						iNextState <= STATE_DATA_READ_EXEC;
+					end if;
+				end if;
+
+			-- Write address register
+			when STATE_ADDR_WRITE_EXEC =>
+				iNextRegAddr <= eppDataBus(1 downto 0);
+				iNextState   <= STATE_ADDR_WRITE_ACK;
+				iNextAck     <= '0';
+			when STATE_ADDR_WRITE_ACK =>
+				if ( iSyncAddrStrobe = '0' ) then
+					iNextState <= STATE_ADDR_WRITE_ACK;
+					iNextAck   <= '1';
+				else
+					iNextState <= STATE_IDLE;
+					iNextAck   <= '0';
+				end if;
+
+			-- Write data register
+			when STATE_DATA_WRITE_EXEC =>
+				case iThisRegAddr is
+					when "00" =>
+						iNextR0 <= eppDataBus;
+					when "01" =>
+						iNextR1 <= eppDataBus;
+					when "10" =>
+						iNextR2 <= eppDataBus;
+					when others =>
+						iNextR3 <= eppDataBus;
+				end case;
+				iNextState <= STATE_DATA_WRITE_ACK;
+				iNextAck   <= '1';
+			when STATE_DATA_WRITE_ACK =>
+				if ( iSyncDataStrobe = '0' ) then
+					iNextState <= STATE_DATA_WRITE_ACK;
+					iNextAck   <= '1';
+				else
+					iNextState <= STATE_IDLE;
+					iNextAck   <= '0';
+				end if;
+
+			-- Read data register
+			when STATE_DATA_READ_EXEC =>
+				iNextAck    <= '1';
+				iNextState  <= STATE_DATA_READ_ACK;
+			when STATE_DATA_READ_ACK =>
+				if ( iSyncDataStrobe = '0' ) then
+					iNextState <= STATE_DATA_READ_ACK;
+					iNextAck   <= '1';
+				else
+					iNextState <= STATE_IDLE;
+					iNextAck   <= '0';
+				end if;
+
+			-- Some unknown state
+			when others =>
+				iNextState <= STATE_IDLE;
+		end case;
+	end process;
+end Behavioural;