rggen 0.4.1 → 0.4.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -1,135 +1,43 @@
-[![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
-[![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
-[![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
+[![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
+[![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
+[![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
 [![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
 [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
-
-# RgGen
-
-RgGen is a code generation tool for SoC designers.
-It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
-Also RgGen is customizable so you can build your specific generate tool.
-
-## Ruby
-
-RgGen is written in the [*Ruby*](https://www.ruby-lang.org/en/about/) programing language and supports version 2.0 or later.
-If you don't have above version of Ruby, you need to install the Ruby at first.
-To install the Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
-
-## Installation
-
-To install RgGen and required libraries, use the following command:
-
-    $ gem install rggen
-
-RgGen will be installed under your system root.
-
-If you want to install them on other location, you need to specify the install directory and set the **GEM_PATH** environment variable like below:
-
-    $ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
-    $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
-
-## Usage
-
-### Writing Configuration File
-
-A configuration file is to describe attributes of your design, e.g. data bus width, address bus width, host interface protocol.
-RgGen supports YAML and JSON for its file format and allows to use Hash notation to describe attributes of your design like below.
-
-- YAML
-~~~YAML
-address_width: 16
-data_width: 32
-host_if: apb
-~~~
-- JSON
-~~~JSON
-{
-  "address_width": 16,
-  "data_width": 32,
-  "host_if": "apb"
-}
-~~~
-
-These attributes have default values. If you use a default value, you don't specify its value.
-In addition, if you use default values for all of attributes, you don't need to write a configuration file.
-
-### Writing Register Map Document
-
-RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
-To do this, you need to write your register map document according to below table format.
-
-|    |A   |B             |C            |D              |E                                |F       |G             |H         |I   |J           |K        |
-|:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------|:-------------|:---------|:---|:-----------|:--------|
-|1   |    |Block Name    |block_0      |               |                                 |        |              |          |    |            |         |
-|2   |    |Byte Size     |256          |               |                                 |        |              |          |    |            |         |
-|3   |    |              |             |               |                                 |        |              |          |    |            |         |
-|4   |    |Offset Address|Register Name|Array Dimension|Shadow Index                     |External|Bit Assignment|Field Name|Type|Iitial Value|Reference|
-|5   |    |0x00          |register_0   |               |                                 |        |[31:16]       |field_0_0 |rw  |0           |         |
-|6   |    |              |             |               |                                 |        |[15:0]        |field_0_1 |rw  |0           |         |
-|7   |    |0x04          |register_1   |               |                                 |        |[16]          |field_1_0 |rw  |0           |         |
-|8   |    |              |             |               |                                 |        |[0]           |field_1_1 |ro  |            |         |
-|9   |    |0x10 - 0x1F   |register_2   |[4]            |                                 |        |[7:0]         |field_2_0 |rw  |0           |         |
-|10  |    |0x20 - 0x3F   |register_3   |               |                                 |true    |              |          |    |            |         |
-|11  |    |0x40          |register_4   |[2, 4]         |field_1_0:1, field_0_0, field_0_1|        |[7:0]         |field_4_0 |rw  |0           |         |
-|12  |    |0x44          |register_5   |               |                                 |        |[8]           |field_5_0 |w0s |0           |         |
-|13  |    |              |             |               |                                 |        |[0]           |field_5_1 |w1s |0           |         |
-|14  |    |0x48          |register_6   |               |                                 |        |[8]           |field_6_0 |w0c |0           |field_1_0|
-|15  |    |              |             |               |                                 |        |[0]           |field_6_1 |w1c |0           |field_1_0|
-
-By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
-
-### Generating Source Code
-
-To generate soruce code from your register map document, use the following command:
-
-    $ rggen your_register_map.xls
-
-If you have a configuration file, you need to use `-c/--configuration` option:
-
-    $ rggen -c your_configuration.yml your_register_map.xls
-
-By default, RgGen will generate RTL SV code under `rtl` directory and UVM RAL model under `ral` dicrectory.
-In addition, file name of generated files is accoding to below rule.
-- RTL
-  - `your_block_name`.sv
-- RAL model
-  - `your_block_name`_ral_pkg.sv
-
-### Compiling Your Design
-
-RgGen has base RTL modules and RAL model package (the base library) to build generated RTL and UVM RAL models.
-Therefore, to compile your design with the base library, you need followins steps:
-
-1. Set the RGGEN_HOME environment variable
-2. Link the base library with you design
-
-**RGGEN_HOME** environement variable is to show the install direcoty.
-To set the variable, you can use `--show-home` option like below:
-
-    $ export RGGEN_HOME=`rggen --show-home`
-
-To link the base library with your design, RgGen has file lists for the base library.
-By using the lists, you can compile your design and the base library like below:
-
-    $ simulator \
-      -f $RGGEN_HOME/rtl/compile.f \
-      -f $RGGEN_HOME/ral/compile.f \
-      rtl/your_register_block.sv \
-      ral/your_register_block_ral_pkg.sv \
-      your_test_bench.sv \
-      your_design.v
-
-### Note
-
-Contents of configuration file and register map document and structure of genrerated RTL and RAL model described above are default.
-Also you can change these by customizing RgGen.
-
-## Development
-
-After checking out the repo, run `bin/setup` to install dependencies. Then, run `rake spec` to run the tests.
-
-To install this gem onto your local machine, run `bundle exec rake install`. To release a new version, update the version number in `version.rb`, and then run `bundle exec rake release`, which will create a git tag for the version, push git commits and tags, and push the `.gem` file to [rubygems.org](https://rubygems.org).
+
+# RgGen
+
+RgGen is a code generation tool for SoC designers.
+It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
+Also RgGen is customizable so you can build your specific generate tool.
+
+## Ruby
+
+RgGen is written in the [*Ruby*](https://www.ruby-lang.org/en/about/) programing language and supports version 2.0 or later.
+If you don't have above version of Ruby, you need to install the Ruby at first.
+To install the Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
+
+## Installation
+
+To install RgGen and required libraries, use the following command:
+
+    $ gem install rggen
+
+RgGen will be installed under your system root.
+
+If you want to install them on other location, you need to specify the install directory and set the **GEM_PATH** environment variable like below:
+
+    $ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
+    $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
+
+## Usage
+
+See [this page](https://github.com/taichi-ishitani/rggen/wiki/Getting-Started)
+
+## Development
+
+After checking out the repo, run `bin/setup` to install dependencies. Then, run `rake spec` to run the tests.
+
+To install this gem onto your local machine, run `bundle exec rake install`. To release a new version, update the version number in `version.rb`, and then run `bundle exec rake release`, which will create a git tag for the version, push git commits and tags, and push the `.gem` file to [rubygems.org](https://rubygems.org).
 
 ## Contact
 
@@ -139,11 +47,11 @@ If you have any questions, problems, ideas or somethings, you can post them on t
 2. [Chat room](https://gitter.im/taichi-ishitani/rggen)
 3. [Mail](mailto:taichi730@gmail.com)
 
-## Contributing
-
-Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the [Contributor Covenant](http://contributor-covenant.org) code of conduct.
-
-## License
-
+## Contributing
+
+Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the [Contributor Covenant](http://contributor-covenant.org) code of conduct.
+
+## License
+
 Copyright © 2015-2016 Taichi Ishitani.
 RgGen is available as open source under the terms of [the MIT License](LICENSE.txt).

data/lib/rggen.rb

@@ -17,6 +17,7 @@ module RgGen
 
   require_relative 'rggen/base/hierarchical_accessors'
   require_relative 'rggen/base/hierarchical_item_accessors'
+  require_relative 'rggen/base/internal_struct'
   require_relative 'rggen/base/component'
   require_relative 'rggen/base/item'
   require_relative 'rggen/base/component_factory'

data/lib/rggen/base/internal_struct.rb

@@ -0,0 +1,28 @@
+module RgGen
+  module Base
+    module InternalStruct
+      private
+
+      def internal_structs
+        @internal_structs ||= {}
+      end
+
+      def define_struct(struct_name, members, &body)
+        return if internal_structs.key?(struct_name)
+        internal_structs[struct_name] = Struct.new(*members, &body)
+        define_method(struct_name) do
+          self.class.send(:internal_structs)[struct_name]
+        end
+        private(struct_name)
+      end
+
+      def inherited(subclass)
+        super(subclass)
+        return unless instance_variable_defined?(:@internal_structs)
+        subclass.instance_variable_set(
+          :@internal_structs, Hash[@internal_structs]
+        )
+      end
+    end
+  end
+end

data/lib/rggen/base/item.rb

@@ -2,6 +2,7 @@ module RgGen
   module Base
     class Item
       extend Forwardable
+      extend InternalStruct
 
       class << self
         def define_helpers(&body)

data/lib/rggen/builtins.rb

@@ -14,6 +14,7 @@ require_relative 'builtins/bit_field/name'
 require_relative 'builtins/bit_field/reference'
 require_relative 'builtins/bit_field/type'
 require_relative 'builtins/bit_field/rw'
+require_relative 'builtins/bit_field/rwl_rwe'
 require_relative 'builtins/bit_field/ro'
 require_relative 'builtins/bit_field/w0c_w1c'
 require_relative 'builtins/bit_field/w0s_w1s'

data/lib/rggen/builtins/bit_field/field_model.rb

@@ -2,11 +2,11 @@ simple_item :bit_field, :field_model do
   ral do
     export :model_creation
 
-    delegate [:name, :width, :lsb, :access] => :bit_field
+    delegate [:name, :width, :lsb, :access, :model_name] => :bit_field
 
     build do
       variable :reg_model, :field_model,
-               data_type: :rggen_ral_field,
+               data_type: model_name,
                name:      name,
                random:    true
     end

data/lib/rggen/builtins/bit_field/rwl_rwe.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_rwl_rwe #(
+  .LOCK_MODE      (<%= lock_mode %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_<%= bit_field.name %> (
+  .clk              (<%= register_block.clock %>),
+  .rst_n            (<%= register_block.reset %>),
+  .i_lock_or_enable (<%= lock_or_enable %>),
+  .i_command_valid  (<%= register_block.host_if.command_valid %>),
+  .i_select         (<%= register_block.register_select[index] %>),
+  .i_write          (<%= register_block.host_if.write %>),
+  .i_write_data     (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
+  .i_write_mask     (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
+  .o_value          (<%= value[loop_variables] %>)
+);

data/lib/rggen/builtins/bit_field/rwl_rwe.rb

@@ -0,0 +1,55 @@
+list_item :bit_field, :type, [:rwl, :rwe] do
+  register_map do
+    read_write
+    need_initial_value
+    use_reference width: 1, required: true
+  end
+
+  rtl do
+    build do
+      output :value_out,
+             name:      "o_#{bit_field.name}",
+             width:      width,
+             dimensions: dimensions
+    end
+
+    generate_code :module_item do |code|
+      code << assign(value_out[loop_variables], value[loop_variables]) << nl
+      code << process_template
+    end
+
+    def lock_mode
+      { rwl: 1, rwe: 0 }[bit_field.type]
+    end
+
+    def initial_value
+      hex(bit_field.initial_value, width)
+    end
+
+    def lock_or_enable
+      mode_field.value
+    end
+
+    def mode_field
+      register_block.bit_fields.find do |f|
+        f.name == bit_field.reference.name
+      end
+    end
+  end
+
+  ral do
+    model_name { "#{class_name}#(#{mode_register}, #{mode_field})" }
+
+    def class_name
+      "rggen_ral_field_#{bit_field.type}"
+    end
+
+    def mode_register
+      string(bit_field.reference.register.name)
+    end
+
+    def mode_field
+      string(bit_field.reference.name)
+    end
+  end
+end

data/lib/rggen/builtins/bit_field/type.rb

@@ -193,11 +193,16 @@ list_item :bit_field, :type do
   ral do
     item_base do
       export :access
+      export :model_name
       export :hdl_path
 
       define_helpers do
         attr_setter :access
 
+        def model_name(&body)
+          define_method(:model_name, &body)
+        end
+
         def hdl_path(&body)
           define_method(:hdl_path, &body)
         end
@@ -207,6 +212,10 @@ list_item :bit_field, :type do
         string((self.class.access || bit_field.type).to_s.upcase)
       end
 
+      def model_name
+        :rggen_ral_field
+      end
+
       def hdl_path
         "u_#{bit_field.name}.value"
       end

data/lib/rggen/builtins/register/read_data.rb

@@ -1,13 +1,23 @@
 simple_item :register, :read_data do
   rtl do
-    available? do
-      !register.external?
-    end
+    available? { register.internal? }
 
     generate_code :module_item do |buffer|
       buffer  << assign(register_read_data, read_data) << nl
     end
 
+    define_struct :read_data_entry, [:lsb, :msb, :value, :dummy] do
+      def initialize(args)
+        self.lsb    = args[:lsb]
+        self.msb    = args[:msb]
+        self.value  = args[:value]
+        self.dummy  = args[:dummy] || false
+      end
+    end
+
+    delegate [:data_width] => :configuration
+    delegate [:loop_variables] => :register
+
     def register_read_data
       register_block.register_read_data[register.index]
     end
@@ -21,16 +31,27 @@ simple_item :register, :read_data do
     end
 
     def read_data_expressions
-      last_lsb    = configuration.data_width
-      expressions = []
-      readable_fields.each do |field|
-        padding_bits  = last_lsb - field.msb - 1
-        last_lsb      = field.lsb
+      read_data_entries.each_cons(2).with_object([]) do |entries, expressions|
+        padding_bits  = entries[0].lsb - entries[1].msb - 1
         expressions << hex(0, padding_bits) if padding_bits > 0
-        expressions << field.value[register.loop_variables]
+        expressions << entries[1].value unless entries[1].dummy
+      end
+    end
+
+    def read_data_entries
+      [].tap do |entries|
+        entries << read_data_entry.new(lsb: data_width, dummy: true)
+        entries.concat(readable_field_entries)
+        entries << read_data_entry.new(msb: -1, dummy: true)
+      end
+    end
+
+    def readable_field_entries
+      readable_fields.map do |field|
+        read_data_entry.new(
+          lsb: field.lsb, msb: field.msb, value: field.value[loop_variables]
+        )
       end
-      expressions << hex(0, last_lsb) if last_lsb > 0
-      expressions
     end
 
     def readable_fields

data/lib/rggen/builtins/register/shadow.rb

@@ -1,18 +1,5 @@
 simple_item :register, :shadow do
   register_map do
-    ShadowIndexEntry  = Struct.new(:name, :value) do
-      def initialize(name, value)
-        self.name   = name
-        self.value  = value && Integer(value)
-      end
-
-      def ==(other)
-        return false unless name == other.name
-        return true if [value, other.value].any?(&:nil?)
-        value == other.value
-      end
-    end
-
     field :shadow?
     field :shadow_indexes
 
@@ -32,11 +19,24 @@ simple_item :register, :shadow do
       check_specific_value_index_values
     end
 
+    define_struct :shadow_index_entry, [:name, :value] do
+      def initialize(name, value)
+        self.name   = name
+        self.value  = value && Integer(value)
+      end
+
+      def ==(other)
+        return false unless name == other.name
+        return true if [value, other.value].any?(&:nil?)
+        value == other.value
+      end
+    end
+
     def parse_shadow_indexes(cell)
       return nil if cell.nil? || cell.empty?
       cell.split(/[,\n]/).map do |entry|
         if pattern_match(entry)
-          ShadowIndexEntry.new(captures[0], captures[1])
+          shadow_index_entry.new(captures[0], captures[1])
         else
           error "invalid value for shadow index: #{cell.inspect}"
         end