rggen 0.4.1 → 0.4.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +44 -136
- data/lib/rggen.rb +1 -0
- data/lib/rggen/base/internal_struct.rb +28 -0
- data/lib/rggen/base/item.rb +1 -0
- data/lib/rggen/builtins.rb +1 -0
- data/lib/rggen/builtins/bit_field/field_model.rb +2 -2
- data/lib/rggen/builtins/bit_field/rwl_rwe.erb +15 -0
- data/lib/rggen/builtins/bit_field/rwl_rwe.rb +55 -0
- data/lib/rggen/builtins/bit_field/type.rb +9 -0
- data/lib/rggen/builtins/register/read_data.rb +32 -11
- data/lib/rggen/builtins/register/shadow.rb +14 -14
- data/lib/rggen/core_components/register_map/bit_field_factory.rb +2 -2
- data/lib/rggen/core_components/register_map/item_factory.rb +1 -1
- data/lib/rggen/core_components/register_map/register_block_factory.rb +2 -2
- data/lib/rggen/core_components/register_map/register_factory.rb +2 -2
- data/lib/rggen/core_extensions/facets.rb +1 -0
- data/lib/rggen/input_base/component_factory.rb +4 -4
- data/lib/rggen/input_base/item.rb +1 -0
- data/lib/rggen/output_base/item.rb +1 -0
- data/lib/rggen/output_base/verilog_utility/declaration.rb +12 -21
- data/lib/rggen/version.rb +1 -1
- data/ral/rggen_ral_field_rwl_rwe.svh +158 -0
- data/ral/rggen_ral_pkg.sv +1 -0
- data/ral/rggen_ral_shadow_reg.svh +51 -46
- data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv +30 -0
- data/sample/sample.csv +3 -1
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample_0.sv +78 -27
- data/sample/sample_0_ral_pkg.sv +16 -3
- data/sample/sample_setup.rb +1 -1
- data/setup/default.rb +1 -1
- metadata +7 -2
@@ -0,0 +1,30 @@
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module rggen_bit_field_rwl_rwe #(
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parameter LOCK_MODE = 1,
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parameter WIDTH = 1,
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parameter INITIAL_VALUE = 0
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)(
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input clk,
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input rst_n,
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input i_lock_or_enable,
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9
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input i_command_valid,
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input i_select,
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input i_write,
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input [WIDTH-1:0] i_write_data,
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input [WIDTH-1:0] i_write_mask,
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output [WIDTH-1:0] o_value
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);
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logic [WIDTH-1:0] value;
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logic writable;
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assign o_value = value;
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assign writable = (LOCK_MODE) ? !i_lock_or_enable : i_lock_or_enable;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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value <= INITIAL_VALUE;
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end
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else if (writable && i_command_valid && i_select && i_write) begin
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value <= (i_write_data & ( i_write_mask))
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| (value & (~i_write_mask));
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end
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end
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endmodule
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data/sample/sample.csv
CHANGED
@@ -16,5 +16,7 @@
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,,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1,
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,0x28,register_7,,,,[8],bit_field_7_0,w0s,0,,
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,,,,,,[0],bit_field_7_1,w1s,0,,
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,
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,0x2C,register_8,,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1,
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,,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1,
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,0x80-0xFF,register_9,,,TRUE,,,,,,
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,,,,,,,,,,,
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data/sample/sample.xls
CHANGED
Binary file
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data/sample/sample.xlsx
CHANGED
Binary file
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data/sample/sample_0.sv
CHANGED
@@ -28,15 +28,17 @@ module sample_0 (
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input i_bit_field_7_0_clear,
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output o_bit_field_7_1,
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input i_bit_field_7_1_clear,
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output
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output
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output
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output
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output
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output [
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input
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output [15:0] o_bit_field_8_0,
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output [15:0] o_bit_field_8_1,
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output o_register_9_valid,
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output o_register_9_write,
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output o_register_9_read,
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output [6:0] o_register_9_address,
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output [3:0] o_register_9_strobe,
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output [31:0] o_register_9_write_data,
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input i_register_9_ready,
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input [1:0] i_register_9_status,
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input [31:0] i_register_9_read_data
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);
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logic command_valid;
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logic write;
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@@ -48,8 +50,8 @@ module sample_0 (
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logic response_ready;
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logic [31:0] read_data;
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logic [1:0] status;
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logic [
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logic [31:0] register_read_data[
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logic [19:0] register_select;
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logic [31:0] register_read_data[20];
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logic [0:0] external_register_select;
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logic [0:0] external_register_ready;
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logic [1:0] external_register_status[1];
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@@ -70,6 +72,8 @@ module sample_0 (
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logic bit_field_6_1_value;
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logic bit_field_7_0_value;
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logic bit_field_7_1_value;
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logic [15:0] bit_field_8_0_value;
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logic [15:0] bit_field_8_1_value;
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rggen_host_if_apb #(
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.DATA_WIDTH (32),
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.HOST_ADDRESS_WIDTH (16),
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@@ -100,7 +104,7 @@ module sample_0 (
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104
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);
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rggen_response_mux #(
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.DATA_WIDTH (32),
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-
.TOTAL_REGISTERS (
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.TOTAL_REGISTERS (20),
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.TOTAL_EXTERNAL_REGISTERS (1)
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) u_response_mux (
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.clk (clk),
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@@ -432,8 +436,8 @@ module sample_0 (
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);
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rggen_address_decoder #(
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.ADDRESS_WIDTH (6),
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-
.START_ADDRESS (6'
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-
.END_ADDRESS (6'
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.START_ADDRESS (6'h0b),
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.END_ADDRESS (6'h0b),
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.USE_SHADOW_INDEX (0),
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.SHADOW_INDEX_WIDTH (1),
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.SHADOW_INDEX_VALUE (1'h0)
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@@ -444,33 +448,80 @@ module sample_0 (
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.i_shadow_index (1'h0),
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.o_select (register_select[18])
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);
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-
assign
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assign register_read_data[18] = {bit_field_8_0_value, bit_field_8_1_value};
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assign o_bit_field_8_0 = bit_field_8_0_value;
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rggen_bit_field_rwl_rwe #(
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.LOCK_MODE (1),
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455
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.WIDTH (16),
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.INITIAL_VALUE (16'h0000)
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457
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) u_bit_field_8_0 (
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458
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.clk (clk),
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459
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.rst_n (rst_n),
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460
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.i_lock_or_enable (bit_field_2_1_value),
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461
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.i_command_valid (command_valid),
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462
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.i_select (register_select[18]),
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463
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.i_write (write),
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464
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.i_write_data (write_data[31:16]),
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.i_write_mask (write_mask[31:16]),
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.o_value (bit_field_8_0_value)
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);
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assign o_bit_field_8_1 = bit_field_8_1_value;
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469
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rggen_bit_field_rwl_rwe #(
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470
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.LOCK_MODE (0),
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471
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.WIDTH (16),
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.INITIAL_VALUE (16'h0000)
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473
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) u_bit_field_8_1 (
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474
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.clk (clk),
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475
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.rst_n (rst_n),
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.i_lock_or_enable (bit_field_2_1_value),
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477
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.i_command_valid (command_valid),
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478
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.i_select (register_select[18]),
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479
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.i_write (write),
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480
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.i_write_data (write_data[15:0]),
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.i_write_mask (write_mask[15:0]),
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482
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.o_value (bit_field_8_1_value)
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483
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);
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484
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rggen_address_decoder #(
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.ADDRESS_WIDTH (6),
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486
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.START_ADDRESS (6'h20),
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487
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.END_ADDRESS (6'h3f),
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488
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.USE_SHADOW_INDEX (0),
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489
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.SHADOW_INDEX_WIDTH (1),
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.SHADOW_INDEX_VALUE (1'h0)
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491
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) u_register_9_address_decoder (
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492
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.i_read (read),
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493
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.i_write (write),
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.i_address (address[7:2]),
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.i_shadow_index (1'h0),
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.o_select (register_select[19])
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);
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assign external_register_select[0] = register_select[19];
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448
499
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rggen_bus_exporter #(
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.DATA_WIDTH (32),
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501
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.LOCAL_ADDRESS_WIDTH (8),
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502
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.EXTERNAL_ADDRESS_WIDTH (7),
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452
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.START_ADDRESS (8'h80)
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453
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-
)
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) u_register_9_bus_exporter (
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.clk (clk),
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.rst_n (rst_n),
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.i_valid (command_valid),
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457
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.i_select (register_select[
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508
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.i_select (register_select[19]),
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509
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.i_write (write),
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459
510
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.i_read (read),
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460
511
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.i_address (address),
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512
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.i_strobe (strobe),
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.i_write_data (write_data),
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514
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.o_ready (external_register_ready[0]),
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464
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.o_read_data (register_read_data[
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.o_read_data (register_read_data[19]),
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516
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.o_status (external_register_status[0]),
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466
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.o_valid (
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.o_write (
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.o_read (
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.o_address (
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.o_strobe (
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.o_write_data (
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.i_ready (
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.i_read_data (
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.i_status (
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.o_valid (o_register_9_valid),
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.o_write (o_register_9_write),
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.o_read (o_register_9_read),
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.o_address (o_register_9_address),
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.o_strobe (o_register_9_strobe),
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522
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.o_write_data (o_register_9_write_data),
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.i_ready (i_register_9_ready),
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.i_read_data (i_register_9_read_data),
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.i_status (i_register_9_status)
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);
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endmodule
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data/sample/sample_0_ral_pkg.sv
CHANGED
@@ -92,8 +92,19 @@ package sample_0_ral_pkg;
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`rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
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endfunction
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endclass
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class register_8_reg_model extends rggen_ral_reg;
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rand rggen_ral_field_rwl#("register_2", "bit_field_2_1") bit_field_8_0;
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rand rggen_ral_field_rwe#("register_2", "bit_field_2_1") bit_field_8_1;
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function new(string name = "register_8");
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super.new(name, 32, 0);
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endfunction
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function void create_fields();
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`rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "u_bit_field_8_0.value")
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`rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "u_bit_field_8_1.value")
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endfunction
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endclass
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class sample_0_block_model#(
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96
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-
type
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type REGISTER_9 = rggen_ral_block
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) extends rggen_ral_block;
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109
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rand register_0_reg_model register_0;
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rand register_1_reg_model register_1;
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@@ -103,7 +114,8 @@ package sample_0_ral_pkg;
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114
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rand register_5_reg_model register_5[2][4];
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rand register_6_reg_model register_6;
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rand register_7_reg_model register_7;
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rand
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rand register_8_reg_model register_8;
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rand REGISTER_9 register_9;
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function new(string name = "sample_0");
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120
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super.new(name);
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121
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endfunction
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@@ -120,7 +132,8 @@ package sample_0_ral_pkg;
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120
132
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end
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133
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`rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
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`rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
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123
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-
`
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`rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "")
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136
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`rggen_ral_create_block_model(register_9, "register_9", 8'h80)
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124
137
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endfunction
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125
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function uvm_reg_map create_default_map();
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126
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return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
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data/sample/sample_setup.rb
CHANGED
@@ -12,7 +12,7 @@ enable :global , [:data_width, :address_width]
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12
12
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enable :register_block, [:name, :base_address]
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enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
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14
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enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
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15
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-
enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :foo, :reserved]
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15
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enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
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enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
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enable :register_block, :host_if, [:apb, :bar]
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enable :register , [:address_decoder, :read_data, :bus_exporter]
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data/setup/default.rb
CHANGED
@@ -2,7 +2,7 @@ enable :global , [:data_width, :address_width]
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2
2
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enable :register_block, [:name, :byte_size]
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3
3
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enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
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4
4
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enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
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-
enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :reserved]
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+
enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
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6
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enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
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7
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enable :register_block, :host_if, [:apb, :axi4lite]
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8
8
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enable :register , [:address_decoder, :read_data, :bus_exporter]
|
metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
|
2
2
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name: rggen
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3
3
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version: !ruby/object:Gem::Version
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4
|
-
version: 0.4.
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4
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+
version: 0.4.2
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5
5
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platform: ruby
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6
6
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authors:
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7
7
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- Taichi Ishitani
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8
8
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autorequire:
|
9
9
|
bindir: bin
|
10
10
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cert_chain: []
|
11
|
-
date: 2016-
|
11
|
+
date: 2016-07-14 00:00:00.000000000 Z
|
12
12
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dependencies:
|
13
13
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- !ruby/object:Gem::Dependency
|
14
14
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name: baby_erubis
|
@@ -128,6 +128,7 @@ files:
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|
128
128
|
- lib/rggen/base/component_factory.rb
|
129
129
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- lib/rggen/base/hierarchical_accessors.rb
|
130
130
|
- lib/rggen/base/hierarchical_item_accessors.rb
|
131
|
+
- lib/rggen/base/internal_struct.rb
|
131
132
|
- lib/rggen/base/item.rb
|
132
133
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- lib/rggen/base/item_factory.rb
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133
134
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- lib/rggen/builder/builder.rb
|
@@ -150,6 +151,8 @@ files:
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|
150
151
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- lib/rggen/builtins/bit_field/ro.rb
|
151
152
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- lib/rggen/builtins/bit_field/rw.erb
|
152
153
|
- lib/rggen/builtins/bit_field/rw.rb
|
154
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+
- lib/rggen/builtins/bit_field/rwl_rwe.erb
|
155
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+
- lib/rggen/builtins/bit_field/rwl_rwe.rb
|
153
156
|
- lib/rggen/builtins/bit_field/type.rb
|
154
157
|
- lib/rggen/builtins/bit_field/w0c_w1c.erb
|
155
158
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- lib/rggen/builtins/bit_field/w0c_w1c.rb
|
@@ -256,6 +259,7 @@ files:
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|
256
259
|
- ral/compile.f
|
257
260
|
- ral/rggen_ral_block.svh
|
258
261
|
- ral/rggen_ral_field.svh
|
262
|
+
- ral/rggen_ral_field_rwl_rwe.svh
|
259
263
|
- ral/rggen_ral_macros.svh
|
260
264
|
- ral/rggen_ral_map.svh
|
261
265
|
- ral/rggen_ral_pkg.sv
|
@@ -263,6 +267,7 @@ files:
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|
263
267
|
- ral/rggen_ral_shadow_reg.svh
|
264
268
|
- rtl/bit_field/rggen_bit_field_ro.sv
|
265
269
|
- rtl/bit_field/rggen_bit_field_rw.sv
|
270
|
+
- rtl/bit_field/rggen_bit_field_rwl_rwe.sv
|
266
271
|
- rtl/bit_field/rggen_bit_field_w0c_w1c.sv
|
267
272
|
- rtl/bit_field/rggen_bit_field_w0s_w1s.sv
|
268
273
|
- rtl/compile.f
|