rggen 0.4.1 → 0.4.2

data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv

@@ -0,0 +1,30 @@
+module rggen_bit_field_rwl_rwe #(
+  parameter LOCK_MODE     = 1,
+  parameter WIDTH         = 1,
+  parameter INITIAL_VALUE = 0
+)(
+  input               clk,
+  input               rst_n,
+  input               i_lock_or_enable,
+  input               i_command_valid,
+  input               i_select,
+  input               i_write,
+  input   [WIDTH-1:0] i_write_data,
+  input   [WIDTH-1:0] i_write_mask,
+  output  [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+  logic             writable;
+
+  assign  o_value   = value;
+  assign  writable  = (LOCK_MODE) ? !i_lock_or_enable : i_lock_or_enable;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else if (writable && i_command_valid && i_select && i_write) begin
+      value <= (i_write_data & ( i_write_mask))
+             | (value        & (~i_write_mask));
+    end
+  end
+endmodule

data/sample/sample.csv

@@ -16,5 +16,7 @@
 ,,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1,
 ,0x28,register_7,,,,[8],bit_field_7_0,w0s,0,,
 ,,,,,,[0],bit_field_7_1,w1s,0,,
-,0x80-0xFF,register_8,,,TRUE,,,,,,
+,0x2C,register_8,,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1,
+,,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1,
+,0x80-0xFF,register_9,,,TRUE,,,,,,
 ,,,,,,,,,,,

data/sample/sample_0.sv

@@ -28,15 +28,17 @@ module sample_0 (
   input i_bit_field_7_0_clear,
   output o_bit_field_7_1,
   input i_bit_field_7_1_clear,
-  output o_register_8_valid,
-  output o_register_8_write,
-  output o_register_8_read,
-  output [6:0] o_register_8_address,
-  output [3:0] o_register_8_strobe,
-  output [31:0] o_register_8_write_data,
-  input i_register_8_ready,
-  input [1:0] i_register_8_status,
-  input [31:0] i_register_8_read_data
+  output [15:0] o_bit_field_8_0,
+  output [15:0] o_bit_field_8_1,
+  output o_register_9_valid,
+  output o_register_9_write,
+  output o_register_9_read,
+  output [6:0] o_register_9_address,
+  output [3:0] o_register_9_strobe,
+  output [31:0] o_register_9_write_data,
+  input i_register_9_ready,
+  input [1:0] i_register_9_status,
+  input [31:0] i_register_9_read_data
 );
   logic command_valid;
   logic write;
@@ -48,8 +50,8 @@ module sample_0 (
   logic response_ready;
   logic [31:0] read_data;
   logic [1:0] status;
-  logic [18:0] register_select;
-  logic [31:0] register_read_data[19];
+  logic [19:0] register_select;
+  logic [31:0] register_read_data[20];
   logic [0:0] external_register_select;
   logic [0:0] external_register_ready;
   logic [1:0] external_register_status[1];
@@ -70,6 +72,8 @@ module sample_0 (
   logic bit_field_6_1_value;
   logic bit_field_7_0_value;
   logic bit_field_7_1_value;
+  logic [15:0] bit_field_8_0_value;
+  logic [15:0] bit_field_8_1_value;
   rggen_host_if_apb #(
     .DATA_WIDTH           (32),
     .HOST_ADDRESS_WIDTH   (16),
@@ -100,7 +104,7 @@ module sample_0 (
   );
   rggen_response_mux #(
     .DATA_WIDTH               (32),
-    .TOTAL_REGISTERS          (19),
+    .TOTAL_REGISTERS          (20),
     .TOTAL_EXTERNAL_REGISTERS (1)
   ) u_response_mux (
     .clk                        (clk),
@@ -432,8 +436,8 @@ module sample_0 (
   );
   rggen_address_decoder #(
     .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h20),
-    .END_ADDRESS        (6'h3f),
+    .START_ADDRESS      (6'h0b),
+    .END_ADDRESS        (6'h0b),
     .USE_SHADOW_INDEX   (0),
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
@@ -444,33 +448,80 @@ module sample_0 (
     .i_shadow_index (1'h0),
     .o_select       (register_select[18])
   );
-  assign external_register_select[0] = register_select[18];
+  assign register_read_data[18] = {bit_field_8_0_value, bit_field_8_1_value};
+  assign o_bit_field_8_0 = bit_field_8_0_value;
+  rggen_bit_field_rwl_rwe #(
+    .LOCK_MODE      (1),
+    .WIDTH          (16),
+    .INITIAL_VALUE  (16'h0000)
+  ) u_bit_field_8_0 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_lock_or_enable (bit_field_2_1_value),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[18]),
+    .i_write          (write),
+    .i_write_data     (write_data[31:16]),
+    .i_write_mask     (write_mask[31:16]),
+    .o_value          (bit_field_8_0_value)
+  );
+  assign o_bit_field_8_1 = bit_field_8_1_value;
+  rggen_bit_field_rwl_rwe #(
+    .LOCK_MODE      (0),
+    .WIDTH          (16),
+    .INITIAL_VALUE  (16'h0000)
+  ) u_bit_field_8_1 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_lock_or_enable (bit_field_2_1_value),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[18]),
+    .i_write          (write),
+    .i_write_data     (write_data[15:0]),
+    .i_write_mask     (write_mask[15:0]),
+    .o_value          (bit_field_8_1_value)
+  );
+  rggen_address_decoder #(
+    .ADDRESS_WIDTH      (6),
+    .START_ADDRESS      (6'h20),
+    .END_ADDRESS        (6'h3f),
+    .USE_SHADOW_INDEX   (0),
+    .SHADOW_INDEX_WIDTH (1),
+    .SHADOW_INDEX_VALUE (1'h0)
+  ) u_register_9_address_decoder (
+    .i_read         (read),
+    .i_write        (write),
+    .i_address      (address[7:2]),
+    .i_shadow_index (1'h0),
+    .o_select       (register_select[19])
+  );
+  assign external_register_select[0] = register_select[19];
   rggen_bus_exporter #(
     .DATA_WIDTH             (32),
     .LOCAL_ADDRESS_WIDTH    (8),
     .EXTERNAL_ADDRESS_WIDTH (7),
     .START_ADDRESS          (8'h80)
-  ) u_register_8_bus_exporter (
+  ) u_register_9_bus_exporter (
     .clk          (clk),
     .rst_n        (rst_n),
     .i_valid      (command_valid),
-    .i_select     (register_select[18]),
+    .i_select     (register_select[19]),
     .i_write      (write),
     .i_read       (read),
     .i_address    (address),
     .i_strobe     (strobe),
     .i_write_data (write_data),
     .o_ready      (external_register_ready[0]),
-    .o_read_data  (register_read_data[18]),
+    .o_read_data  (register_read_data[19]),
     .o_status     (external_register_status[0]),
-    .o_valid      (o_register_8_valid),
-    .o_write      (o_register_8_write),
-    .o_read       (o_register_8_read),
-    .o_address    (o_register_8_address),
-    .o_strobe     (o_register_8_strobe),
-    .o_write_data (o_register_8_write_data),
-    .i_ready      (i_register_8_ready),
-    .i_read_data  (i_register_8_read_data),
-    .i_status     (i_register_8_status)
+    .o_valid      (o_register_9_valid),
+    .o_write      (o_register_9_write),
+    .o_read       (o_register_9_read),
+    .o_address    (o_register_9_address),
+    .o_strobe     (o_register_9_strobe),
+    .o_write_data (o_register_9_write_data),
+    .i_ready      (i_register_9_ready),
+    .i_read_data  (i_register_9_read_data),
+    .i_status     (i_register_9_status)
   );
 endmodule

data/sample/sample_0_ral_pkg.sv

@@ -92,8 +92,19 @@ package sample_0_ral_pkg;
       `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
     endfunction
   endclass
+  class register_8_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field_rwl#("register_2", "bit_field_2_1") bit_field_8_0;
+    rand rggen_ral_field_rwe#("register_2", "bit_field_2_1") bit_field_8_1;
+    function new(string name = "register_8");
+      super.new(name, 32, 0);
+    endfunction
+    function void create_fields();
+      `rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "u_bit_field_8_0.value")
+      `rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "u_bit_field_8_1.value")
+    endfunction
+  endclass
   class sample_0_block_model#(
-    type REGISTER_8 = rggen_ral_block
+    type REGISTER_9 = rggen_ral_block
   ) extends rggen_ral_block;
     rand register_0_reg_model register_0;
     rand register_1_reg_model register_1;
@@ -103,7 +114,8 @@ package sample_0_ral_pkg;
     rand register_5_reg_model register_5[2][4];
     rand register_6_reg_model register_6;
     rand register_7_reg_model register_7;
-    rand REGISTER_8 register_8;
+    rand register_8_reg_model register_8;
+    rand REGISTER_9 register_9;
     function new(string name = "sample_0");
       super.new(name);
     endfunction
@@ -120,7 +132,8 @@ package sample_0_ral_pkg;
       end
       `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
       `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
-      `rggen_ral_create_block_model(register_8, "register_8", 8'h80)
+      `rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "")
+      `rggen_ral_create_block_model(register_9, "register_9", 8'h80)
     endfunction
     function uvm_reg_map create_default_map();
       return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);

data/sample/sample_setup.rb

@@ -12,7 +12,7 @@ enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :base_address]
 enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :foo, :reserved]
+enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
 enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :bar]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]

data/setup/default.rb

@@ -2,7 +2,7 @@ enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :byte_size]
 enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :reserved]
+enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
 enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :axi4lite]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.4.1
+  version: 0.4.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-06-07 00:00:00.000000000 Z
+date: 2016-07-14 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -128,6 +128,7 @@ files:
 - lib/rggen/base/component_factory.rb
 - lib/rggen/base/hierarchical_accessors.rb
 - lib/rggen/base/hierarchical_item_accessors.rb
+- lib/rggen/base/internal_struct.rb
 - lib/rggen/base/item.rb
 - lib/rggen/base/item_factory.rb
 - lib/rggen/builder/builder.rb
@@ -150,6 +151,8 @@ files:
 - lib/rggen/builtins/bit_field/ro.rb
 - lib/rggen/builtins/bit_field/rw.erb
 - lib/rggen/builtins/bit_field/rw.rb
+- lib/rggen/builtins/bit_field/rwl_rwe.erb
+- lib/rggen/builtins/bit_field/rwl_rwe.rb
 - lib/rggen/builtins/bit_field/type.rb
 - lib/rggen/builtins/bit_field/w0c_w1c.erb
 - lib/rggen/builtins/bit_field/w0c_w1c.rb
@@ -256,6 +259,7 @@ files:
 - ral/compile.f
 - ral/rggen_ral_block.svh
 - ral/rggen_ral_field.svh
+- ral/rggen_ral_field_rwl_rwe.svh
 - ral/rggen_ral_macros.svh
 - ral/rggen_ral_map.svh
 - ral/rggen_ral_pkg.sv
@@ -263,6 +267,7 @@ files:
 - ral/rggen_ral_shadow_reg.svh
 - rtl/bit_field/rggen_bit_field_ro.sv
 - rtl/bit_field/rggen_bit_field_rw.sv
+- rtl/bit_field/rggen_bit_field_rwl_rwe.sv
 - rtl/bit_field/rggen_bit_field_w0c_w1c.sv
 - rtl/bit_field/rggen_bit_field_w0s_w1s.sv
 - rtl/compile.f