rggen 0.4.1 → 0.4.2

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@@ -0,0 +1,30 @@
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+ module rggen_bit_field_rwl_rwe #(
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+ parameter LOCK_MODE = 1,
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+ parameter WIDTH = 1,
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+ parameter INITIAL_VALUE = 0
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+ )(
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+ input clk,
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+ input rst_n,
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+ input i_lock_or_enable,
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+ input i_command_valid,
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+ input i_select,
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+ input i_write,
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+ input [WIDTH-1:0] i_write_data,
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+ input [WIDTH-1:0] i_write_mask,
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+ output [WIDTH-1:0] o_value
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+ );
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+ logic [WIDTH-1:0] value;
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+ logic writable;
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+
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+ assign o_value = value;
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+ assign writable = (LOCK_MODE) ? !i_lock_or_enable : i_lock_or_enable;
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+ always_ff @(posedge clk or negedge rst_n) begin
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+ if (!rst_n) begin
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+ value <= INITIAL_VALUE;
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+ end
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+ else if (writable && i_command_valid && i_select && i_write) begin
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+ value <= (i_write_data & ( i_write_mask))
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+ | (value & (~i_write_mask));
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+ end
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+ end
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+ endmodule
data/sample/sample.csv CHANGED
@@ -16,5 +16,7 @@
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  ,,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1,
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  ,0x28,register_7,,,,[8],bit_field_7_0,w0s,0,,
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  ,,,,,,[0],bit_field_7_1,w1s,0,,
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- ,0x80-0xFF,register_8,,,TRUE,,,,,,
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+ ,0x2C,register_8,,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1,
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+ ,,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1,
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+ ,0x80-0xFF,register_9,,,TRUE,,,,,,
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  ,,,,,,,,,,,
data/sample/sample.xls CHANGED
Binary file
data/sample/sample.xlsx CHANGED
Binary file
data/sample/sample_0.sv CHANGED
@@ -28,15 +28,17 @@ module sample_0 (
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  input i_bit_field_7_0_clear,
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  output o_bit_field_7_1,
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  input i_bit_field_7_1_clear,
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- output o_register_8_valid,
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- output o_register_8_write,
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- output o_register_8_read,
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- output [6:0] o_register_8_address,
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- output [3:0] o_register_8_strobe,
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- output [31:0] o_register_8_write_data,
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- input i_register_8_ready,
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- input [1:0] i_register_8_status,
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- input [31:0] i_register_8_read_data
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+ output [15:0] o_bit_field_8_0,
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+ output [15:0] o_bit_field_8_1,
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+ output o_register_9_valid,
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+ output o_register_9_write,
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+ output o_register_9_read,
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+ output [6:0] o_register_9_address,
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+ output [3:0] o_register_9_strobe,
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+ output [31:0] o_register_9_write_data,
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+ input i_register_9_ready,
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+ input [1:0] i_register_9_status,
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+ input [31:0] i_register_9_read_data
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  );
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  logic command_valid;
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  logic write;
@@ -48,8 +50,8 @@ module sample_0 (
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  logic response_ready;
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  logic [31:0] read_data;
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  logic [1:0] status;
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- logic [18:0] register_select;
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- logic [31:0] register_read_data[19];
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+ logic [19:0] register_select;
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+ logic [31:0] register_read_data[20];
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  logic [0:0] external_register_select;
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  logic [0:0] external_register_ready;
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  logic [1:0] external_register_status[1];
@@ -70,6 +72,8 @@ module sample_0 (
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  logic bit_field_6_1_value;
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  logic bit_field_7_0_value;
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  logic bit_field_7_1_value;
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+ logic [15:0] bit_field_8_0_value;
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+ logic [15:0] bit_field_8_1_value;
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  rggen_host_if_apb #(
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  .DATA_WIDTH (32),
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  .HOST_ADDRESS_WIDTH (16),
@@ -100,7 +104,7 @@ module sample_0 (
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  );
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  rggen_response_mux #(
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  .DATA_WIDTH (32),
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- .TOTAL_REGISTERS (19),
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+ .TOTAL_REGISTERS (20),
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  .TOTAL_EXTERNAL_REGISTERS (1)
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  ) u_response_mux (
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  .clk (clk),
@@ -432,8 +436,8 @@ module sample_0 (
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  );
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  rggen_address_decoder #(
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  .ADDRESS_WIDTH (6),
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- .START_ADDRESS (6'h20),
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- .END_ADDRESS (6'h3f),
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+ .START_ADDRESS (6'h0b),
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+ .END_ADDRESS (6'h0b),
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  .USE_SHADOW_INDEX (0),
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  .SHADOW_INDEX_WIDTH (1),
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  .SHADOW_INDEX_VALUE (1'h0)
@@ -444,33 +448,80 @@ module sample_0 (
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  .i_shadow_index (1'h0),
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  .o_select (register_select[18])
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  );
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- assign external_register_select[0] = register_select[18];
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+ assign register_read_data[18] = {bit_field_8_0_value, bit_field_8_1_value};
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+ assign o_bit_field_8_0 = bit_field_8_0_value;
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+ rggen_bit_field_rwl_rwe #(
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+ .LOCK_MODE (1),
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+ .WIDTH (16),
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+ .INITIAL_VALUE (16'h0000)
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+ ) u_bit_field_8_0 (
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+ .clk (clk),
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+ .rst_n (rst_n),
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+ .i_lock_or_enable (bit_field_2_1_value),
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+ .i_command_valid (command_valid),
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+ .i_select (register_select[18]),
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+ .i_write (write),
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+ .i_write_data (write_data[31:16]),
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+ .i_write_mask (write_mask[31:16]),
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+ .o_value (bit_field_8_0_value)
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+ );
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+ assign o_bit_field_8_1 = bit_field_8_1_value;
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+ rggen_bit_field_rwl_rwe #(
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+ .LOCK_MODE (0),
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+ .WIDTH (16),
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+ .INITIAL_VALUE (16'h0000)
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+ ) u_bit_field_8_1 (
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+ .clk (clk),
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+ .rst_n (rst_n),
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+ .i_lock_or_enable (bit_field_2_1_value),
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+ .i_command_valid (command_valid),
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+ .i_select (register_select[18]),
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+ .i_write (write),
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+ .i_write_data (write_data[15:0]),
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+ .i_write_mask (write_mask[15:0]),
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+ .o_value (bit_field_8_1_value)
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+ );
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+ rggen_address_decoder #(
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+ .ADDRESS_WIDTH (6),
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+ .START_ADDRESS (6'h20),
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+ .END_ADDRESS (6'h3f),
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+ .USE_SHADOW_INDEX (0),
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+ .SHADOW_INDEX_WIDTH (1),
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+ .SHADOW_INDEX_VALUE (1'h0)
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+ ) u_register_9_address_decoder (
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+ .i_read (read),
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+ .i_write (write),
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+ .i_address (address[7:2]),
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+ .i_shadow_index (1'h0),
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+ .o_select (register_select[19])
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+ );
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+ assign external_register_select[0] = register_select[19];
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  rggen_bus_exporter #(
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  .DATA_WIDTH (32),
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  .LOCAL_ADDRESS_WIDTH (8),
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  .EXTERNAL_ADDRESS_WIDTH (7),
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  .START_ADDRESS (8'h80)
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- ) u_register_8_bus_exporter (
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+ ) u_register_9_bus_exporter (
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  .clk (clk),
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  .rst_n (rst_n),
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  .i_valid (command_valid),
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- .i_select (register_select[18]),
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+ .i_select (register_select[19]),
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  .i_write (write),
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  .i_read (read),
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  .i_address (address),
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  .i_strobe (strobe),
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  .i_write_data (write_data),
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  .o_ready (external_register_ready[0]),
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- .o_read_data (register_read_data[18]),
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+ .o_read_data (register_read_data[19]),
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  .o_status (external_register_status[0]),
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- .o_valid (o_register_8_valid),
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- .o_write (o_register_8_write),
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- .o_read (o_register_8_read),
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- .o_address (o_register_8_address),
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- .o_strobe (o_register_8_strobe),
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- .o_write_data (o_register_8_write_data),
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- .i_ready (i_register_8_ready),
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- .i_read_data (i_register_8_read_data),
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- .i_status (i_register_8_status)
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+ .o_valid (o_register_9_valid),
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+ .o_write (o_register_9_write),
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+ .o_read (o_register_9_read),
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+ .o_address (o_register_9_address),
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+ .o_strobe (o_register_9_strobe),
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+ .o_write_data (o_register_9_write_data),
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+ .i_ready (i_register_9_ready),
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+ .i_read_data (i_register_9_read_data),
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+ .i_status (i_register_9_status)
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  );
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  endmodule
@@ -92,8 +92,19 @@ package sample_0_ral_pkg;
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  `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
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  endfunction
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  endclass
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+ class register_8_reg_model extends rggen_ral_reg;
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+ rand rggen_ral_field_rwl#("register_2", "bit_field_2_1") bit_field_8_0;
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+ rand rggen_ral_field_rwe#("register_2", "bit_field_2_1") bit_field_8_1;
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+ function new(string name = "register_8");
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+ super.new(name, 32, 0);
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+ endfunction
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+ function void create_fields();
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+ `rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "u_bit_field_8_0.value")
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+ `rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "u_bit_field_8_1.value")
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+ endfunction
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+ endclass
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  class sample_0_block_model#(
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- type REGISTER_8 = rggen_ral_block
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+ type REGISTER_9 = rggen_ral_block
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  ) extends rggen_ral_block;
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  rand register_0_reg_model register_0;
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  rand register_1_reg_model register_1;
@@ -103,7 +114,8 @@ package sample_0_ral_pkg;
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  rand register_5_reg_model register_5[2][4];
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  rand register_6_reg_model register_6;
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  rand register_7_reg_model register_7;
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- rand REGISTER_8 register_8;
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+ rand register_8_reg_model register_8;
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+ rand REGISTER_9 register_9;
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  function new(string name = "sample_0");
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  super.new(name);
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  endfunction
@@ -120,7 +132,8 @@ package sample_0_ral_pkg;
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  end
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  `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
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  `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
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- `rggen_ral_create_block_model(register_8, "register_8", 8'h80)
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+ `rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "")
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+ `rggen_ral_create_block_model(register_9, "register_9", 8'h80)
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  endfunction
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  function uvm_reg_map create_default_map();
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  return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
@@ -12,7 +12,7 @@ enable :global , [:data_width, :address_width]
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  enable :register_block, [:name, :base_address]
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  enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
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  enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
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- enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :foo, :reserved]
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+ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
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  enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
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  enable :register_block, :host_if, [:apb, :bar]
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  enable :register , [:address_decoder, :read_data, :bus_exporter]
data/setup/default.rb CHANGED
@@ -2,7 +2,7 @@ enable :global , [:data_width, :address_width]
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  enable :register_block, [:name, :byte_size]
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  enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
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  enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
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- enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :reserved]
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+ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
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  enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
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  enable :register_block, :host_if, [:apb, :axi4lite]
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  enable :register , [:address_decoder, :read_data, :bus_exporter]
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.4.1
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+ version: 0.4.2
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2016-06-07 00:00:00.000000000 Z
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+ date: 2016-07-14 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: baby_erubis
@@ -128,6 +128,7 @@ files:
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  - lib/rggen/base/component_factory.rb
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  - lib/rggen/base/hierarchical_accessors.rb
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  - lib/rggen/base/hierarchical_item_accessors.rb
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+ - lib/rggen/base/internal_struct.rb
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  - lib/rggen/base/item.rb
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  - lib/rggen/base/item_factory.rb
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  - lib/rggen/builder/builder.rb
@@ -150,6 +151,8 @@ files:
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  - lib/rggen/builtins/bit_field/ro.rb
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  - lib/rggen/builtins/bit_field/rw.erb
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  - lib/rggen/builtins/bit_field/rw.rb
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+ - lib/rggen/builtins/bit_field/rwl_rwe.erb
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+ - lib/rggen/builtins/bit_field/rwl_rwe.rb
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  - lib/rggen/builtins/bit_field/type.rb
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  - lib/rggen/builtins/bit_field/w0c_w1c.erb
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  - lib/rggen/builtins/bit_field/w0c_w1c.rb
@@ -256,6 +259,7 @@ files:
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  - ral/compile.f
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  - ral/rggen_ral_block.svh
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  - ral/rggen_ral_field.svh
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+ - ral/rggen_ral_field_rwl_rwe.svh
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  - ral/rggen_ral_macros.svh
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  - ral/rggen_ral_map.svh
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  - ral/rggen_ral_pkg.sv
@@ -263,6 +267,7 @@ files:
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  - ral/rggen_ral_shadow_reg.svh
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  - rtl/bit_field/rggen_bit_field_ro.sv
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  - rtl/bit_field/rggen_bit_field_rw.sv
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+ - rtl/bit_field/rggen_bit_field_rwl_rwe.sv
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  - rtl/bit_field/rggen_bit_field_w0c_w1c.sv
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  - rtl/bit_field/rggen_bit_field_w0s_w1s.sv
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  - rtl/compile.f