rggen 0.4.1 → 0.4.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +44 -136
- data/lib/rggen.rb +1 -0
- data/lib/rggen/base/internal_struct.rb +28 -0
- data/lib/rggen/base/item.rb +1 -0
- data/lib/rggen/builtins.rb +1 -0
- data/lib/rggen/builtins/bit_field/field_model.rb +2 -2
- data/lib/rggen/builtins/bit_field/rwl_rwe.erb +15 -0
- data/lib/rggen/builtins/bit_field/rwl_rwe.rb +55 -0
- data/lib/rggen/builtins/bit_field/type.rb +9 -0
- data/lib/rggen/builtins/register/read_data.rb +32 -11
- data/lib/rggen/builtins/register/shadow.rb +14 -14
- data/lib/rggen/core_components/register_map/bit_field_factory.rb +2 -2
- data/lib/rggen/core_components/register_map/item_factory.rb +1 -1
- data/lib/rggen/core_components/register_map/register_block_factory.rb +2 -2
- data/lib/rggen/core_components/register_map/register_factory.rb +2 -2
- data/lib/rggen/core_extensions/facets.rb +1 -0
- data/lib/rggen/input_base/component_factory.rb +4 -4
- data/lib/rggen/input_base/item.rb +1 -0
- data/lib/rggen/output_base/item.rb +1 -0
- data/lib/rggen/output_base/verilog_utility/declaration.rb +12 -21
- data/lib/rggen/version.rb +1 -1
- data/ral/rggen_ral_field_rwl_rwe.svh +158 -0
- data/ral/rggen_ral_pkg.sv +1 -0
- data/ral/rggen_ral_shadow_reg.svh +51 -46
- data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv +30 -0
- data/sample/sample.csv +3 -1
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample_0.sv +78 -27
- data/sample/sample_0_ral_pkg.sv +16 -3
- data/sample/sample_setup.rb +1 -1
- data/setup/default.rb +1 -1
- metadata +7 -2
@@ -1,9 +1,9 @@
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module RgGen
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module RegisterMap
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class BitFieldFactory < ComponentFactory
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def create_active_items(bit_field,
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def create_active_items(bit_field, cells)
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active_item_factories.each_value.with_index do |factory, index|
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create_item(factory, bit_field,
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create_item(factory, bit_field, cells[index])
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end
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end
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end
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@@ -3,7 +3,7 @@ module RgGen
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class ItemFactory < InputBase::ItemFactory
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include RaiseError
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def create(component,
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def create(component, cell = nil)
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convert_cell_value(cell)
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create_item(component, cell) do |item|
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item.build(cell) unless cell.nil?
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@@ -1,10 +1,10 @@
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module RgGen
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module RegisterMap
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class RegisterBlockFactory < ComponentFactory
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def create_active_items(register_block,
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def create_active_items(register_block, sheet)
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active_item_factories.each_value.with_index do |factory, index|
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cell = sheet[index, 2]
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create_item(factory, register_block,
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create_item(factory, register_block, cell)
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end
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end
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@@ -1,9 +1,9 @@
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module RgGen
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module RegisterMap
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class RegisterFactory < ComponentFactory
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def create_active_items(register,
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def create_active_items(register, rows)
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active_item_factories.each_value.with_index do |factory, index|
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create_item(factory, register,
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create_item(factory, register, rows.first[index])
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end
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end
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@@ -8,6 +8,7 @@ require 'facets/kernel/not'
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require 'facets/kernel/not_nil'
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require 'facets/module/attr_setter'
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require 'facets/numeric/positive'
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require 'facets/object/itself' unless Object.public_method_defined?(:itself)
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require 'facets/range/overlap'
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require 'facets/regexp/op_add'
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require 'facets/regexp/op_or'
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@@ -20,13 +20,13 @@ module RgGen
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private
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def create_items(component, *sources)
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create_active_items(component,
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create_passive_items(component
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create_active_items(component, sources.last)
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create_passive_items(component)
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end
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def create_passive_items(component
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def create_passive_items(component)
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passive_item_factories.each do |factory|
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create_item(factory, component
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create_item(factory, component)
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end
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end
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@@ -20,26 +20,24 @@ module RgGen
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width,
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identifier,
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default_value_assignment
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].
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].select(&:itself)
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end
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def random_or_direction_or_parameter_type
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-
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when :parameter
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@attributes[:parameter_type] || ''
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end
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{
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variable: @attributes[:random] && :rand,
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port: @attributes[:direction],
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parameter: @attributes[:parameter_type]
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}[@declation_type]
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end
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def data_type
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@attributes[:data_type]
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@attributes[:data_type]
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end
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def width
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return unless vector?
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"[#{(@attributes[:width] || 1) - 1}:0]"
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end
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def identifier
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end
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def dimensions
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return
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return if @attributes[:dimensions].nil?
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@attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
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end
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def default_value_assignment
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def variable?
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@declation_type == :variable
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end
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def port?
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@declation_type == :port
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return if @attributes[:default].nil?
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"= #{@attributes[:default]}"
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end
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def parameter?
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data/lib/rggen/version.rb
CHANGED
@@ -0,0 +1,158 @@
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`ifndef __RGGEN_RAL_FIELD_RWL_RWE_SVH__
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`define __RGGEN_RAL_FIELD_RWL_RWE_SVH__
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class rggen_ral_field_rwl_rwe_cbs extends uvm_reg_cbs;
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local uvm_reg_field this_field;
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local bit lock_mode;
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local string mode_reg_name;
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local string mode_field_name;
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local uvm_reg_field mode_field;
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extern function new(string name, uvm_reg_field this_field, bit lock_mode, string mode_reg_name, string mode_field_name);
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extern task pre_write(uvm_reg_item rw);
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extern function void post_predict(
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input uvm_reg_field fld,
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input uvm_reg_data_t previous,
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inout uvm_reg_data_t value,
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input uvm_predict_e kind,
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input uvm_path_e path,
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input uvm_reg_map map
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);
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extern local function void get_mode_field();
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extern local function bit not_wriable();
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endclass
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function rggen_ral_field_rwl_rwe_cbs::new(
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string name,
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uvm_reg_field this_field,
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bit lock_mode,
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string mode_reg_name,
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string mode_field_name
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);
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super.new(name);
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this.this_field = this_field;
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this.lock_mode = lock_mode;
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this.mode_reg_name = mode_reg_name;
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this.mode_field_name = mode_field_name;
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endfunction
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task rggen_ral_field_rwl_rwe_cbs::pre_write(uvm_reg_item rw);
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if ((rw.kind == UVM_WRITE) && (rw.path == UVM_BACKDOOR) && not_wriable()) begin
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rw.value[0] = this_field.get_mirrored_value();
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end
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endtask
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function void rggen_ral_field_rwl_rwe_cbs::post_predict(
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input uvm_reg_field fld,
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input uvm_reg_data_t previous,
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inout uvm_reg_data_t value,
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input uvm_predict_e kind,
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input uvm_path_e path,
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input uvm_reg_map map
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);
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if ((kind == UVM_PREDICT_WRITE) && not_wriable()) begin
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value = previous;
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end
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endfunction
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function void rggen_ral_field_rwl_rwe_cbs::get_mode_field();
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uvm_reg parent_reg;
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uvm_reg_block parent_block;
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uvm_reg mode_reg;
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parent_reg = this_field.get_parent();
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parent_block = parent_reg.get_parent();
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mode_reg = parent_block.get_reg_by_name(mode_reg_name);
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if (mode_reg == null) begin
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`uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode register: %s", mode_reg_name))
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return;
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end
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mode_field = mode_reg.get_field_by_name(mode_field_name);
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if (mode_field == null) begin
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`uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode field: %s", mode_field_name))
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return;
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end
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endfunction
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function bit rggen_ral_field_rwl_rwe_cbs::not_wriable();
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if (mode_field == null) begin
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get_mode_field();
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end
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if (lock_mode) begin
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return (mode_field.get() == 1) ? 1 : 0;
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end
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else begin
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return (mode_field.get() == 0) ? 1 : 0;
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end
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endfunction
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class rggen_ral_field_rwl_rwe extends rggen_ral_field;
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local static bit rwl_defined = define_access("RWL");
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local static bit rwe_defined = define_access("RWE");
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protected rggen_ral_field_rwl_rwe_cbs cbs;
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extern function new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
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extern function void configure(
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uvm_object cfg,
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uvm_reg parent,
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int unsigned size,
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int unsigned lsb_pos,
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string access,
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bit volatile,
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uvm_reg_data_t reset,
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bit has_reset,
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bit is_rand,
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bit individually_accessible
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);
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endclass
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function rggen_ral_field_rwl_rwe::new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
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string cbs_name;
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super.new(name);
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cbs_name = (lock_mode) ? "rwl_cbs" : "rwe_cbs";
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cbs = new(cbs_name, this, lock_mode, mode_reg_name, mode_field_name);
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endfunction
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function void rggen_ral_field_rwl_rwe::configure(
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uvm_object cfg,
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uvm_reg parent,
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int unsigned size,
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int unsigned lsb_pos,
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string access,
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bit volatile,
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uvm_reg_data_t reset,
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bit has_reset,
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bit is_rand,
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bit individually_accessible
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);
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super.configure(cfg, parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand, individually_accessible);
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uvm_reg_field_cb::add(this, cbs);
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endfunction
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class rggen_ral_field_rwl #(
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string MODE_REG_NAME = "",
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string MODE_FIELD_NAME = ""
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) extends rggen_ral_field_rwl_rwe;
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extern function new(string name = "rggen_ral_field_rwl");
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endclass
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function rggen_ral_field_rwl::new(string name);
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super.new(name, 1, MODE_REG_NAME, MODE_FIELD_NAME);
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endfunction
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class rggen_ral_field_rwe #(
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string MODE_REG_NAME = "",
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string MODE_FIELD_NAME = ""
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) extends rggen_ral_field_rwl_rwe;
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extern function new(string name = "rggen_ral_field_rwe");
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endclass
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function rggen_ral_field_rwe::new(string name);
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super.new(name, 0, MODE_REG_NAME, MODE_FIELD_NAME);
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endfunction
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`endif
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data/ral/rggen_ral_pkg.sv
CHANGED
@@ -66,6 +66,7 @@ class rggen_ral_shadow_reg_index;
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protected string reg_name;
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protected string field_name;
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protected uvm_reg_data_t value;
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protected uvm_reg index_reg;
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protected uvm_reg_field index_field;
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extern function new(
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@@ -76,18 +77,9 @@ class rggen_ral_shadow_reg_index;
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);
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extern virtual function bit is_matched();
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extern virtual
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input uvm_reg_map map = null,
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input uvm_sequence_base parent = null,
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input int prior = -1,
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input uvm_object extension = null,
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input string fname = "",
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input int lineno = 0
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);
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extern protected virtual function uvm_reg_field get_index_field();
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extern virtual function void set(string fname = "", int lineno = 0);
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extern virtual function uvm_reg get_index_reg();
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extern virtual function uvm_reg_field get_index_field();
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endclass
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function rggen_ral_shadow_reg_index::new(
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@@ -103,37 +95,31 @@ function rggen_ral_shadow_reg_index::new(
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endfunction
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function bit rggen_ral_shadow_reg_index::is_matched();
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return (
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void'(get_index_field());
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return (index_field.value == value) ? 1 : 0;
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endfunction
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input uvm_sequence_base parent,
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input int prior,
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input uvm_object extension,
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input string fname,
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input int lineno
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);
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uvm_reg_field field = get_index_field();
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uvm_reg parent_reg = field.get_parent();
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field.set(value);
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parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
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124
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-
endtask
|
125
|
-
|
126
|
-
function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
|
127
|
-
if (index_field == null) begin
|
128
|
-
uvm_reg_block parent_block = shadow_reg.get_parent();
|
129
|
-
uvm_reg index_reg;
|
102
|
+
function void rggen_ral_shadow_reg_index::set(string fname = "", int lineno = 0);
|
103
|
+
void'(get_index_field());
|
104
|
+
index_field.set(value, fname, lineno);
|
105
|
+
endfunction
|
130
106
|
|
131
|
-
|
107
|
+
function uvm_reg rggen_ral_shadow_reg_index::get_index_reg();
|
108
|
+
if (index_reg == null) begin
|
109
|
+
uvm_reg_block parent_block;
|
110
|
+
parent_block = shadow_reg.get_parent();
|
111
|
+
index_reg = parent_block.get_reg_by_name(reg_name);
|
132
112
|
if (index_reg == null) begin
|
133
113
|
`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
|
134
114
|
return null;
|
135
115
|
end
|
116
|
+
end
|
117
|
+
return index_reg;
|
118
|
+
endfunction
|
136
119
|
|
120
|
+
function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
|
121
|
+
if (index_field == null) begin
|
122
|
+
void'(get_index_reg());
|
137
123
|
index_field = index_reg.get_field_by_name(field_name);
|
138
124
|
if (index_field == null) begin
|
139
125
|
`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
|
@@ -145,10 +131,12 @@ endfunction
|
|
145
131
|
|
146
132
|
class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
|
147
133
|
protected rggen_ral_shadow_reg_index shadow_indexes[$];
|
134
|
+
protected bit index_regs[uvm_reg];
|
148
135
|
|
149
136
|
extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
|
150
137
|
|
151
138
|
extern virtual task body();
|
139
|
+
extern task update_index_regs(ref uvm_status_e status);
|
152
140
|
endclass
|
153
141
|
|
154
142
|
function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
|
@@ -159,9 +147,35 @@ function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shado
|
|
159
147
|
endfunction
|
160
148
|
|
161
149
|
task rggen_ral_shadow_reg_ftdr_seq::body();
|
150
|
+
uvm_status_e status;
|
151
|
+
update_index_regs(status);
|
152
|
+
if (status == UVM_NOT_OK) begin
|
153
|
+
`uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index registers failed")
|
154
|
+
rw_info.status = status;
|
155
|
+
return;
|
156
|
+
end
|
157
|
+
if (rw_info.kind == UVM_WRITE) begin
|
158
|
+
rw_info.local_map.do_write(rw_info);
|
159
|
+
end
|
160
|
+
else begin
|
161
|
+
rw_info.local_map.do_read(rw_info);
|
162
|
+
end
|
163
|
+
endtask
|
164
|
+
|
165
|
+
task rggen_ral_shadow_reg_ftdr_seq::update_index_regs(ref uvm_status_e status);
|
166
|
+
if (index_regs.size() == 0) begin
|
167
|
+
foreach (shadow_indexes[i]) begin
|
168
|
+
uvm_reg index_reg = shadow_indexes[i].get_index_reg();
|
169
|
+
if (!index_regs.exists(index_reg)) begin
|
170
|
+
index_regs[index_reg] = 1;
|
171
|
+
end
|
172
|
+
end
|
173
|
+
end
|
162
174
|
foreach (shadow_indexes[i]) begin
|
163
|
-
|
164
|
-
|
175
|
+
shadow_indexes[i].set(rw_info.fname, rw_info.lineno);
|
176
|
+
end
|
177
|
+
foreach (index_regs[index_reg]) begin
|
178
|
+
index_reg.update(
|
165
179
|
status,
|
166
180
|
rw_info.path,
|
167
181
|
rw_info.map,
|
@@ -172,17 +186,8 @@ task rggen_ral_shadow_reg_ftdr_seq::body();
|
|
172
186
|
rw_info.lineno
|
173
187
|
);
|
174
188
|
if (status == UVM_NOT_OK) begin
|
175
|
-
`uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
|
176
|
-
rw_info.status = status;
|
177
189
|
return;
|
178
190
|
end
|
179
191
|
end
|
180
|
-
|
181
|
-
if (rw_info.kind == UVM_WRITE) begin
|
182
|
-
rw_info.local_map.do_write(rw_info);
|
183
|
-
end
|
184
|
-
else begin
|
185
|
-
rw_info.local_map.do_read(rw_info);
|
186
|
-
end
|
187
192
|
endtask
|
188
193
|
`endif
|