rggen 0.4.1 → 0.4.2

data/lib/rggen/core_components/register_map/bit_field_factory.rb

@@ -1,9 +1,9 @@
 module RgGen
   module RegisterMap
     class BitFieldFactory < ComponentFactory
-      def create_active_items(bit_field, configuration, cells)
+      def create_active_items(bit_field, cells)
         active_item_factories.each_value.with_index do |factory, index|
-          create_item(factory, bit_field, configuration, cells[index])
+          create_item(factory, bit_field, cells[index])
         end
       end
     end

data/lib/rggen/core_components/register_map/item_factory.rb

@@ -3,7 +3,7 @@ module RgGen
     class ItemFactory < InputBase::ItemFactory
       include RaiseError
 
-      def create(component, configuration, cell = nil)
+      def create(component, cell = nil)
         convert_cell_value(cell)
         create_item(component, cell) do |item|
           item.build(cell) unless cell.nil?

data/lib/rggen/core_components/register_map/register_block_factory.rb

@@ -1,10 +1,10 @@
 module RgGen
   module RegisterMap
     class RegisterBlockFactory < ComponentFactory
-      def create_active_items(register_block, configuration, sheet)
+      def create_active_items(register_block, sheet)
         active_item_factories.each_value.with_index do |factory, index|
           cell  = sheet[index, 2]
-          create_item(factory, register_block, configuration, cell)
+          create_item(factory, register_block, cell)
         end
       end
 

data/lib/rggen/core_components/register_map/register_factory.rb

@@ -1,9 +1,9 @@
 module RgGen
   module RegisterMap
     class RegisterFactory < ComponentFactory
-      def create_active_items(register, configuration, rows)
+      def create_active_items(register, rows)
         active_item_factories.each_value.with_index do |factory, index|
-          create_item(factory, register, configuration, rows.first[index])
+          create_item(factory, register, rows.first[index])
         end
       end
 

data/lib/rggen/core_extensions/facets.rb

@@ -8,6 +8,7 @@ require 'facets/kernel/not'
 require 'facets/kernel/not_nil'
 require 'facets/module/attr_setter'
 require 'facets/numeric/positive'
+require 'facets/object/itself' unless Object.public_method_defined?(:itself)
 require 'facets/range/overlap'
 require 'facets/regexp/op_add'
 require 'facets/regexp/op_or'

data/lib/rggen/input_base/component_factory.rb

@@ -20,13 +20,13 @@ module RgGen
       private
 
       def create_items(component, *sources)
-        create_active_items(component, *sources)
-        create_passive_items(component, *sources[0..-2])
+        create_active_items(component, sources.last)
+        create_passive_items(component)
       end
 
-      def create_passive_items(component, *sources)
+      def create_passive_items(component)
         passive_item_factories.each do |factory|
-          create_item(factory, component, *sources)
+          create_item(factory, component)
         end
       end
 

data/lib/rggen/input_base/item.rb

@@ -88,6 +88,7 @@ module RgGen
       end
 
       def self.inherited(subclass)
+        super(subclass)
         [:@fields, :@builders, :@validators].each do |v|
           subclass.inherit_class_instance_variable(v, self, &:dup)
         end

data/lib/rggen/output_base/item.rb

@@ -114,6 +114,7 @@ module RgGen
       end
 
       def self.inherited(subclass)
+        super(subclass)
         [:@builders, :@exported_methods].each do |v|
           subclass.inherit_class_instance_variable(v, self, &:dup)
         end

data/lib/rggen/output_base/verilog_utility/declaration.rb

@@ -20,26 +20,24 @@ module RgGen
             width,
             identifier,
             default_value_assignment
-          ].reject(&:empty?)
+          ].select(&:itself)
         end
 
         def random_or_direction_or_parameter_type
-          case @declation_type
-          when :variable
-            (@attributes[:random] && 'rand') || ''
-          when :port
-            @attributes[:direction] || ''
-          when :parameter
-            @attributes[:parameter_type] || ''
-          end
+          {
+            variable:  @attributes[:random] && :rand,
+            port:      @attributes[:direction],
+            parameter: @attributes[:parameter_type]
+          }[@declation_type]
         end
 
         def data_type
-          @attributes[:data_type] || ''
+          @attributes[:data_type]
         end
 
         def width
-          (vector? && "[#{(@attributes[:width] || 1) - 1}:0]") || ''
+          return unless vector?
+          "[#{(@attributes[:width] || 1) - 1}:0]"
         end
 
         def identifier
@@ -47,20 +45,13 @@ module RgGen
         end
 
         def dimensions
-          return '' if @attributes[:dimensions].nil?
+          return if @attributes[:dimensions].nil?
           @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
         end
 
         def default_value_assignment
-          (@attributes[:default].nil? && '') || "= #{@attributes[:default]}"
-        end
-
-        def variable?
-          @declation_type == :variable
-        end
-
-        def port?
-          @declation_type == :port
+          return if @attributes[:default].nil?
+          "= #{@attributes[:default]}"
         end
 
         def parameter?

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
   MINOR   = 4
-  TEENY   = 1
+  TEENY   = 2
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/rggen_ral_field_rwl_rwe.svh

@@ -0,0 +1,158 @@
+`ifndef __RGGEN_RAL_FIELD_RWL_RWE_SVH__
+`define __RGGEN_RAL_FIELD_RWL_RWE_SVH__
+class rggen_ral_field_rwl_rwe_cbs extends uvm_reg_cbs;
+  local uvm_reg_field this_field;
+  local bit           lock_mode;
+  local string        mode_reg_name;
+  local string        mode_field_name;
+  local uvm_reg_field mode_field;
+
+  extern function new(string name, uvm_reg_field this_field, bit lock_mode, string mode_reg_name, string mode_field_name);
+
+  extern task pre_write(uvm_reg_item rw);
+  extern function void post_predict(
+    input uvm_reg_field   fld,
+    input uvm_reg_data_t  previous,
+    inout uvm_reg_data_t  value,
+    input uvm_predict_e   kind,
+    input uvm_path_e      path,
+    input uvm_reg_map     map
+  );
+
+  extern local function void get_mode_field();
+  extern local function bit not_wriable();
+endclass
+
+function rggen_ral_field_rwl_rwe_cbs::new(
+  string        name,
+  uvm_reg_field this_field,
+  bit           lock_mode,
+  string        mode_reg_name,
+  string        mode_field_name
+);
+  super.new(name);
+  this.this_field       = this_field;
+  this.lock_mode        = lock_mode;
+  this.mode_reg_name    = mode_reg_name;
+  this.mode_field_name  = mode_field_name;
+endfunction
+
+task rggen_ral_field_rwl_rwe_cbs::pre_write(uvm_reg_item rw);
+  if ((rw.kind == UVM_WRITE) && (rw.path == UVM_BACKDOOR) && not_wriable()) begin
+    rw.value[0] = this_field.get_mirrored_value();
+  end
+endtask
+
+function void rggen_ral_field_rwl_rwe_cbs::post_predict(
+  input uvm_reg_field   fld,
+  input uvm_reg_data_t  previous,
+  inout uvm_reg_data_t  value,
+  input uvm_predict_e   kind,
+  input uvm_path_e      path,
+  input uvm_reg_map     map
+);
+  if ((kind == UVM_PREDICT_WRITE) && not_wriable()) begin
+    value = previous;
+  end
+endfunction
+
+function void rggen_ral_field_rwl_rwe_cbs::get_mode_field();
+  uvm_reg       parent_reg;
+  uvm_reg_block parent_block;
+  uvm_reg       mode_reg;
+
+  parent_reg    = this_field.get_parent();
+  parent_block  = parent_reg.get_parent();
+
+  mode_reg  = parent_block.get_reg_by_name(mode_reg_name);
+  if (mode_reg == null) begin
+    `uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode register: %s", mode_reg_name))
+    return;
+  end
+
+  mode_field  = mode_reg.get_field_by_name(mode_field_name);
+  if (mode_field == null) begin
+    `uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode field: %s", mode_field_name))
+    return;
+  end
+endfunction
+
+function bit rggen_ral_field_rwl_rwe_cbs::not_wriable();
+  if (mode_field == null) begin
+    get_mode_field();
+  end
+  if (lock_mode) begin
+    return (mode_field.get() == 1) ? 1 : 0;
+  end
+  else begin
+    return (mode_field.get() == 0) ? 1 : 0;
+  end
+endfunction
+
+class rggen_ral_field_rwl_rwe extends rggen_ral_field;
+  local static bit  rwl_defined = define_access("RWL");
+  local static bit  rwe_defined = define_access("RWE");
+
+  protected rggen_ral_field_rwl_rwe_cbs cbs;
+
+  extern function new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
+
+  extern function void configure(
+    uvm_object      cfg,
+    uvm_reg         parent,
+    int unsigned    size,
+    int unsigned    lsb_pos,
+    string          access,
+    bit             volatile,
+    uvm_reg_data_t  reset,
+    bit             has_reset,
+    bit             is_rand,
+    bit             individually_accessible
+  );
+endclass
+
+function rggen_ral_field_rwl_rwe::new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
+  string  cbs_name;
+  super.new(name);
+  cbs_name  = (lock_mode) ? "rwl_cbs" : "rwe_cbs";
+  cbs       = new(cbs_name, this, lock_mode, mode_reg_name, mode_field_name);
+endfunction
+
+function void rggen_ral_field_rwl_rwe::configure(
+  uvm_object      cfg,
+  uvm_reg         parent,
+  int unsigned    size,
+  int unsigned    lsb_pos,
+  string          access,
+  bit             volatile,
+  uvm_reg_data_t  reset,
+  bit             has_reset,
+  bit             is_rand,
+  bit             individually_accessible
+);
+  super.configure(cfg, parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand, individually_accessible);
+  uvm_reg_field_cb::add(this, cbs);
+endfunction
+
+class rggen_ral_field_rwl #(
+  string  MODE_REG_NAME   = "",
+  string  MODE_FIELD_NAME = ""
+) extends rggen_ral_field_rwl_rwe;
+  extern function new(string name = "rggen_ral_field_rwl");
+endclass
+
+function rggen_ral_field_rwl::new(string name);
+  super.new(name, 1, MODE_REG_NAME, MODE_FIELD_NAME);
+endfunction
+
+class rggen_ral_field_rwe #(
+  string  MODE_REG_NAME   = "",
+  string  MODE_FIELD_NAME = ""
+) extends rggen_ral_field_rwl_rwe;
+  extern function new(string name = "rggen_ral_field_rwe");
+endclass
+
+function rggen_ral_field_rwe::new(string name);
+  super.new(name, 0, MODE_REG_NAME, MODE_FIELD_NAME);
+endfunction
+`endif

data/ral/rggen_ral_pkg.sv

@@ -6,6 +6,7 @@ package rggen_ral_pkg;
 
   `include  "rggen_ral_macros.svh"
   `include  "rggen_ral_field.svh"
+  `include  "rggen_ral_field_rwl_rwe.svh"
   `include  "rggen_ral_reg.svh"
   `include  "rggen_ral_shadow_reg.svh"
   `include  "rggen_ral_map.svh"

data/ral/rggen_ral_shadow_reg.svh

@@ -66,6 +66,7 @@ class rggen_ral_shadow_reg_index;
   protected string                reg_name;
   protected string                field_name;
   protected uvm_reg_data_t        value;
+  protected uvm_reg               index_reg;
   protected uvm_reg_field         index_field;
 
   extern function new(
@@ -76,18 +77,9 @@ class rggen_ral_shadow_reg_index;
   );
 
   extern virtual function bit is_matched();
-  extern virtual task update(
-    output  uvm_status_e      status,
-    input   uvm_path_e        path      = UVM_DEFAULT_PATH,
-    input   uvm_reg_map       map       = null,
-    input   uvm_sequence_base parent    = null,
-    input   int               prior     = -1,
-    input   uvm_object        extension = null,
-    input   string            fname     = "",
-    input   int               lineno    = 0
-  );
-
-  extern protected virtual function uvm_reg_field get_index_field();
+  extern virtual function void set(string fname = "", int lineno = 0);
+  extern virtual function uvm_reg get_index_reg();
+  extern virtual function uvm_reg_field get_index_field();
 endclass
 
 function rggen_ral_shadow_reg_index::new(
@@ -103,37 +95,31 @@ function rggen_ral_shadow_reg_index::new(
 endfunction
 
 function bit rggen_ral_shadow_reg_index::is_matched();
-  uvm_reg_field field = get_index_field();
-  return (field.value == value) ? 1 : 0;
+  void'(get_index_field());
+  return (index_field.value == value) ? 1 : 0;
 endfunction
 
-task rggen_ral_shadow_reg_index::update(
-  output  uvm_status_e      status,
-  input   uvm_path_e        path,
-  input   uvm_reg_map       map,
-  input   uvm_sequence_base parent,
-  input   int               prior,
-  input   uvm_object        extension,
-  input   string            fname,
-  input   int               lineno
-);
-  uvm_reg_field field       = get_index_field();
-  uvm_reg       parent_reg  = field.get_parent();
-  field.set(value);
-  parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
-endtask
-
-function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
-  if (index_field == null) begin
-    uvm_reg_block parent_block  = shadow_reg.get_parent();
-    uvm_reg       index_reg;
+function void rggen_ral_shadow_reg_index::set(string fname = "", int lineno = 0);
+  void'(get_index_field());
+  index_field.set(value, fname, lineno);
+endfunction
 
-    index_reg = parent_block.get_reg_by_name(reg_name);
+function uvm_reg rggen_ral_shadow_reg_index::get_index_reg();
+  if (index_reg == null) begin
+    uvm_reg_block parent_block;
+    parent_block  = shadow_reg.get_parent();
+    index_reg     = parent_block.get_reg_by_name(reg_name);
     if (index_reg == null) begin
       `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
       return null;
     end
+  end
+  return index_reg;
+endfunction
 
+function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
+  if (index_field == null) begin
+    void'(get_index_reg());
     index_field = index_reg.get_field_by_name(field_name);
     if (index_field == null) begin
       `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
@@ -145,10 +131,12 @@ endfunction
 
 class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
   protected rggen_ral_shadow_reg_index  shadow_indexes[$];
+  protected bit                         index_regs[uvm_reg];
 
   extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
 
   extern virtual task body();
+  extern task update_index_regs(ref uvm_status_e status);
 endclass
 
 function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
@@ -159,9 +147,35 @@ function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shado
 endfunction
 
 task rggen_ral_shadow_reg_ftdr_seq::body();
+  uvm_status_e  status;
+  update_index_regs(status);
+  if (status == UVM_NOT_OK) begin
+    `uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index registers failed")
+    rw_info.status  = status;
+    return;
+  end
+  if (rw_info.kind == UVM_WRITE) begin
+    rw_info.local_map.do_write(rw_info);
+  end
+  else begin
+    rw_info.local_map.do_read(rw_info);
+  end
+endtask
+
+task rggen_ral_shadow_reg_ftdr_seq::update_index_regs(ref uvm_status_e status);
+  if (index_regs.size() == 0) begin
+    foreach (shadow_indexes[i]) begin
+      uvm_reg index_reg = shadow_indexes[i].get_index_reg();
+      if (!index_regs.exists(index_reg)) begin
+        index_regs[index_reg] = 1;
+      end
+    end
+  end
   foreach (shadow_indexes[i]) begin
-    uvm_status_e  status;
-    shadow_indexes[i].update(
+    shadow_indexes[i].set(rw_info.fname, rw_info.lineno);
+  end
+  foreach (index_regs[index_reg]) begin
+    index_reg.update(
       status,
       rw_info.path,
       rw_info.map,
@@ -172,17 +186,8 @@ task rggen_ral_shadow_reg_ftdr_seq::body();
       rw_info.lineno
     );
     if (status == UVM_NOT_OK) begin
-      `uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
-      rw_info.status  = status;
       return;
     end
   end
-
-  if (rw_info.kind == UVM_WRITE) begin
-    rw_info.local_map.do_write(rw_info);
-  end
-  else begin
-    rw_info.local_map.do_read(rw_info);
-  end
 endtask
 `endif