rggen 0.4.1 → 0.4.2

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@@ -1,9 +1,9 @@
1
1
  module RgGen
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2
  module RegisterMap
3
3
  class BitFieldFactory < ComponentFactory
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- def create_active_items(bit_field, configuration, cells)
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+ def create_active_items(bit_field, cells)
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  active_item_factories.each_value.with_index do |factory, index|
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- create_item(factory, bit_field, configuration, cells[index])
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+ create_item(factory, bit_field, cells[index])
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  end
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  end
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  end
@@ -3,7 +3,7 @@ module RgGen
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  class ItemFactory < InputBase::ItemFactory
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  include RaiseError
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5
 
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- def create(component, configuration, cell = nil)
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+ def create(component, cell = nil)
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  convert_cell_value(cell)
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  create_item(component, cell) do |item|
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  item.build(cell) unless cell.nil?
@@ -1,10 +1,10 @@
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  module RgGen
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  module RegisterMap
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  class RegisterBlockFactory < ComponentFactory
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- def create_active_items(register_block, configuration, sheet)
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+ def create_active_items(register_block, sheet)
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  active_item_factories.each_value.with_index do |factory, index|
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  cell = sheet[index, 2]
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- create_item(factory, register_block, configuration, cell)
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+ create_item(factory, register_block, cell)
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  end
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  end
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@@ -1,9 +1,9 @@
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  module RgGen
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  module RegisterMap
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  class RegisterFactory < ComponentFactory
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- def create_active_items(register, configuration, rows)
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+ def create_active_items(register, rows)
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  active_item_factories.each_value.with_index do |factory, index|
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- create_item(factory, register, configuration, rows.first[index])
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+ create_item(factory, register, rows.first[index])
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  end
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  end
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@@ -8,6 +8,7 @@ require 'facets/kernel/not'
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  require 'facets/kernel/not_nil'
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  require 'facets/module/attr_setter'
10
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  require 'facets/numeric/positive'
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+ require 'facets/object/itself' unless Object.public_method_defined?(:itself)
11
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  require 'facets/range/overlap'
12
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  require 'facets/regexp/op_add'
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  require 'facets/regexp/op_or'
@@ -20,13 +20,13 @@ module RgGen
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  private
21
21
 
22
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  def create_items(component, *sources)
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- create_active_items(component, *sources)
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- create_passive_items(component, *sources[0..-2])
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+ create_active_items(component, sources.last)
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+ create_passive_items(component)
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  end
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26
 
27
- def create_passive_items(component, *sources)
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+ def create_passive_items(component)
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  passive_item_factories.each do |factory|
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- create_item(factory, component, *sources)
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+ create_item(factory, component)
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  end
31
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  end
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32
 
@@ -88,6 +88,7 @@ module RgGen
88
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  end
89
89
 
90
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  def self.inherited(subclass)
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+ super(subclass)
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  [:@fields, :@builders, :@validators].each do |v|
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  subclass.inherit_class_instance_variable(v, self, &:dup)
93
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  end
@@ -114,6 +114,7 @@ module RgGen
114
114
  end
115
115
 
116
116
  def self.inherited(subclass)
117
+ super(subclass)
117
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  [:@builders, :@exported_methods].each do |v|
118
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  subclass.inherit_class_instance_variable(v, self, &:dup)
119
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  end
@@ -20,26 +20,24 @@ module RgGen
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  width,
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  identifier,
22
22
  default_value_assignment
23
- ].reject(&:empty?)
23
+ ].select(&:itself)
24
24
  end
25
25
 
26
26
  def random_or_direction_or_parameter_type
27
- case @declation_type
28
- when :variable
29
- (@attributes[:random] && 'rand') || ''
30
- when :port
31
- @attributes[:direction] || ''
32
- when :parameter
33
- @attributes[:parameter_type] || ''
34
- end
27
+ {
28
+ variable: @attributes[:random] && :rand,
29
+ port: @attributes[:direction],
30
+ parameter: @attributes[:parameter_type]
31
+ }[@declation_type]
35
32
  end
36
33
 
37
34
  def data_type
38
- @attributes[:data_type] || ''
35
+ @attributes[:data_type]
39
36
  end
40
37
 
41
38
  def width
42
- (vector? && "[#{(@attributes[:width] || 1) - 1}:0]") || ''
39
+ return unless vector?
40
+ "[#{(@attributes[:width] || 1) - 1}:0]"
43
41
  end
44
42
 
45
43
  def identifier
@@ -47,20 +45,13 @@ module RgGen
47
45
  end
48
46
 
49
47
  def dimensions
50
- return '' if @attributes[:dimensions].nil?
48
+ return if @attributes[:dimensions].nil?
51
49
  @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
52
50
  end
53
51
 
54
52
  def default_value_assignment
55
- (@attributes[:default].nil? && '') || "= #{@attributes[:default]}"
56
- end
57
-
58
- def variable?
59
- @declation_type == :variable
60
- end
61
-
62
- def port?
63
- @declation_type == :port
53
+ return if @attributes[:default].nil?
54
+ "= #{@attributes[:default]}"
64
55
  end
65
56
 
66
57
  def parameter?
data/lib/rggen/version.rb CHANGED
@@ -1,6 +1,6 @@
1
1
  module RgGen
2
2
  MAJOR = 0
3
3
  MINOR = 4
4
- TEENY = 1
4
+ TEENY = 2
5
5
  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
6
6
  end
@@ -0,0 +1,158 @@
1
+ `ifndef __RGGEN_RAL_FIELD_RWL_RWE_SVH__
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+ `define __RGGEN_RAL_FIELD_RWL_RWE_SVH__
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+ class rggen_ral_field_rwl_rwe_cbs extends uvm_reg_cbs;
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+ local uvm_reg_field this_field;
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+ local bit lock_mode;
6
+ local string mode_reg_name;
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+ local string mode_field_name;
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+ local uvm_reg_field mode_field;
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+
10
+ extern function new(string name, uvm_reg_field this_field, bit lock_mode, string mode_reg_name, string mode_field_name);
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+
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+ extern task pre_write(uvm_reg_item rw);
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+ extern function void post_predict(
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+ input uvm_reg_field fld,
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+ input uvm_reg_data_t previous,
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+ inout uvm_reg_data_t value,
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+ input uvm_predict_e kind,
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+ input uvm_path_e path,
19
+ input uvm_reg_map map
20
+ );
21
+
22
+ extern local function void get_mode_field();
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+ extern local function bit not_wriable();
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+ endclass
25
+
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+ function rggen_ral_field_rwl_rwe_cbs::new(
27
+ string name,
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+ uvm_reg_field this_field,
29
+ bit lock_mode,
30
+ string mode_reg_name,
31
+ string mode_field_name
32
+ );
33
+ super.new(name);
34
+ this.this_field = this_field;
35
+ this.lock_mode = lock_mode;
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+ this.mode_reg_name = mode_reg_name;
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+ this.mode_field_name = mode_field_name;
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+ endfunction
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+
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+ task rggen_ral_field_rwl_rwe_cbs::pre_write(uvm_reg_item rw);
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+ if ((rw.kind == UVM_WRITE) && (rw.path == UVM_BACKDOOR) && not_wriable()) begin
42
+ rw.value[0] = this_field.get_mirrored_value();
43
+ end
44
+ endtask
45
+
46
+ function void rggen_ral_field_rwl_rwe_cbs::post_predict(
47
+ input uvm_reg_field fld,
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+ input uvm_reg_data_t previous,
49
+ inout uvm_reg_data_t value,
50
+ input uvm_predict_e kind,
51
+ input uvm_path_e path,
52
+ input uvm_reg_map map
53
+ );
54
+ if ((kind == UVM_PREDICT_WRITE) && not_wriable()) begin
55
+ value = previous;
56
+ end
57
+ endfunction
58
+
59
+ function void rggen_ral_field_rwl_rwe_cbs::get_mode_field();
60
+ uvm_reg parent_reg;
61
+ uvm_reg_block parent_block;
62
+ uvm_reg mode_reg;
63
+
64
+ parent_reg = this_field.get_parent();
65
+ parent_block = parent_reg.get_parent();
66
+
67
+ mode_reg = parent_block.get_reg_by_name(mode_reg_name);
68
+ if (mode_reg == null) begin
69
+ `uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode register: %s", mode_reg_name))
70
+ return;
71
+ end
72
+
73
+ mode_field = mode_reg.get_field_by_name(mode_field_name);
74
+ if (mode_field == null) begin
75
+ `uvm_fatal("rggen_ral_field_rwl_rwe_cbs", $sformatf("Unable to locate the mode field: %s", mode_field_name))
76
+ return;
77
+ end
78
+ endfunction
79
+
80
+ function bit rggen_ral_field_rwl_rwe_cbs::not_wriable();
81
+ if (mode_field == null) begin
82
+ get_mode_field();
83
+ end
84
+ if (lock_mode) begin
85
+ return (mode_field.get() == 1) ? 1 : 0;
86
+ end
87
+ else begin
88
+ return (mode_field.get() == 0) ? 1 : 0;
89
+ end
90
+ endfunction
91
+
92
+ class rggen_ral_field_rwl_rwe extends rggen_ral_field;
93
+ local static bit rwl_defined = define_access("RWL");
94
+ local static bit rwe_defined = define_access("RWE");
95
+
96
+ protected rggen_ral_field_rwl_rwe_cbs cbs;
97
+
98
+ extern function new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
99
+
100
+ extern function void configure(
101
+ uvm_object cfg,
102
+ uvm_reg parent,
103
+ int unsigned size,
104
+ int unsigned lsb_pos,
105
+ string access,
106
+ bit volatile,
107
+ uvm_reg_data_t reset,
108
+ bit has_reset,
109
+ bit is_rand,
110
+ bit individually_accessible
111
+ );
112
+ endclass
113
+
114
+ function rggen_ral_field_rwl_rwe::new(string name, bit lock_mode, string mode_reg_name, string mode_field_name);
115
+ string cbs_name;
116
+ super.new(name);
117
+ cbs_name = (lock_mode) ? "rwl_cbs" : "rwe_cbs";
118
+ cbs = new(cbs_name, this, lock_mode, mode_reg_name, mode_field_name);
119
+ endfunction
120
+
121
+ function void rggen_ral_field_rwl_rwe::configure(
122
+ uvm_object cfg,
123
+ uvm_reg parent,
124
+ int unsigned size,
125
+ int unsigned lsb_pos,
126
+ string access,
127
+ bit volatile,
128
+ uvm_reg_data_t reset,
129
+ bit has_reset,
130
+ bit is_rand,
131
+ bit individually_accessible
132
+ );
133
+ super.configure(cfg, parent, size, lsb_pos, access, volatile, reset, has_reset, is_rand, individually_accessible);
134
+ uvm_reg_field_cb::add(this, cbs);
135
+ endfunction
136
+
137
+ class rggen_ral_field_rwl #(
138
+ string MODE_REG_NAME = "",
139
+ string MODE_FIELD_NAME = ""
140
+ ) extends rggen_ral_field_rwl_rwe;
141
+ extern function new(string name = "rggen_ral_field_rwl");
142
+ endclass
143
+
144
+ function rggen_ral_field_rwl::new(string name);
145
+ super.new(name, 1, MODE_REG_NAME, MODE_FIELD_NAME);
146
+ endfunction
147
+
148
+ class rggen_ral_field_rwe #(
149
+ string MODE_REG_NAME = "",
150
+ string MODE_FIELD_NAME = ""
151
+ ) extends rggen_ral_field_rwl_rwe;
152
+ extern function new(string name = "rggen_ral_field_rwe");
153
+ endclass
154
+
155
+ function rggen_ral_field_rwe::new(string name);
156
+ super.new(name, 0, MODE_REG_NAME, MODE_FIELD_NAME);
157
+ endfunction
158
+ `endif
data/ral/rggen_ral_pkg.sv CHANGED
@@ -6,6 +6,7 @@ package rggen_ral_pkg;
6
6
 
7
7
  `include "rggen_ral_macros.svh"
8
8
  `include "rggen_ral_field.svh"
9
+ `include "rggen_ral_field_rwl_rwe.svh"
9
10
  `include "rggen_ral_reg.svh"
10
11
  `include "rggen_ral_shadow_reg.svh"
11
12
  `include "rggen_ral_map.svh"
@@ -66,6 +66,7 @@ class rggen_ral_shadow_reg_index;
66
66
  protected string reg_name;
67
67
  protected string field_name;
68
68
  protected uvm_reg_data_t value;
69
+ protected uvm_reg index_reg;
69
70
  protected uvm_reg_field index_field;
70
71
 
71
72
  extern function new(
@@ -76,18 +77,9 @@ class rggen_ral_shadow_reg_index;
76
77
  );
77
78
 
78
79
  extern virtual function bit is_matched();
79
- extern virtual task update(
80
- output uvm_status_e status,
81
- input uvm_path_e path = UVM_DEFAULT_PATH,
82
- input uvm_reg_map map = null,
83
- input uvm_sequence_base parent = null,
84
- input int prior = -1,
85
- input uvm_object extension = null,
86
- input string fname = "",
87
- input int lineno = 0
88
- );
89
-
90
- extern protected virtual function uvm_reg_field get_index_field();
80
+ extern virtual function void set(string fname = "", int lineno = 0);
81
+ extern virtual function uvm_reg get_index_reg();
82
+ extern virtual function uvm_reg_field get_index_field();
91
83
  endclass
92
84
 
93
85
  function rggen_ral_shadow_reg_index::new(
@@ -103,37 +95,31 @@ function rggen_ral_shadow_reg_index::new(
103
95
  endfunction
104
96
 
105
97
  function bit rggen_ral_shadow_reg_index::is_matched();
106
- uvm_reg_field field = get_index_field();
107
- return (field.value == value) ? 1 : 0;
98
+ void'(get_index_field());
99
+ return (index_field.value == value) ? 1 : 0;
108
100
  endfunction
109
101
 
110
- task rggen_ral_shadow_reg_index::update(
111
- output uvm_status_e status,
112
- input uvm_path_e path,
113
- input uvm_reg_map map,
114
- input uvm_sequence_base parent,
115
- input int prior,
116
- input uvm_object extension,
117
- input string fname,
118
- input int lineno
119
- );
120
- uvm_reg_field field = get_index_field();
121
- uvm_reg parent_reg = field.get_parent();
122
- field.set(value);
123
- parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
124
- endtask
125
-
126
- function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
127
- if (index_field == null) begin
128
- uvm_reg_block parent_block = shadow_reg.get_parent();
129
- uvm_reg index_reg;
102
+ function void rggen_ral_shadow_reg_index::set(string fname = "", int lineno = 0);
103
+ void'(get_index_field());
104
+ index_field.set(value, fname, lineno);
105
+ endfunction
130
106
 
131
- index_reg = parent_block.get_reg_by_name(reg_name);
107
+ function uvm_reg rggen_ral_shadow_reg_index::get_index_reg();
108
+ if (index_reg == null) begin
109
+ uvm_reg_block parent_block;
110
+ parent_block = shadow_reg.get_parent();
111
+ index_reg = parent_block.get_reg_by_name(reg_name);
132
112
  if (index_reg == null) begin
133
113
  `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
134
114
  return null;
135
115
  end
116
+ end
117
+ return index_reg;
118
+ endfunction
136
119
 
120
+ function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
121
+ if (index_field == null) begin
122
+ void'(get_index_reg());
137
123
  index_field = index_reg.get_field_by_name(field_name);
138
124
  if (index_field == null) begin
139
125
  `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
@@ -145,10 +131,12 @@ endfunction
145
131
 
146
132
  class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
147
133
  protected rggen_ral_shadow_reg_index shadow_indexes[$];
134
+ protected bit index_regs[uvm_reg];
148
135
 
149
136
  extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
150
137
 
151
138
  extern virtual task body();
139
+ extern task update_index_regs(ref uvm_status_e status);
152
140
  endclass
153
141
 
154
142
  function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
@@ -159,9 +147,35 @@ function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shado
159
147
  endfunction
160
148
 
161
149
  task rggen_ral_shadow_reg_ftdr_seq::body();
150
+ uvm_status_e status;
151
+ update_index_regs(status);
152
+ if (status == UVM_NOT_OK) begin
153
+ `uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index registers failed")
154
+ rw_info.status = status;
155
+ return;
156
+ end
157
+ if (rw_info.kind == UVM_WRITE) begin
158
+ rw_info.local_map.do_write(rw_info);
159
+ end
160
+ else begin
161
+ rw_info.local_map.do_read(rw_info);
162
+ end
163
+ endtask
164
+
165
+ task rggen_ral_shadow_reg_ftdr_seq::update_index_regs(ref uvm_status_e status);
166
+ if (index_regs.size() == 0) begin
167
+ foreach (shadow_indexes[i]) begin
168
+ uvm_reg index_reg = shadow_indexes[i].get_index_reg();
169
+ if (!index_regs.exists(index_reg)) begin
170
+ index_regs[index_reg] = 1;
171
+ end
172
+ end
173
+ end
162
174
  foreach (shadow_indexes[i]) begin
163
- uvm_status_e status;
164
- shadow_indexes[i].update(
175
+ shadow_indexes[i].set(rw_info.fname, rw_info.lineno);
176
+ end
177
+ foreach (index_regs[index_reg]) begin
178
+ index_reg.update(
165
179
  status,
166
180
  rw_info.path,
167
181
  rw_info.map,
@@ -172,17 +186,8 @@ task rggen_ral_shadow_reg_ftdr_seq::body();
172
186
  rw_info.lineno
173
187
  );
174
188
  if (status == UVM_NOT_OK) begin
175
- `uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
176
- rw_info.status = status;
177
189
  return;
178
190
  end
179
191
  end
180
-
181
- if (rw_info.kind == UVM_WRITE) begin
182
- rw_info.local_map.do_write(rw_info);
183
- end
184
- else begin
185
- rw_info.local_map.do_read(rw_info);
186
- end
187
192
  endtask
188
193
  `endif