rggen 0.4.0 → 0.4.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 33c2428ac880c98ecf68e103721e0decec844892
-  data.tar.gz: e2c208ee59c2c860aeadcde867e69a95336c78b7
+  metadata.gz: 2396e3bda75fed6482252aa77cb4b4173876357d
+  data.tar.gz: d8eaa7e4be192d6e904e3ba59a279213adf46b27
 SHA512:
-  metadata.gz: bf5a199dd488d76174bc36d3b758d4df1af53ded4bd5513c8c0d00f297e4c8f183ef9364c9a23663385c82c6466483ee3803aa654fe96ee2f9d0d7d116e810f5
-  data.tar.gz: 6acdf0c8e0e223c69ee547a15db390221622c4c29e8d1d5ac0efc3589f8e483b4ea8ee79f4c2be02588997913ad630c99594677175d9552c0c54e46909989cfc
+  metadata.gz: 54fb50cd74efae359260ff966c274ab31777e30ff212084f731ea77928df348faa9d97e92e4e735f4c9e04db1d9115baaa6189e7240f5a92f2ae61126957e529
+  data.tar.gz: c5cf3cf847bedc4bdf68a2fb372b641d0b4a0735e002e5cf6654eb2c1bf4b3a3d16e269d78228fe497e86a519d7b6089c8e1f598dc5ac765ecd1f8950383c8e7

data/README.md

@@ -59,20 +59,24 @@ In addition, if you use default values for all of attributes, you don't need to
 RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
 To do this, you need to write your register map document according to below table format.
 
-|    |A   |B             |C            |D              |E                                |F       |G             |H         |I   |J           |
-|:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------|:-------------|:---------|:---|:-----------|
-|1   |    |Block Name    |block_0      |               |                                 |        |              |          |    |            |
-|2   |    |Byte Size     |256          |               |                                 |        |              |          |    |            |
-|3   |    |              |             |               |                                 |        |              |          |    |            |
-|4   |    |Offset Address|Register Name|Array Dimension|Shadow Index                     |External|Bit Assignment|Field Name|Type|Iitial Value|
-|5   |    |0x00          |register_0   |               |                                 |        |[31:16]       |field_0_0 |rw  |0           |
-|6   |    |              |             |               |                                 |        |[15:0]        |field_0_1 |rw  |0           |
-|7   |    |0x04          |register_1   |               |                                 |        |[16]          |field_1_0 |rw  |0           |
-|8   |    |              |             |               |                                 |        |[0]           |field_1_1 |ro  |            |
-|9   |    |0x10 - 0x1F   |register_2   |[4]            |                                 |        |[7:0]         |field_2_0 |rw  |0           |
-|10  |    |0x20 - 0x3F   |register_3   |               |                                 |true    |              |          |    |            |
-|11  |    |0x40          |register_4   |[2, 4]         |field_1_0:1, field_0_0, field_0_1|        |[7:0]         |field_4_0 |rw  |0           |
-
+|    |A   |B             |C            |D              |E                                |F       |G             |H         |I   |J           |K        |
+|:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------|:-------------|:---------|:---|:-----------|:--------|
+|1   |    |Block Name    |block_0      |               |                                 |        |              |          |    |            |         |
+|2   |    |Byte Size     |256          |               |                                 |        |              |          |    |            |         |
+|3   |    |              |             |               |                                 |        |              |          |    |            |         |
+|4   |    |Offset Address|Register Name|Array Dimension|Shadow Index                     |External|Bit Assignment|Field Name|Type|Iitial Value|Reference|
+|5   |    |0x00          |register_0   |               |                                 |        |[31:16]       |field_0_0 |rw  |0           |         |
+|6   |    |              |             |               |                                 |        |[15:0]        |field_0_1 |rw  |0           |         |
+|7   |    |0x04          |register_1   |               |                                 |        |[16]          |field_1_0 |rw  |0           |         |
+|8   |    |              |             |               |                                 |        |[0]           |field_1_1 |ro  |            |         |
+|9   |    |0x10 - 0x1F   |register_2   |[4]            |                                 |        |[7:0]         |field_2_0 |rw  |0           |         |
+|10  |    |0x20 - 0x3F   |register_3   |               |                                 |true    |              |          |    |            |         |
+|11  |    |0x40          |register_4   |[2, 4]         |field_1_0:1, field_0_0, field_0_1|        |[7:0]         |field_4_0 |rw  |0           |         |
+|12  |    |0x44          |register_5   |               |                                 |        |[8]           |field_5_0 |w0s |0           |         |
+|13  |    |              |             |               |                                 |        |[0]           |field_5_1 |w1s |0           |         |
+|14  |    |0x48          |register_6   |               |                                 |        |[8]           |field_6_0 |w0c |0           |field_1_0|
+|15  |    |              |             |               |                                 |        |[0]           |field_6_1 |w1c |0           |field_1_0|
+
 By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
 
 ### Generating Source Code

data/lib/rggen/builder/category.rb

@@ -11,12 +11,23 @@ module RgGen
         define_definition_method(component_name)
       end
 
-      def define_simple_item(item_name, &body)
-        do_definition(:define_simple_item, item_name, &body)
+      def define_simple_item(item_name_or_names, &body)
+        Array(item_name_or_names).each do |item_name|
+          do_definition(:define_simple_item, item_name, &body)
+        end
       end
 
-      def define_list_item(list_name, item_name = nil, &body)
-        do_definition(:define_list_item, list_name, item_name, &body)
+      def define_list_item(list_name_or_names, item_name_or_names = nil, &body)
+        if item_name_or_names.nil?
+          Array(list_name_or_names).each do |list_name|
+            do_definition(:define_list_item, list_name, nil, &body)
+          end
+        else
+          list_name = list_name_or_names
+          Array(item_name_or_names).each do |item_name|
+            do_definition(:define_list_item, list_name, item_name, &body)
+          end
+        end
       end
 
       def shared_context(&body)

data/lib/rggen/builtins.rb

@@ -15,6 +15,8 @@ require_relative 'builtins/bit_field/reference'
 require_relative 'builtins/bit_field/type'
 require_relative 'builtins/bit_field/rw'
 require_relative 'builtins/bit_field/ro'
+require_relative 'builtins/bit_field/w0c_w1c'
+require_relative 'builtins/bit_field/w0s_w1s'
 require_relative 'builtins/bit_field/wo'
 require_relative 'builtins/bit_field/reserved'
 
@@ -43,6 +45,7 @@ require_relative 'builtins/register_block/default_map_creator'
 require_relative 'builtins/register_block/host_if'
 require_relative 'builtins/register_block/apb'
 require_relative 'builtins/register_block/axi4lite'
+require_relative 'builtins/register_block/irq_controller'
 require_relative 'builtins/register_block/name'
 require_relative 'builtins/register_block/ral_package'
 require_relative 'builtins/register_block/response_mux'

data/lib/rggen/builtins/bit_field/field_model.rb

@@ -12,11 +12,11 @@ simple_item :bit_field, :field_model do
     end
 
     def model_creation(code)
-      code << "`rggen_ral_create_field_model(#{arguments.join(', ')})" << nl
+      code << subroutine_call('`rggen_ral_create_field_model', arguments) << nl
     end
 
     def arguments
-      [name, string(name), width, lsb, access, volatile, reset, has_reset]
+      [name, string(name), width, lsb, access, volatile, reset, has_reset, hdl_path]
     end
 
     def volatile
@@ -30,5 +30,9 @@ simple_item :bit_field, :field_model do
     def has_reset
       (bit_field.initial_value? && 1) || 0
     end
+
+    def hdl_path
+      string(bit_field.hdl_path)
+    end
   end
 end

data/lib/rggen/builtins/bit_field/reserved.rb

@@ -5,5 +5,6 @@ list_item :bit_field, :type, :reserved  do
 
   ral do
     access :ro
+    hdl_path { '' }
   end
 end

data/lib/rggen/builtins/bit_field/ro.erb

@@ -0,0 +1,6 @@
+rggen_bit_field_ro #(
+  .WIDTH  (<%= width %>)
+) u_<%= bit_field.name %> (
+  .i_value  (<%= value_in[loop_variables] %>),
+  .o_value  (<%= value[loop_variables] %>)
+);

data/lib/rggen/builtins/bit_field/ro.rb

@@ -5,15 +5,16 @@ list_item :bit_field, :type, :ro do
 
   rtl do
     build do
-      input :value_in, name: port_name, width: width, dimensions: dimensions
+      input :value_in,
+            name:       "i_#{bit_field.name}",
+            width:      width,
+            dimensions: dimensions
     end
 
-    generate_code :module_item do |buffer|
-      buffer << assign(value[loop_variables], value_in[loop_variables]) << nl
-    end
+    generate_code_from_template :module_item
+  end
 
-    def port_name
-      "i_#{bit_field.name}"
-    end
+  ral do
+    hdl_path { "u_#{bit_field.name}.i_value" }
   end
 end

data/lib/rggen/builtins/bit_field/type.rb

@@ -70,6 +70,10 @@ list_item :bit_field, :type do
         def same_width
           :same_width
         end
+
+        def irq?(&body)
+          define_method(:irq?, &body)
+        end
       end
 
       field :type
@@ -78,6 +82,7 @@ list_item :bit_field, :type do
       field :read_only? , forward_to_helper: true
       field :write_only?, forward_to_helper: true
       field :reserved?  , forward_to_helper: true
+      field :irq?       , default:           false
 
       class_delegator :full_width
       class_delegator :need_initial_value?
@@ -188,14 +193,23 @@ list_item :bit_field, :type do
   ral do
     item_base do
       export :access
+      export :hdl_path
 
       define_helpers do
         attr_setter :access
+
+        def hdl_path(&body)
+          define_method(:hdl_path, &body)
+        end
       end
 
       def access
         string((self.class.access || bit_field.type).to_s.upcase)
       end
+
+      def hdl_path
+        "u_#{bit_field.name}.value"
+      end
     end
 
     default_item do

data/lib/rggen/builtins/bit_field/w0c_w1c.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_w0c_w1c #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .CLEAR_VALUE    (<%= clear_value %>)
+) u_<%= name%> (
+  .clk              (<%= register_block.clock %>),
+  .rst_n            (<%= register_block.reset %>),
+  .i_set            (<%= set[loop_variables] %>),
+  .i_command_valid  (<%= register_block.host_if.command_valid %>),
+  .i_select         (<%= register_block.register_select[index] %>),
+  .i_write          (<%= register_block.host_if.write %>),
+  .i_write_data     (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
+  .i_write_mask     (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
+  .o_value          (<%= value[loop_variables] %>)
+);

data/lib/rggen/builtins/bit_field/w0c_w1c.rb

@@ -0,0 +1,26 @@
+list_item :bit_field, :type, [:w0c, :w1c] do
+  register_map do
+    read_write
+    need_initial_value
+    use_reference width: same_width
+    irq? { bit_field.has_reference? }
+  end
+
+  rtl do
+    delegate [:name, :type] => :bit_field
+
+    build do
+      input :set, name: "i_#{name}_set", width: width, dimensions: dimensions
+    end
+
+    generate_code_from_template :module_item
+
+    def initial_value
+      hex(bit_field.initial_value, width)
+    end
+
+    def clear_value
+      bin({ w0c: 0, w1c: 1 }[type], 1)
+    end
+  end
+end

data/lib/rggen/builtins/bit_field/w0s_w1s.erb

@@ -0,0 +1,15 @@
+rggen_bit_field_w0s_w1s #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SET_VALUE      (<%= set_value %>)
+) u_<%= name %> (
+  .clk              (<%= register_block.clock %>),
+  .rst_n            (<%= register_block.reset %>),
+  .i_clear          (<%= clear[loop_variables] %>),
+  .i_command_valid  (<%= register_block.host_if.command_valid %>),
+  .i_select         (<%= register_block.register_select[index] %>),
+  .i_write          (<%= register_block.host_if.write %>),
+  .i_write_data     (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
+  .i_write_mask     (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
+  .o_value          (<%= value[loop_variables] %>)
+);

data/lib/rggen/builtins/bit_field/w0s_w1s.rb

@@ -0,0 +1,34 @@
+list_item :bit_field, :type, [:w0s, :w1s] do
+  register_map do
+    read_write
+    need_initial_value
+  end
+
+  rtl do
+    delegate [:name, :type] => :bit_field
+
+    build do
+      output :value_out,
+             name:      "o_#{name}",
+             width:      width,
+             dimensions: dimensions
+       input :clear,
+             name:       "i_#{name}_clear",
+             width:      width,
+             dimensions: dimensions
+    end
+
+    generate_code :module_item do |code|
+      code << assign(value_out[loop_variables], value[loop_variables]) << nl
+      code << process_template
+    end
+
+    def initial_value
+      hex(bit_field.initial_value, width)
+    end
+
+    def set_value
+      bin({ w0s: 0, w1s: 1 }[type], 1)
+    end
+  end
+end

data/lib/rggen/builtins/register/address_decoder.erb

@@ -1,6 +1,4 @@
 rggen_address_decoder #(
-  .READABLE           (<%= readable %>),
-  .WRITABLE           (<%= writable %>),
   .ADDRESS_WIDTH      (<%= local_address_width - address_lsb %>),
   .START_ADDRESS      (<%= start_address%>),
   .END_ADDRESS        (<%= end_address %>),

data/lib/rggen/builtins/register/address_decoder.rb

@@ -17,14 +17,6 @@ simple_item :register, :address_decoder do
     delegate [:array?, :shadow?, :multiple?] => :register
     delegate [:shadow_indexes, :loop_variables] => :register
 
-    def readable
-      ((register.readable? || register.reserved?) && 1) || 0
-    end
-
-    def writable
-      ((register.writable? || register.reserved?) && 1) || 0
-    end
-
     def address_lsb
       Math.clog2(configuration.byte_width)
     end

data/lib/rggen/builtins/register/reg_model.rb

@@ -26,7 +26,7 @@ simple_item :register, :reg_model do
 
     def model_creation(code)
       foreach_header(code) if array?
-      code << "`rggen_ral_create_reg_model(#{arguments.join(', ')})" << nl
+      code << subroutine_call('`rggen_ral_create_reg_model', arguments) << nl
       foreach_footer(code) if array?
     end
 
@@ -41,13 +41,21 @@ simple_item :register, :reg_model do
     end
 
     def arguments
-      [handle, string(name), array_index, offset_address, rights, unmapped]
+      [handle, instance_name, array_index, offset_address, rights, unmapped, hdl_path]
     end
 
     def handle
       create_identifier(name)[loop_varibles]
     end
 
+    def instance_name
+      return string(name) unless array?
+      subroutine_call '$sformatf', [
+        string(name + '[%0d]' * loop_varibles.size),
+        *loop_varibles
+      ]
+    end
+
     def array_index
       return '\'{}' unless array?
       array(*loop_varibles)
@@ -72,6 +80,14 @@ simple_item :register, :reg_model do
       (shadow? && 1) || 0
     end
 
+    def hdl_path
+      return string('') unless array?
+      subroutine_call '$sformatf', [
+        string("g_#{name}" + '.g[%0d]' * loop_varibles.size),
+        *loop_varibles
+      ]
+    end
+
     def loop_varibles
       return nil unless array?
       @loop_varibles ||= Array.new(dimensions.size, &method(:loop_index))

data/lib/rggen/builtins/register/shadow_index_configurator.rb

@@ -13,7 +13,9 @@ simple_item :register, :shadow_index_configurator do
 
     def function_body(code)
       register.shadow_indexes.each do |shadow_index|
-        code << "set_shadow_index(#{arguments(shadow_index)});" << nl
+        code << subroutine_call(:set_shadow_index, arguments(shadow_index))
+        code << semicolon
+        code << nl
       end
     end
 
@@ -22,7 +24,7 @@ simple_item :register, :shadow_index_configurator do
         parent_name(shadow_index),
         index_name(shadow_index),
         index_value(shadow_index)
-      ].join(', ')
+      ]
     end
 
     def parent_name(shadow_index)

data/lib/rggen/builtins/register/sub_block_model.rb

@@ -20,7 +20,7 @@ simple_item :register, :sub_block_model do
     end
 
     def model_creation(code)
-      code << "`rggen_ral_create_block_model(#{arguments.join(', ')})" << nl
+      code << subroutine_call('`rggen_ral_create_block_model', arguments) << nl
     end
 
     def arguments

data/lib/rggen/builtins/register_block/default_map_creator.rb

@@ -6,7 +6,7 @@ simple_item :register_block, :default_map_creator do
         f.body do |code|
           code << :return
           code << space
-          code << "create_map(#{arguments.join(', ')})"
+          code << subroutine_call(:create_map, arguments)
           code << semicolon
         end
       end

data/lib/rggen/builtins/register_block/irq_controller.erb

@@ -0,0 +1,9 @@
+rggen_irq_controller #(
+  .TOTAL_INTERRUPTS (<%= total_interrupts %>)
+) u_irq_controller (
+  .clk    (<%= register_block.clock %>),
+  .rst_n  (<%= register_block.reset %>),
+  .i_ier  (<%= ier %>),
+  .i_isr  (<%= isr %>),
+  .o_irq  (<%= irq %>)
+);

data/lib/rggen/builtins/register_block/irq_controller.rb

@@ -0,0 +1,44 @@
+simple_item :register_block, :irq_controller do
+  rtl do
+    available? { total_interrupts > 0 }
+
+    build do
+      output :irq, width: 1               , name: 'o_irq'
+      logic  :ier, width: total_interrupts
+      logic  :isr, width: total_interrupts
+    end
+
+    generate_code :module_item do |code|
+      code << assign_ier << nl
+      code << assign_isr << nl
+      code << process_template
+    end
+
+    def total_interrupts
+      @total_interrupts ||=
+        register_block.source.bit_fields.count(&:irq?)
+    end
+
+    def assign_ier
+      assign(ier, concat(*ier_fields.map(&:value)))
+    end
+
+    def assign_isr
+      assign(isr, concat(*isr_fields.map(&:value)))
+    end
+
+    def isr_fields
+      register_block.bit_fields.select(&:irq?)
+    end
+
+    def ier_fields
+      isr_fields.each_with_object([]) do |isr_field, fields|
+        fields << find_ier_field(isr_field.reference)
+      end
+    end
+
+    def find_ier_field(reference)
+      register_block.bit_fields.find { |field| field.name == reference.name }
+    end
+  end
+end