rggen 0.4.0 → 0.4.1

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Files changed (43) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +18 -14
  3. data/lib/rggen/builder/category.rb +15 -4
  4. data/lib/rggen/builtins.rb +3 -0
  5. data/lib/rggen/builtins/bit_field/field_model.rb +6 -2
  6. data/lib/rggen/builtins/bit_field/reserved.rb +1 -0
  7. data/lib/rggen/builtins/bit_field/ro.erb +6 -0
  8. data/lib/rggen/builtins/bit_field/ro.rb +8 -7
  9. data/lib/rggen/builtins/bit_field/type.rb +14 -0
  10. data/lib/rggen/builtins/bit_field/w0c_w1c.erb +15 -0
  11. data/lib/rggen/builtins/bit_field/w0c_w1c.rb +26 -0
  12. data/lib/rggen/builtins/bit_field/w0s_w1s.erb +15 -0
  13. data/lib/rggen/builtins/bit_field/w0s_w1s.rb +34 -0
  14. data/lib/rggen/builtins/register/address_decoder.erb +0 -2
  15. data/lib/rggen/builtins/register/address_decoder.rb +0 -8
  16. data/lib/rggen/builtins/register/reg_model.rb +18 -2
  17. data/lib/rggen/builtins/register/shadow_index_configurator.rb +4 -2
  18. data/lib/rggen/builtins/register/sub_block_model.rb +1 -1
  19. data/lib/rggen/builtins/register_block/default_map_creator.rb +1 -1
  20. data/lib/rggen/builtins/register_block/irq_controller.erb +9 -0
  21. data/lib/rggen/builtins/register_block/irq_controller.rb +44 -0
  22. data/lib/rggen/output_base/component.rb +5 -4
  23. data/lib/rggen/output_base/verilog_utility.rb +4 -0
  24. data/lib/rggen/version.rb +1 -1
  25. data/ral/rggen_ral_block.svh +4 -0
  26. data/ral/rggen_ral_macros.svh +10 -9
  27. data/ral/rggen_ral_map.svh +3 -3
  28. data/ral/rggen_ral_reg.svh +4 -0
  29. data/rtl/bit_field/rggen_bit_field_ro.sv +8 -0
  30. data/rtl/bit_field/rggen_bit_field_w0c_w1c.sv +36 -0
  31. data/rtl/bit_field/rggen_bit_field_w0s_w1s.sv +36 -0
  32. data/rtl/register/rggen_address_decoder.sv +1 -19
  33. data/rtl/register_block/rggen_irq_controller.sv +21 -0
  34. data/sample/sample.csv +20 -15
  35. data/sample/sample.xls +0 -0
  36. data/sample/sample.xlsx +0 -0
  37. data/sample/sample_0.sv +167 -45
  38. data/sample/sample_0_ral_pkg.sv +45 -19
  39. data/sample/sample_1.sv +12 -8
  40. data/sample/sample_1_ral_pkg.sv +8 -8
  41. data/sample/sample_setup.rb +2 -2
  42. data/setup/default.rb +2 -2
  43. metadata +13 -2
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data/README.md CHANGED
@@ -59,20 +59,24 @@ In addition, if you use default values for all of attributes, you don't need to
59
59
  RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
60
60
  To do this, you need to write your register map document according to below table format.
61
61
 
62
- | |A |B |C |D |E |F |G |H |I |J |
63
- |:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------|:-------------|:---------|:---|:-----------|
64
- |1 | |Block Name |block_0 | | | | | | | |
65
- |2 | |Byte Size |256 | | | | | | | |
66
- |3 | | | | | | | | | | |
67
- |4 | |Offset Address|Register Name|Array Dimension|Shadow Index |External|Bit Assignment|Field Name|Type|Iitial Value|
68
- |5 | |0x00 |register_0 | | | |[31:16] |field_0_0 |rw |0 |
69
- |6 | | | | | | |[15:0] |field_0_1 |rw |0 |
70
- |7 | |0x04 |register_1 | | | |[16] |field_1_0 |rw |0 |
71
- |8 | | | | | | |[0] |field_1_1 |ro | |
72
- |9 | |0x10 - 0x1F |register_2 |[4] | | |[7:0] |field_2_0 |rw |0 |
73
- |10 | |0x20 - 0x3F |register_3 | | |true | | | | |
74
- |11 | |0x40 |register_4 |[2, 4] |field_1_0:1, field_0_0, field_0_1| |[7:0] |field_4_0 |rw |0 |
75
-
62
+ | |A |B |C |D |E |F |G |H |I |J |K |
63
+ |:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------|:-------------|:---------|:---|:-----------|:--------|
64
+ |1 | |Block Name |block_0 | | | | | | | | |
65
+ |2 | |Byte Size |256 | | | | | | | | |
66
+ |3 | | | | | | | | | | | |
67
+ |4 | |Offset Address|Register Name|Array Dimension|Shadow Index |External|Bit Assignment|Field Name|Type|Iitial Value|Reference|
68
+ |5 | |0x00 |register_0 | | | |[31:16] |field_0_0 |rw |0 | |
69
+ |6 | | | | | | |[15:0] |field_0_1 |rw |0 | |
70
+ |7 | |0x04 |register_1 | | | |[16] |field_1_0 |rw |0 | |
71
+ |8 | | | | | | |[0] |field_1_1 |ro | | |
72
+ |9 | |0x10 - 0x1F |register_2 |[4] | | |[7:0] |field_2_0 |rw |0 | |
73
+ |10 | |0x20 - 0x3F |register_3 | | |true | | | | | |
74
+ |11 | |0x40 |register_4 |[2, 4] |field_1_0:1, field_0_0, field_0_1| |[7:0] |field_4_0 |rw |0 | |
75
+ |12 | |0x44 |register_5 | | | |[8] |field_5_0 |w0s |0 | |
76
+ |13 | | | | | | |[0] |field_5_1 |w1s |0 | |
77
+ |14 | |0x48 |register_6 | | | |[8] |field_6_0 |w0c |0 |field_1_0|
78
+ |15 | | | | | | |[0] |field_6_1 |w1c |0 |field_1_0|
79
+
76
80
  By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
77
81
 
78
82
  ### Generating Source Code
@@ -11,12 +11,23 @@ module RgGen
11
11
  define_definition_method(component_name)
12
12
  end
13
13
 
14
- def define_simple_item(item_name, &body)
15
- do_definition(:define_simple_item, item_name, &body)
14
+ def define_simple_item(item_name_or_names, &body)
15
+ Array(item_name_or_names).each do |item_name|
16
+ do_definition(:define_simple_item, item_name, &body)
17
+ end
16
18
  end
17
19
 
18
- def define_list_item(list_name, item_name = nil, &body)
19
- do_definition(:define_list_item, list_name, item_name, &body)
20
+ def define_list_item(list_name_or_names, item_name_or_names = nil, &body)
21
+ if item_name_or_names.nil?
22
+ Array(list_name_or_names).each do |list_name|
23
+ do_definition(:define_list_item, list_name, nil, &body)
24
+ end
25
+ else
26
+ list_name = list_name_or_names
27
+ Array(item_name_or_names).each do |item_name|
28
+ do_definition(:define_list_item, list_name, item_name, &body)
29
+ end
30
+ end
20
31
  end
21
32
 
22
33
  def shared_context(&body)
@@ -15,6 +15,8 @@ require_relative 'builtins/bit_field/reference'
15
15
  require_relative 'builtins/bit_field/type'
16
16
  require_relative 'builtins/bit_field/rw'
17
17
  require_relative 'builtins/bit_field/ro'
18
+ require_relative 'builtins/bit_field/w0c_w1c'
19
+ require_relative 'builtins/bit_field/w0s_w1s'
18
20
  require_relative 'builtins/bit_field/wo'
19
21
  require_relative 'builtins/bit_field/reserved'
20
22
 
@@ -43,6 +45,7 @@ require_relative 'builtins/register_block/default_map_creator'
43
45
  require_relative 'builtins/register_block/host_if'
44
46
  require_relative 'builtins/register_block/apb'
45
47
  require_relative 'builtins/register_block/axi4lite'
48
+ require_relative 'builtins/register_block/irq_controller'
46
49
  require_relative 'builtins/register_block/name'
47
50
  require_relative 'builtins/register_block/ral_package'
48
51
  require_relative 'builtins/register_block/response_mux'
@@ -12,11 +12,11 @@ simple_item :bit_field, :field_model do
12
12
  end
13
13
 
14
14
  def model_creation(code)
15
- code << "`rggen_ral_create_field_model(#{arguments.join(', ')})" << nl
15
+ code << subroutine_call('`rggen_ral_create_field_model', arguments) << nl
16
16
  end
17
17
 
18
18
  def arguments
19
- [name, string(name), width, lsb, access, volatile, reset, has_reset]
19
+ [name, string(name), width, lsb, access, volatile, reset, has_reset, hdl_path]
20
20
  end
21
21
 
22
22
  def volatile
@@ -30,5 +30,9 @@ simple_item :bit_field, :field_model do
30
30
  def has_reset
31
31
  (bit_field.initial_value? && 1) || 0
32
32
  end
33
+
34
+ def hdl_path
35
+ string(bit_field.hdl_path)
36
+ end
33
37
  end
34
38
  end
@@ -5,5 +5,6 @@ list_item :bit_field, :type, :reserved do
5
5
 
6
6
  ral do
7
7
  access :ro
8
+ hdl_path { '' }
8
9
  end
9
10
  end
@@ -0,0 +1,6 @@
1
+ rggen_bit_field_ro #(
2
+ .WIDTH (<%= width %>)
3
+ ) u_<%= bit_field.name %> (
4
+ .i_value (<%= value_in[loop_variables] %>),
5
+ .o_value (<%= value[loop_variables] %>)
6
+ );
@@ -5,15 +5,16 @@ list_item :bit_field, :type, :ro do
5
5
 
6
6
  rtl do
7
7
  build do
8
- input :value_in, name: port_name, width: width, dimensions: dimensions
8
+ input :value_in,
9
+ name: "i_#{bit_field.name}",
10
+ width: width,
11
+ dimensions: dimensions
9
12
  end
10
13
 
11
- generate_code :module_item do |buffer|
12
- buffer << assign(value[loop_variables], value_in[loop_variables]) << nl
13
- end
14
+ generate_code_from_template :module_item
15
+ end
14
16
 
15
- def port_name
16
- "i_#{bit_field.name}"
17
- end
17
+ ral do
18
+ hdl_path { "u_#{bit_field.name}.i_value" }
18
19
  end
19
20
  end
@@ -70,6 +70,10 @@ list_item :bit_field, :type do
70
70
  def same_width
71
71
  :same_width
72
72
  end
73
+
74
+ def irq?(&body)
75
+ define_method(:irq?, &body)
76
+ end
73
77
  end
74
78
 
75
79
  field :type
@@ -78,6 +82,7 @@ list_item :bit_field, :type do
78
82
  field :read_only? , forward_to_helper: true
79
83
  field :write_only?, forward_to_helper: true
80
84
  field :reserved? , forward_to_helper: true
85
+ field :irq? , default: false
81
86
 
82
87
  class_delegator :full_width
83
88
  class_delegator :need_initial_value?
@@ -188,14 +193,23 @@ list_item :bit_field, :type do
188
193
  ral do
189
194
  item_base do
190
195
  export :access
196
+ export :hdl_path
191
197
 
192
198
  define_helpers do
193
199
  attr_setter :access
200
+
201
+ def hdl_path(&body)
202
+ define_method(:hdl_path, &body)
203
+ end
194
204
  end
195
205
 
196
206
  def access
197
207
  string((self.class.access || bit_field.type).to_s.upcase)
198
208
  end
209
+
210
+ def hdl_path
211
+ "u_#{bit_field.name}.value"
212
+ end
199
213
  end
200
214
 
201
215
  default_item do
@@ -0,0 +1,15 @@
1
+ rggen_bit_field_w0c_w1c #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .CLEAR_VALUE (<%= clear_value %>)
5
+ ) u_<%= name%> (
6
+ .clk (<%= register_block.clock %>),
7
+ .rst_n (<%= register_block.reset %>),
8
+ .i_set (<%= set[loop_variables] %>),
9
+ .i_command_valid (<%= register_block.host_if.command_valid %>),
10
+ .i_select (<%= register_block.register_select[index] %>),
11
+ .i_write (<%= register_block.host_if.write %>),
12
+ .i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
13
+ .i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
14
+ .o_value (<%= value[loop_variables] %>)
15
+ );
@@ -0,0 +1,26 @@
1
+ list_item :bit_field, :type, [:w0c, :w1c] do
2
+ register_map do
3
+ read_write
4
+ need_initial_value
5
+ use_reference width: same_width
6
+ irq? { bit_field.has_reference? }
7
+ end
8
+
9
+ rtl do
10
+ delegate [:name, :type] => :bit_field
11
+
12
+ build do
13
+ input :set, name: "i_#{name}_set", width: width, dimensions: dimensions
14
+ end
15
+
16
+ generate_code_from_template :module_item
17
+
18
+ def initial_value
19
+ hex(bit_field.initial_value, width)
20
+ end
21
+
22
+ def clear_value
23
+ bin({ w0c: 0, w1c: 1 }[type], 1)
24
+ end
25
+ end
26
+ end
@@ -0,0 +1,15 @@
1
+ rggen_bit_field_w0s_w1s #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SET_VALUE (<%= set_value %>)
5
+ ) u_<%= name %> (
6
+ .clk (<%= register_block.clock %>),
7
+ .rst_n (<%= register_block.reset %>),
8
+ .i_clear (<%= clear[loop_variables] %>),
9
+ .i_command_valid (<%= register_block.host_if.command_valid %>),
10
+ .i_select (<%= register_block.register_select[index] %>),
11
+ .i_write (<%= register_block.host_if.write %>),
12
+ .i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
13
+ .i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
14
+ .o_value (<%= value[loop_variables] %>)
15
+ );
@@ -0,0 +1,34 @@
1
+ list_item :bit_field, :type, [:w0s, :w1s] do
2
+ register_map do
3
+ read_write
4
+ need_initial_value
5
+ end
6
+
7
+ rtl do
8
+ delegate [:name, :type] => :bit_field
9
+
10
+ build do
11
+ output :value_out,
12
+ name: "o_#{name}",
13
+ width: width,
14
+ dimensions: dimensions
15
+ input :clear,
16
+ name: "i_#{name}_clear",
17
+ width: width,
18
+ dimensions: dimensions
19
+ end
20
+
21
+ generate_code :module_item do |code|
22
+ code << assign(value_out[loop_variables], value[loop_variables]) << nl
23
+ code << process_template
24
+ end
25
+
26
+ def initial_value
27
+ hex(bit_field.initial_value, width)
28
+ end
29
+
30
+ def set_value
31
+ bin({ w0s: 0, w1s: 1 }[type], 1)
32
+ end
33
+ end
34
+ end
@@ -1,6 +1,4 @@
1
1
  rggen_address_decoder #(
2
- .READABLE (<%= readable %>),
3
- .WRITABLE (<%= writable %>),
4
2
  .ADDRESS_WIDTH (<%= local_address_width - address_lsb %>),
5
3
  .START_ADDRESS (<%= start_address%>),
6
4
  .END_ADDRESS (<%= end_address %>),
@@ -17,14 +17,6 @@ simple_item :register, :address_decoder do
17
17
  delegate [:array?, :shadow?, :multiple?] => :register
18
18
  delegate [:shadow_indexes, :loop_variables] => :register
19
19
 
20
- def readable
21
- ((register.readable? || register.reserved?) && 1) || 0
22
- end
23
-
24
- def writable
25
- ((register.writable? || register.reserved?) && 1) || 0
26
- end
27
-
28
20
  def address_lsb
29
21
  Math.clog2(configuration.byte_width)
30
22
  end
@@ -26,7 +26,7 @@ simple_item :register, :reg_model do
26
26
 
27
27
  def model_creation(code)
28
28
  foreach_header(code) if array?
29
- code << "`rggen_ral_create_reg_model(#{arguments.join(', ')})" << nl
29
+ code << subroutine_call('`rggen_ral_create_reg_model', arguments) << nl
30
30
  foreach_footer(code) if array?
31
31
  end
32
32
 
@@ -41,13 +41,21 @@ simple_item :register, :reg_model do
41
41
  end
42
42
 
43
43
  def arguments
44
- [handle, string(name), array_index, offset_address, rights, unmapped]
44
+ [handle, instance_name, array_index, offset_address, rights, unmapped, hdl_path]
45
45
  end
46
46
 
47
47
  def handle
48
48
  create_identifier(name)[loop_varibles]
49
49
  end
50
50
 
51
+ def instance_name
52
+ return string(name) unless array?
53
+ subroutine_call '$sformatf', [
54
+ string(name + '[%0d]' * loop_varibles.size),
55
+ *loop_varibles
56
+ ]
57
+ end
58
+
51
59
  def array_index
52
60
  return '\'{}' unless array?
53
61
  array(*loop_varibles)
@@ -72,6 +80,14 @@ simple_item :register, :reg_model do
72
80
  (shadow? && 1) || 0
73
81
  end
74
82
 
83
+ def hdl_path
84
+ return string('') unless array?
85
+ subroutine_call '$sformatf', [
86
+ string("g_#{name}" + '.g[%0d]' * loop_varibles.size),
87
+ *loop_varibles
88
+ ]
89
+ end
90
+
75
91
  def loop_varibles
76
92
  return nil unless array?
77
93
  @loop_varibles ||= Array.new(dimensions.size, &method(:loop_index))
@@ -13,7 +13,9 @@ simple_item :register, :shadow_index_configurator do
13
13
 
14
14
  def function_body(code)
15
15
  register.shadow_indexes.each do |shadow_index|
16
- code << "set_shadow_index(#{arguments(shadow_index)});" << nl
16
+ code << subroutine_call(:set_shadow_index, arguments(shadow_index))
17
+ code << semicolon
18
+ code << nl
17
19
  end
18
20
  end
19
21
 
@@ -22,7 +24,7 @@ simple_item :register, :shadow_index_configurator do
22
24
  parent_name(shadow_index),
23
25
  index_name(shadow_index),
24
26
  index_value(shadow_index)
25
- ].join(', ')
27
+ ]
26
28
  end
27
29
 
28
30
  def parent_name(shadow_index)
@@ -20,7 +20,7 @@ simple_item :register, :sub_block_model do
20
20
  end
21
21
 
22
22
  def model_creation(code)
23
- code << "`rggen_ral_create_block_model(#{arguments.join(', ')})" << nl
23
+ code << subroutine_call('`rggen_ral_create_block_model', arguments) << nl
24
24
  end
25
25
 
26
26
  def arguments
@@ -6,7 +6,7 @@ simple_item :register_block, :default_map_creator do
6
6
  f.body do |code|
7
7
  code << :return
8
8
  code << space
9
- code << "create_map(#{arguments.join(', ')})"
9
+ code << subroutine_call(:create_map, arguments)
10
10
  code << semicolon
11
11
  end
12
12
  end
@@ -0,0 +1,9 @@
1
+ rggen_irq_controller #(
2
+ .TOTAL_INTERRUPTS (<%= total_interrupts %>)
3
+ ) u_irq_controller (
4
+ .clk (<%= register_block.clock %>),
5
+ .rst_n (<%= register_block.reset %>),
6
+ .i_ier (<%= ier %>),
7
+ .i_isr (<%= isr %>),
8
+ .o_irq (<%= irq %>)
9
+ );
@@ -0,0 +1,44 @@
1
+ simple_item :register_block, :irq_controller do
2
+ rtl do
3
+ available? { total_interrupts > 0 }
4
+
5
+ build do
6
+ output :irq, width: 1 , name: 'o_irq'
7
+ logic :ier, width: total_interrupts
8
+ logic :isr, width: total_interrupts
9
+ end
10
+
11
+ generate_code :module_item do |code|
12
+ code << assign_ier << nl
13
+ code << assign_isr << nl
14
+ code << process_template
15
+ end
16
+
17
+ def total_interrupts
18
+ @total_interrupts ||=
19
+ register_block.source.bit_fields.count(&:irq?)
20
+ end
21
+
22
+ def assign_ier
23
+ assign(ier, concat(*ier_fields.map(&:value)))
24
+ end
25
+
26
+ def assign_isr
27
+ assign(isr, concat(*isr_fields.map(&:value)))
28
+ end
29
+
30
+ def isr_fields
31
+ register_block.bit_fields.select(&:irq?)
32
+ end
33
+
34
+ def ier_fields
35
+ isr_fields.each_with_object([]) do |isr_field, fields|
36
+ fields << find_ier_field(isr_field.reference)
37
+ end
38
+ end
39
+
40
+ def find_ier_field(reference)
41
+ register_block.bit_fields.find { |field| field.name == reference.name }
42
+ end
43
+ end
44
+ end