rggen 0.4.0 → 0.4.1

data/sample/sample_0_ral_pkg.sv

@@ -10,8 +10,8 @@ package sample_0_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1)
-      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1)
+      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
+      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_0_1.value")
     endfunction
   endclass
   class register_1_reg_model extends rggen_ral_reg;
@@ -20,7 +20,7 @@ package sample_0_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1)
+      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
     endfunction
   endclass
   class register_2_reg_model extends rggen_ral_reg;
@@ -30,8 +30,8 @@ package sample_0_ral_pkg;
       super.new(name, 24, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0)
-      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
+      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
     endfunction
   endclass
   class register_3_reg_model extends rggen_ral_reg;
@@ -40,7 +40,7 @@ package sample_0_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0)
+      `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0, "u_bit_field_3_0.i_value")
     endfunction
   endclass
   class register_4_reg_model extends rggen_ral_reg;
@@ -50,8 +50,8 @@ package sample_0_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0)
-      `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1)
+      `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_4_0.i_value")
+      `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_4_1.value")
     endfunction
   endclass
   class register_5_reg_model extends rggen_ral_shadow_reg;
@@ -61,8 +61,8 @@ package sample_0_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0)
-      `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1)
+      `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_5_0.i_value")
+      `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_5_1.value")
     endfunction
     function void configure_shadow_indexes();
       set_shadow_index("register_2", "bit_field_2_1", 1);
@@ -70,8 +70,30 @@ package sample_0_ral_pkg;
       set_shadow_index("register_0", "bit_field_0_1", indexes[1]);
     endfunction
   endclass
+  class register_6_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_6_0;
+    rand rggen_ral_field bit_field_6_1;
+    function new(string name = "register_6");
+      super.new(name, 16, 0);
+    endfunction
+    function void create_fields();
+      `rggen_ral_create_field_model(bit_field_6_0, "bit_field_6_0", 1, 8, "W0C", 0, 1'h0, 1, "u_bit_field_6_0.value")
+      `rggen_ral_create_field_model(bit_field_6_1, "bit_field_6_1", 1, 0, "W1C", 0, 1'h0, 1, "u_bit_field_6_1.value")
+    endfunction
+  endclass
+  class register_7_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_7_0;
+    rand rggen_ral_field bit_field_7_1;
+    function new(string name = "register_7");
+      super.new(name, 16, 0);
+    endfunction
+    function void create_fields();
+      `rggen_ral_create_field_model(bit_field_7_0, "bit_field_7_0", 1, 8, "W0S", 0, 1'h0, 1, "u_bit_field_7_0.value")
+      `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
+    endfunction
+  endclass
   class sample_0_block_model#(
-    type REGISTER_6 = rggen_ral_block
+    type REGISTER_8 = rggen_ral_block
   ) extends rggen_ral_block;
     rand register_0_reg_model register_0;
     rand register_1_reg_model register_1;
@@ -79,22 +101,26 @@ package sample_0_ral_pkg;
     rand register_3_reg_model register_3;
     rand register_4_reg_model register_4[4];
     rand register_5_reg_model register_5[2][4];
-    rand REGISTER_6 register_6;
+    rand register_6_reg_model register_6;
+    rand register_7_reg_model register_7;
+    rand REGISTER_8 register_8;
     function new(string name = "sample_0");
       super.new(name);
     endfunction
     function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0)
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0)
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0)
-      `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0)
+      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0, "")
       foreach (register_4[i]) begin
-        `rggen_ral_create_reg_model(register_4[i], "register_4", '{i}, 8'h10 + 4 * i, "RW", 0)
+        `rggen_ral_create_reg_model(register_4[i], $sformatf("register_4[%0d]", i), '{i}, 8'h10 + 4 * i, "RW", 0, $sformatf("g_register_4.g[%0d]", i))
       end
       foreach (register_5[i, j]) begin
-        `rggen_ral_create_reg_model(register_5[i][j], "register_5", '{i, j}, 8'h20, "RW", 1)
+        `rggen_ral_create_reg_model(register_5[i][j], $sformatf("register_5[%0d][%0d]", i, j), '{i, j}, 8'h20, "RW", 1, $sformatf("g_register_5.g[%0d].g[%0d]", i, j))
       end
-      `rggen_ral_create_block_model(register_6, "register_6", 8'h80)
+      `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
+      `rggen_ral_create_block_model(register_8, "register_8", 8'h80)
     endfunction
     function uvm_reg_map create_default_map();
       return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);

data/sample/sample_1.sv

@@ -81,8 +81,6 @@ module sample_1 (
     .i_external_register_status ('{2'b00})
   );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (5),
     .START_ADDRESS      (5'h00),
     .END_ADDRESS        (5'h00),
@@ -111,10 +109,13 @@ module sample_1 (
     .i_write_mask     (write_mask[31:16]),
     .o_value          (bit_field_0_0_value)
   );
-  assign bit_field_0_1_value = i_bit_field_0_1;
+  rggen_bit_field_ro #(
+    .WIDTH  (16)
+  ) u_bit_field_0_1 (
+    .i_value  (i_bit_field_0_1),
+    .o_value  (bit_field_0_1_value)
+  );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (5),
     .START_ADDRESS      (5'h01),
     .END_ADDRESS        (5'h01),
@@ -144,8 +145,6 @@ module sample_1 (
     .o_value          (bit_field_1_0_value)
   );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (5),
     .START_ADDRESS      (5'h02),
     .END_ADDRESS        (5'h02),
@@ -160,7 +159,12 @@ module sample_1 (
     .o_select       (register_select[2])
   );
   assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
-  assign bit_field_2_0_value = i_bit_field_2_0;
+  rggen_bit_field_ro #(
+    .WIDTH  (1)
+  ) u_bit_field_2_0 (
+    .i_value  (i_bit_field_2_0),
+    .o_value  (bit_field_2_0_value)
+  );
   assign o_bit_field_2_1 = bit_field_2_1_value;
   rggen_bit_field_rw #(
     .WIDTH          (1),

data/sample/sample_1_ral_pkg.sv

@@ -10,8 +10,8 @@ package sample_1_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1)
-      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0)
+      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
+      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0, "u_bit_field_0_1.i_value")
     endfunction
   endclass
   class register_1_reg_model extends rggen_ral_reg;
@@ -20,7 +20,7 @@ package sample_1_ral_pkg;
       super.new(name, 32, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1)
+      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
     endfunction
   endclass
   class register_2_reg_model extends rggen_ral_reg;
@@ -30,8 +30,8 @@ package sample_1_ral_pkg;
       super.new(name, 24, 0);
     endfunction
     function void create_fields();
-      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0)
-      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
+      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
     endfunction
   endclass
   class sample_1_block_model extends rggen_ral_block;
@@ -42,9 +42,9 @@ package sample_1_ral_pkg;
       super.new(name);
     endfunction
     function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0)
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0)
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0)
+      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0, "")
     endfunction
     function uvm_reg_map create_default_map();
       return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);

data/sample/sample_setup.rb

@@ -12,8 +12,8 @@ enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :base_address]
 enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :foo, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux]
+enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :foo, :reserved]
+enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :bar]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]

data/setup/default.rb

@@ -2,8 +2,8 @@ enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :byte_size]
 enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux]
+enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :reserved]
+enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :axi4lite]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.4.0
+  version: 0.4.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-05-24 00:00:00.000000000 Z
+date: 2016-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -146,10 +146,15 @@ files:
 - lib/rggen/builtins/bit_field/name.rb
 - lib/rggen/builtins/bit_field/reference.rb
 - lib/rggen/builtins/bit_field/reserved.rb
+- lib/rggen/builtins/bit_field/ro.erb
 - lib/rggen/builtins/bit_field/ro.rb
 - lib/rggen/builtins/bit_field/rw.erb
 - lib/rggen/builtins/bit_field/rw.rb
 - lib/rggen/builtins/bit_field/type.rb
+- lib/rggen/builtins/bit_field/w0c_w1c.erb
+- lib/rggen/builtins/bit_field/w0c_w1c.rb
+- lib/rggen/builtins/bit_field/w0s_w1s.erb
+- lib/rggen/builtins/bit_field/w0s_w1s.rb
 - lib/rggen/builtins/bit_field/wo.rb
 - lib/rggen/builtins/global/address_width.rb
 - lib/rggen/builtins/global/data_width.rb
@@ -186,6 +191,8 @@ files:
 - lib/rggen/builtins/register_block/constructor.rb
 - lib/rggen/builtins/register_block/default_map_creator.rb
 - lib/rggen/builtins/register_block/host_if.rb
+- lib/rggen/builtins/register_block/irq_controller.erb
+- lib/rggen/builtins/register_block/irq_controller.rb
 - lib/rggen/builtins/register_block/name.rb
 - lib/rggen/builtins/register_block/ral_package.rb
 - lib/rggen/builtins/register_block/response_mux.erb
@@ -254,13 +261,17 @@ files:
 - ral/rggen_ral_pkg.sv
 - ral/rggen_ral_reg.svh
 - ral/rggen_ral_shadow_reg.svh
+- rtl/bit_field/rggen_bit_field_ro.sv
 - rtl/bit_field/rggen_bit_field_rw.sv
+- rtl/bit_field/rggen_bit_field_w0c_w1c.sv
+- rtl/bit_field/rggen_bit_field_w0s_w1s.sv
 - rtl/compile.f
 - rtl/register/rggen_address_decoder.sv
 - rtl/register/rggen_bus_exporter.sv
 - rtl/register_block/rggen_host_if_apb.sv
 - rtl/register_block/rggen_host_if_axi4lite.sv
 - rtl/register_block/rggen_host_if_common.svh
+- rtl/register_block/rggen_irq_controller.sv
 - rtl/register_block/rggen_response_mux.sv
 - sample/sample.csv
 - sample/sample.json