rggen 0.4.0 → 0.4.1

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Files changed (43) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +18 -14
  3. data/lib/rggen/builder/category.rb +15 -4
  4. data/lib/rggen/builtins.rb +3 -0
  5. data/lib/rggen/builtins/bit_field/field_model.rb +6 -2
  6. data/lib/rggen/builtins/bit_field/reserved.rb +1 -0
  7. data/lib/rggen/builtins/bit_field/ro.erb +6 -0
  8. data/lib/rggen/builtins/bit_field/ro.rb +8 -7
  9. data/lib/rggen/builtins/bit_field/type.rb +14 -0
  10. data/lib/rggen/builtins/bit_field/w0c_w1c.erb +15 -0
  11. data/lib/rggen/builtins/bit_field/w0c_w1c.rb +26 -0
  12. data/lib/rggen/builtins/bit_field/w0s_w1s.erb +15 -0
  13. data/lib/rggen/builtins/bit_field/w0s_w1s.rb +34 -0
  14. data/lib/rggen/builtins/register/address_decoder.erb +0 -2
  15. data/lib/rggen/builtins/register/address_decoder.rb +0 -8
  16. data/lib/rggen/builtins/register/reg_model.rb +18 -2
  17. data/lib/rggen/builtins/register/shadow_index_configurator.rb +4 -2
  18. data/lib/rggen/builtins/register/sub_block_model.rb +1 -1
  19. data/lib/rggen/builtins/register_block/default_map_creator.rb +1 -1
  20. data/lib/rggen/builtins/register_block/irq_controller.erb +9 -0
  21. data/lib/rggen/builtins/register_block/irq_controller.rb +44 -0
  22. data/lib/rggen/output_base/component.rb +5 -4
  23. data/lib/rggen/output_base/verilog_utility.rb +4 -0
  24. data/lib/rggen/version.rb +1 -1
  25. data/ral/rggen_ral_block.svh +4 -0
  26. data/ral/rggen_ral_macros.svh +10 -9
  27. data/ral/rggen_ral_map.svh +3 -3
  28. data/ral/rggen_ral_reg.svh +4 -0
  29. data/rtl/bit_field/rggen_bit_field_ro.sv +8 -0
  30. data/rtl/bit_field/rggen_bit_field_w0c_w1c.sv +36 -0
  31. data/rtl/bit_field/rggen_bit_field_w0s_w1s.sv +36 -0
  32. data/rtl/register/rggen_address_decoder.sv +1 -19
  33. data/rtl/register_block/rggen_irq_controller.sv +21 -0
  34. data/sample/sample.csv +20 -15
  35. data/sample/sample.xls +0 -0
  36. data/sample/sample.xlsx +0 -0
  37. data/sample/sample_0.sv +167 -45
  38. data/sample/sample_0_ral_pkg.sv +45 -19
  39. data/sample/sample_1.sv +12 -8
  40. data/sample/sample_1_ral_pkg.sv +8 -8
  41. data/sample/sample_setup.rb +2 -2
  42. data/setup/default.rb +2 -2
  43. metadata +13 -2
@@ -10,8 +10,8 @@ package sample_0_ral_pkg;
10
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  super.new(name, 32, 0);
11
11
  endfunction
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  function void create_fields();
13
- `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1)
14
- `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1)
13
+ `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
14
+ `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_0_1.value")
15
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  endfunction
16
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  endclass
17
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  class register_1_reg_model extends rggen_ral_reg;
@@ -20,7 +20,7 @@ package sample_0_ral_pkg;
20
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  super.new(name, 32, 0);
21
21
  endfunction
22
22
  function void create_fields();
23
- `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1)
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+ `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
24
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  endfunction
25
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  endclass
26
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  class register_2_reg_model extends rggen_ral_reg;
@@ -30,8 +30,8 @@ package sample_0_ral_pkg;
30
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  super.new(name, 24, 0);
31
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  endfunction
32
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  function void create_fields();
33
- `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0)
34
- `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1)
33
+ `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
34
+ `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
35
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  endfunction
36
36
  endclass
37
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  class register_3_reg_model extends rggen_ral_reg;
@@ -40,7 +40,7 @@ package sample_0_ral_pkg;
40
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  super.new(name, 32, 0);
41
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  endfunction
42
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  function void create_fields();
43
- `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0)
43
+ `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0, "u_bit_field_3_0.i_value")
44
44
  endfunction
45
45
  endclass
46
46
  class register_4_reg_model extends rggen_ral_reg;
@@ -50,8 +50,8 @@ package sample_0_ral_pkg;
50
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  super.new(name, 32, 0);
51
51
  endfunction
52
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  function void create_fields();
53
- `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0)
54
- `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1)
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+ `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_4_0.i_value")
54
+ `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_4_1.value")
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  endfunction
56
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  endclass
57
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  class register_5_reg_model extends rggen_ral_shadow_reg;
@@ -61,8 +61,8 @@ package sample_0_ral_pkg;
61
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  super.new(name, 32, 0);
62
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  endfunction
63
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  function void create_fields();
64
- `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0)
65
- `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1)
64
+ `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_5_0.i_value")
65
+ `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_5_1.value")
66
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  endfunction
67
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  function void configure_shadow_indexes();
68
68
  set_shadow_index("register_2", "bit_field_2_1", 1);
@@ -70,8 +70,30 @@ package sample_0_ral_pkg;
70
70
  set_shadow_index("register_0", "bit_field_0_1", indexes[1]);
71
71
  endfunction
72
72
  endclass
73
+ class register_6_reg_model extends rggen_ral_reg;
74
+ rand rggen_ral_field bit_field_6_0;
75
+ rand rggen_ral_field bit_field_6_1;
76
+ function new(string name = "register_6");
77
+ super.new(name, 16, 0);
78
+ endfunction
79
+ function void create_fields();
80
+ `rggen_ral_create_field_model(bit_field_6_0, "bit_field_6_0", 1, 8, "W0C", 0, 1'h0, 1, "u_bit_field_6_0.value")
81
+ `rggen_ral_create_field_model(bit_field_6_1, "bit_field_6_1", 1, 0, "W1C", 0, 1'h0, 1, "u_bit_field_6_1.value")
82
+ endfunction
83
+ endclass
84
+ class register_7_reg_model extends rggen_ral_reg;
85
+ rand rggen_ral_field bit_field_7_0;
86
+ rand rggen_ral_field bit_field_7_1;
87
+ function new(string name = "register_7");
88
+ super.new(name, 16, 0);
89
+ endfunction
90
+ function void create_fields();
91
+ `rggen_ral_create_field_model(bit_field_7_0, "bit_field_7_0", 1, 8, "W0S", 0, 1'h0, 1, "u_bit_field_7_0.value")
92
+ `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
93
+ endfunction
94
+ endclass
73
95
  class sample_0_block_model#(
74
- type REGISTER_6 = rggen_ral_block
96
+ type REGISTER_8 = rggen_ral_block
75
97
  ) extends rggen_ral_block;
76
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  rand register_0_reg_model register_0;
77
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  rand register_1_reg_model register_1;
@@ -79,22 +101,26 @@ package sample_0_ral_pkg;
79
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  rand register_3_reg_model register_3;
80
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  rand register_4_reg_model register_4[4];
81
103
  rand register_5_reg_model register_5[2][4];
82
- rand REGISTER_6 register_6;
104
+ rand register_6_reg_model register_6;
105
+ rand register_7_reg_model register_7;
106
+ rand REGISTER_8 register_8;
83
107
  function new(string name = "sample_0");
84
108
  super.new(name);
85
109
  endfunction
86
110
  function void create_sub_models();
87
- `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0)
88
- `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0)
89
- `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0)
90
- `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0)
111
+ `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0, "")
112
+ `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0, "")
113
+ `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0, "")
114
+ `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0, "")
91
115
  foreach (register_4[i]) begin
92
- `rggen_ral_create_reg_model(register_4[i], "register_4", '{i}, 8'h10 + 4 * i, "RW", 0)
116
+ `rggen_ral_create_reg_model(register_4[i], $sformatf("register_4[%0d]", i), '{i}, 8'h10 + 4 * i, "RW", 0, $sformatf("g_register_4.g[%0d]", i))
93
117
  end
94
118
  foreach (register_5[i, j]) begin
95
- `rggen_ral_create_reg_model(register_5[i][j], "register_5", '{i, j}, 8'h20, "RW", 1)
119
+ `rggen_ral_create_reg_model(register_5[i][j], $sformatf("register_5[%0d][%0d]", i, j), '{i, j}, 8'h20, "RW", 1, $sformatf("g_register_5.g[%0d].g[%0d]", i, j))
96
120
  end
97
- `rggen_ral_create_block_model(register_6, "register_6", 8'h80)
121
+ `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
122
+ `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
123
+ `rggen_ral_create_block_model(register_8, "register_8", 8'h80)
98
124
  endfunction
99
125
  function uvm_reg_map create_default_map();
100
126
  return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
@@ -81,8 +81,6 @@ module sample_1 (
81
81
  .i_external_register_status ('{2'b00})
82
82
  );
83
83
  rggen_address_decoder #(
84
- .READABLE (1),
85
- .WRITABLE (1),
86
84
  .ADDRESS_WIDTH (5),
87
85
  .START_ADDRESS (5'h00),
88
86
  .END_ADDRESS (5'h00),
@@ -111,10 +109,13 @@ module sample_1 (
111
109
  .i_write_mask (write_mask[31:16]),
112
110
  .o_value (bit_field_0_0_value)
113
111
  );
114
- assign bit_field_0_1_value = i_bit_field_0_1;
112
+ rggen_bit_field_ro #(
113
+ .WIDTH (16)
114
+ ) u_bit_field_0_1 (
115
+ .i_value (i_bit_field_0_1),
116
+ .o_value (bit_field_0_1_value)
117
+ );
115
118
  rggen_address_decoder #(
116
- .READABLE (1),
117
- .WRITABLE (1),
118
119
  .ADDRESS_WIDTH (5),
119
120
  .START_ADDRESS (5'h01),
120
121
  .END_ADDRESS (5'h01),
@@ -144,8 +145,6 @@ module sample_1 (
144
145
  .o_value (bit_field_1_0_value)
145
146
  );
146
147
  rggen_address_decoder #(
147
- .READABLE (1),
148
- .WRITABLE (1),
149
148
  .ADDRESS_WIDTH (5),
150
149
  .START_ADDRESS (5'h02),
151
150
  .END_ADDRESS (5'h02),
@@ -160,7 +159,12 @@ module sample_1 (
160
159
  .o_select (register_select[2])
161
160
  );
162
161
  assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
163
- assign bit_field_2_0_value = i_bit_field_2_0;
162
+ rggen_bit_field_ro #(
163
+ .WIDTH (1)
164
+ ) u_bit_field_2_0 (
165
+ .i_value (i_bit_field_2_0),
166
+ .o_value (bit_field_2_0_value)
167
+ );
164
168
  assign o_bit_field_2_1 = bit_field_2_1_value;
165
169
  rggen_bit_field_rw #(
166
170
  .WIDTH (1),
@@ -10,8 +10,8 @@ package sample_1_ral_pkg;
10
10
  super.new(name, 32, 0);
11
11
  endfunction
12
12
  function void create_fields();
13
- `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1)
14
- `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0)
13
+ `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
14
+ `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0, "u_bit_field_0_1.i_value")
15
15
  endfunction
16
16
  endclass
17
17
  class register_1_reg_model extends rggen_ral_reg;
@@ -20,7 +20,7 @@ package sample_1_ral_pkg;
20
20
  super.new(name, 32, 0);
21
21
  endfunction
22
22
  function void create_fields();
23
- `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1)
23
+ `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
24
24
  endfunction
25
25
  endclass
26
26
  class register_2_reg_model extends rggen_ral_reg;
@@ -30,8 +30,8 @@ package sample_1_ral_pkg;
30
30
  super.new(name, 24, 0);
31
31
  endfunction
32
32
  function void create_fields();
33
- `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0)
34
- `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1)
33
+ `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
34
+ `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
35
35
  endfunction
36
36
  endclass
37
37
  class sample_1_block_model extends rggen_ral_block;
@@ -42,9 +42,9 @@ package sample_1_ral_pkg;
42
42
  super.new(name);
43
43
  endfunction
44
44
  function void create_sub_models();
45
- `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0)
46
- `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0)
47
- `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0)
45
+ `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0, "")
46
+ `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0, "")
47
+ `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0, "")
48
48
  endfunction
49
49
  function uvm_reg_map create_default_map();
50
50
  return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
@@ -12,8 +12,8 @@ enable :global , [:data_width, :address_width]
12
12
  enable :register_block, [:name, :base_address]
13
13
  enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
14
14
  enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
15
- enable :bit_field , :type, [:rw, :ro, :foo, :reserved]
16
- enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux]
15
+ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :foo, :reserved]
16
+ enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
17
17
  enable :register_block, :host_if, [:apb, :bar]
18
18
  enable :register , [:address_decoder, :read_data, :bus_exporter]
19
19
  enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
@@ -2,8 +2,8 @@ enable :global , [:data_width, :address_width]
2
2
  enable :register_block, [:name, :byte_size]
3
3
  enable :register , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
4
4
  enable :bit_field , [:bit_assignment, :name, :type, :initial_value, :reference]
5
- enable :bit_field , :type, [:rw, :ro, :reserved]
6
- enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux]
5
+ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :reserved]
6
+ enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
7
7
  enable :register_block, :host_if, [:apb, :axi4lite]
8
8
  enable :register , [:address_decoder, :read_data, :bus_exporter]
9
9
  enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.4.0
4
+ version: 0.4.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2016-05-24 00:00:00.000000000 Z
11
+ date: 2016-06-07 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: baby_erubis
@@ -146,10 +146,15 @@ files:
146
146
  - lib/rggen/builtins/bit_field/name.rb
147
147
  - lib/rggen/builtins/bit_field/reference.rb
148
148
  - lib/rggen/builtins/bit_field/reserved.rb
149
+ - lib/rggen/builtins/bit_field/ro.erb
149
150
  - lib/rggen/builtins/bit_field/ro.rb
150
151
  - lib/rggen/builtins/bit_field/rw.erb
151
152
  - lib/rggen/builtins/bit_field/rw.rb
152
153
  - lib/rggen/builtins/bit_field/type.rb
154
+ - lib/rggen/builtins/bit_field/w0c_w1c.erb
155
+ - lib/rggen/builtins/bit_field/w0c_w1c.rb
156
+ - lib/rggen/builtins/bit_field/w0s_w1s.erb
157
+ - lib/rggen/builtins/bit_field/w0s_w1s.rb
153
158
  - lib/rggen/builtins/bit_field/wo.rb
154
159
  - lib/rggen/builtins/global/address_width.rb
155
160
  - lib/rggen/builtins/global/data_width.rb
@@ -186,6 +191,8 @@ files:
186
191
  - lib/rggen/builtins/register_block/constructor.rb
187
192
  - lib/rggen/builtins/register_block/default_map_creator.rb
188
193
  - lib/rggen/builtins/register_block/host_if.rb
194
+ - lib/rggen/builtins/register_block/irq_controller.erb
195
+ - lib/rggen/builtins/register_block/irq_controller.rb
189
196
  - lib/rggen/builtins/register_block/name.rb
190
197
  - lib/rggen/builtins/register_block/ral_package.rb
191
198
  - lib/rggen/builtins/register_block/response_mux.erb
@@ -254,13 +261,17 @@ files:
254
261
  - ral/rggen_ral_pkg.sv
255
262
  - ral/rggen_ral_reg.svh
256
263
  - ral/rggen_ral_shadow_reg.svh
264
+ - rtl/bit_field/rggen_bit_field_ro.sv
257
265
  - rtl/bit_field/rggen_bit_field_rw.sv
266
+ - rtl/bit_field/rggen_bit_field_w0c_w1c.sv
267
+ - rtl/bit_field/rggen_bit_field_w0s_w1s.sv
258
268
  - rtl/compile.f
259
269
  - rtl/register/rggen_address_decoder.sv
260
270
  - rtl/register/rggen_bus_exporter.sv
261
271
  - rtl/register_block/rggen_host_if_apb.sv
262
272
  - rtl/register_block/rggen_host_if_axi4lite.sv
263
273
  - rtl/register_block/rggen_host_if_common.svh
274
+ - rtl/register_block/rggen_irq_controller.sv
264
275
  - rtl/register_block/rggen_response_mux.sv
265
276
  - sample/sample.csv
266
277
  - sample/sample.json