rggen 0.4.0 → 0.4.1

data/lib/rggen/output_base/component.rb

@@ -3,16 +3,17 @@ module RgGen
     class Component < Base::Component
       include Base::HierarchicalAccessors
 
-      def initialize(parent, configuration, register_map)
+      def initialize(parent, configuration, source)
         super(parent)
         define_hierarchical_accessors
         @configuration  = configuration
-        @register_map   = register_map
-        @need_children  = register_map.need_children?
-        def_delegators(:@register_map, *@register_map.fields)
+        @source         = source
+        @need_children  = source.need_children?
+        def_delegators(:source, *source.fields)
       end
 
       attr_reader :configuration
+      attr_reader :source
       attr_writer :output_directory
 
       def add_item(item)

data/lib/rggen/output_base/verilog_utility.rb

@@ -36,6 +36,10 @@ module RgGen
         "assign #{lhs} = #{rhs};"
       end
 
+      def subroutine_call(subroutine, arguments = nil)
+        "#{subroutine}(#{Array(arguments).join(', ')})"
+      end
+
       def concat(expression, *other_expressions)
         expressions = Array[expression, *other_expressions]
         "{#{expressions.join(', ')}}"

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
   MINOR   = 4
-  TEENY   = 0
+  TEENY   = 1
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/rggen_ral_block.svh

@@ -14,6 +14,7 @@ class rggen_ral_block extends uvm_reg_block;
     uvm_endianness_e  endian,
     bit               byte_addressing = 1
   );
+  extern virtual function void build();
   extern virtual function void lock_model();
 
   extern protected virtual function void set_cfg(uvm_object cfg);
@@ -28,6 +29,9 @@ endfunction
 function void rggen_ral_block::configure(uvm_object cfg, uvm_reg_block parent, string hdl_path);
   set_cfg(cfg);
   super.configure(parent, hdl_path);
+endfunction
+
+function void rggen_ral_block::build();
   if (default_map == null) begin
     default_map = create_default_map();
   end

data/ral/rggen_ral_macros.svh

@@ -1,21 +1,21 @@
 `ifndef __RGGEN_RAL_MACROS_SVH__
 `define __RGGEN_RAL_MACROS_SVH__
 
-`define rggen_ral_create_field_model(handle, name, width, lsb, access, volatile, reset, has_reset) \
+`define rggen_ral_create_field_model(handle, name, width, lsb, access, volatile, reset, has_reset, hdl_path) \
 begin \
+  string  __hdl_path  = hdl_path; \
   handle  = new(name); \
   handle.configure(this.cfg, this, width, lsb, access, volatile, reset, has_reset, 1, 1); \
+  if (__hdl_path.len() > 0) begin \
+    this.add_hdl_path_slice(__hdl_path, lsb, width); \
+  end \
 end
 
-`define rggen_ral_create_reg_model(handle, base_name, array_index, offset_address, rights, unmapped) \
+`define rggen_ral_create_reg_model(handle, name, array_index, offset_address, rights, unmapped, hdl_path) \
 begin \
-  string  __instance_name   = base_name; \
-  int     __array_index[$]  = array_index; \
-  foreach (__array_index[__i]) begin \
-    $sformat(__instance_name, "%s[%0d]", __instance_name, __array_index[__i]); \
-  end \
-  handle  = new(__instance_name); \
-  handle.configure(this.cfg, this, null, array_index); \
+  handle  = new(name); \
+  handle.configure(this.cfg, this, null, array_index, hdl_path); \
+  handle.build(); \
   default_map.add_reg(handle, offset_address, rights, unmapped); \
 end
 
@@ -23,6 +23,7 @@ end
 begin \
   handle  = new(name); \
   handle.configure(this.cfg, this, ""); \
+  handle.build(); \
   default_map.add_submap(handle.default_map, offset_address); \
 end
 

data/ral/rggen_ral_map.svh

@@ -61,7 +61,7 @@ function void rggen_ral_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_
   super.set_submap_offset(submap, offset);
   if ((submap != null) && locked) begin
     uvm_reg_map   root_map  = get_root_map();
-    rggen_ral_map  rggen_map;
+    rggen_ral_map rggen_map;
     if ($cast(rggen_map, root_map)) begin
       rggen_map.Xinit_shadow_reg_address_mapX();
     end
@@ -84,7 +84,7 @@ endfunction
 
 function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
   uvm_reg_map   top_map;
-  rggen_ral_map  top_rggen_map;
+  rggen_ral_map top_rggen_map;
   uvm_reg_map   submaps[$];
   uvm_reg       regs[$];
 
@@ -98,7 +98,7 @@ function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
 
   get_submaps(submaps, UVM_NO_HIER);
   foreach (submaps[i]) begin
-    rggen_ral_map  rggen_map;
+    rggen_ral_map rggen_map;
     if ($cast(rggen_map, submaps[i])) begin
       rggen_map.Xinit_shadow_reg_address_mapX();
     end

data/ral/rggen_ral_reg.svh

@@ -13,6 +13,7 @@ class rggen_ral_reg extends uvm_reg;
     int           indexes[$],
     string        hdl_path = ""
   );
+  extern virtual function void build();
 
   extern virtual function uvm_reg_frontdoor create_frontdoor();
 
@@ -36,6 +37,9 @@ function void rggen_ral_reg::configure(
   end
   set_cfg(cfg);
   super.configure(blk_parent, regfile_parent, hdl_path);
+endfunction
+
+function void rggen_ral_reg::build();
   create_fields();
 endfunction
 

data/rtl/bit_field/rggen_bit_field_ro.sv

@@ -0,0 +1,8 @@
+module rggen_bit_field_ro #(
+  parameter WIDTH = 1
+)(
+  input   [WIDTH-1:0] i_value,
+  output  [WIDTH-1:0] o_value
+);
+  assign  o_value = i_value;
+endmodule

data/rtl/bit_field/rggen_bit_field_w0c_w1c.sv

@@ -0,0 +1,36 @@
+module rggen_bit_field_w0c_w1c #(
+  parameter WIDTH         = 1,
+  parameter INITIAL_VALUE = 1'b0,
+  parameter CLEAR_VALUE   = 1'b0
+)(
+  input               clk,
+  input               rst_n,
+  input   [WIDTH-1:0] i_set,
+  input               i_command_valid,
+  input               i_select,
+  input               i_write,
+  input   [WIDTH-1:0] i_write_data,
+  input   [WIDTH-1:0] i_write_mask,
+  output  [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+  logic             write_valid;
+
+  assign  o_value     = value;
+  assign  write_valid = (i_command_valid && i_select && i_write) ? 1'b1 : 1'b0;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else begin
+      for (int i = 0;i < WIDTH;i++) begin
+        if (i_set[i]) begin
+          value[i]  <= 1'b1;
+        end
+        else if (write_valid && i_write_mask[i] && (i_write_data[i] == CLEAR_VALUE)) begin
+          value[i]  <= 1'b0;
+        end
+      end
+    end
+  end
+endmodule

data/rtl/bit_field/rggen_bit_field_w0s_w1s.sv

@@ -0,0 +1,36 @@
+module rggen_bit_field_w0s_w1s #(
+  parameter WIDTH         = 1,
+  parameter INITIAL_VALUE = 1'b0,
+  parameter SET_VALUE     = 1'b0
+)(
+  input               clk,
+  input               rst_n,
+  input   [WIDTH-1:0] i_clear,
+  input               i_command_valid,
+  input               i_select,
+  input               i_write,
+  input   [WIDTH-1:0] i_write_data,
+  input   [WIDTH-1:0] i_write_mask,
+  output  [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+  logic             write_valid;
+
+  assign  o_value     = value;
+  assign  write_valid = (i_command_valid && i_select && i_write) ? 1'b1 : 1'b0;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else begin
+      for (int i = 0;i < WIDTH;i++) begin
+        if (write_valid && i_write_mask[i] && (i_write_data[i] == SET_VALUE)) begin
+          value[i]  <= 1'b1;
+        end
+        else if (i_clear[i]) begin
+          value[i]  <= 1'b0;
+        end
+      end
+    end
+  end
+endmodule

data/rtl/register/rggen_address_decoder.sv

@@ -1,6 +1,4 @@
 module rggen_address_decoder #(
-  parameter READABLE            = 1,
-  parameter WRITABLE            = 1,
   parameter ADDRESS_WIDTH       = 16,
   parameter START_ADDRESS       = 'h00,
   parameter END_ADDRESS         = 'h00,
@@ -14,14 +12,10 @@ module rggen_address_decoder #(
   input   [SHADOW_INDEX_WIDTH-1:0]  i_shadow_index,
   output                            o_select
 );
-  localparam  READ_ONLY   = (READABLE && (!WRITABLE)) ? 1 : 0;
-  localparam  WRITE_ONLY  = (WRITABLE && (!READABLE)) ? 1 : 0;
-
-  logic match;
   logic match_address;
   logic match_shadow_index;
 
-  assign  match = (match_address && match_shadow_index) ? 1'b1 : 1'b0;
+  assign  o_select  = (match_address && match_shadow_index) ? 1'b1 : 1'b0;
 
   generate
     if (START_ADDRESS == END_ADDRESS) begin
@@ -42,16 +36,4 @@ module rggen_address_decoder #(
       assign  match_shadow_index  = 1'b1;
     end
   endgenerate
-
-  generate
-    if (READ_ONLY) begin
-      assign  o_select  = (match && i_read) ? 1'b1 : 1'b0;
-    end
-    else if (WRITE_ONLY) begin
-      assign  o_select  = (match && i_write) ? 1'b1 : 1'b0;
-    end
-    else begin
-      assign  o_select  = match;
-    end
-  endgenerate
 endmodule

data/rtl/register_block/rggen_irq_controller.sv

@@ -0,0 +1,21 @@
+module rggen_irq_controller #(
+  parameter TOTAL_INTERRUPTS  = 1
+)(
+  input                           clk,
+  input                           rst_n,
+  input   [TOTAL_INTERRUPTS-1:0]  i_ier,
+  input   [TOTAL_INTERRUPTS-1:0]  i_isr,
+  output                          o_irq
+);
+  logic irq;
+
+  assign  o_irq = irq;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      irq <= 1'b0;
+    end
+    else begin
+      irq <= |(i_ier & i_isr);
+    end
+  end
+endmodule

data/sample/sample.csv

@@ -1,15 +1,20 @@
-,block name,block_0,,,,,,,,
-,byte size,256,,,,,,,,
-,,,,,,,,,,
-,offset address,registe name,array dimension,shadow index,external,assignment,field name,type,initial value,reference
-,0x00,register_0,,,,[31:16],bit_field_0_0,rw,0,
-,,,,,,[15:0],bit_field_0_1,rw,0,
-,0x04,register_1,,,,[31:0],bit_field_1_0,rw,0,
-,0x08,register_2,,,,[16],bit_field_2_0,ro,,
-,,,,,,[0],bit_field_2_1,rw,0,
-,0x0C,register_3,,,,[31:0],bit_field_3_0,ro,,
-,0x10 - 0x1F,register_4,[4],,,[31:16],bit_field_4_0,ro,,
-,,,,,,[15:0],bit_field_4_1,rw,0,
-,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",,[31:16],bit_field_5_0,ro,,
-,,,,,,[15:0],bit_field_5_1,rw,0,
-,0x80-0xFF,register_6,,,true,,,,,
+,block name,block_0,,,,,,,,,
+,byte size,256,,,,,,,,,
+,,,,,,,,,,,
+,offset address,registe name,array dimension,shadow index,external,assignment,field name,type,initial value,reference,
+,0x00,register_0,,,,[31:16],bit_field_0_0,rw,0,,
+,,,,,,[15:0],bit_field_0_1,rw,0,,
+,0x04,register_1,,,,[31:0],bit_field_1_0,rw,0,,
+,0x08,register_2,,,,[16],bit_field_2_0,ro,,,
+,,,,,,[0],bit_field_2_1,rw,0,,
+,0x0C,register_3,,,,[31:0],bit_field_3_0,ro,,,
+,0x10 - 0x1F,register_4,[4],,,[31:16],bit_field_4_0,ro,,,
+,,,,,,[15:0],bit_field_4_1,rw,0,,
+,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",,[31:16],bit_field_5_0,ro,,,
+,,,,,,[15:0],bit_field_5_1,rw,0,,
+,0x24,register_6,,,,[8],bit_field_6_0,w0c,0,bit_field_2_1,
+,,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1,
+,0x28,register_7,,,,[8],bit_field_7_0,w0s,0,,
+,,,,,,[0],bit_field_7_1,w1s,0,,
+,0x80-0xFF,register_8,,,TRUE,,,,,,
+,,,,,,,,,,,

data/sample/sample_0.sv

@@ -11,6 +11,7 @@ module sample_0 (
   output o_pready,
   output [31:0] o_prdata,
   output o_pslverr,
+  output o_irq,
   output [15:0] o_bit_field_0_0,
   output [15:0] o_bit_field_0_1,
   output [31:0] o_bit_field_1_0,
@@ -21,15 +22,21 @@ module sample_0 (
   output [15:0] o_bit_field_4_1[4],
   input [15:0] i_bit_field_5_0[2][4],
   output [15:0] o_bit_field_5_1[2][4],
-  output o_register_6_valid,
-  output o_register_6_write,
-  output o_register_6_read,
-  output [6:0] o_register_6_address,
-  output [3:0] o_register_6_strobe,
-  output [31:0] o_register_6_write_data,
-  input i_register_6_ready,
-  input [1:0] i_register_6_status,
-  input [31:0] i_register_6_read_data
+  input i_bit_field_6_0_set,
+  input i_bit_field_6_1_set,
+  output o_bit_field_7_0,
+  input i_bit_field_7_0_clear,
+  output o_bit_field_7_1,
+  input i_bit_field_7_1_clear,
+  output o_register_8_valid,
+  output o_register_8_write,
+  output o_register_8_read,
+  output [6:0] o_register_8_address,
+  output [3:0] o_register_8_strobe,
+  output [31:0] o_register_8_write_data,
+  input i_register_8_ready,
+  input [1:0] i_register_8_status,
+  input [31:0] i_register_8_read_data
 );
   logic command_valid;
   logic write;
@@ -41,11 +48,13 @@ module sample_0 (
   logic response_ready;
   logic [31:0] read_data;
   logic [1:0] status;
-  logic [16:0] register_select;
-  logic [31:0] register_read_data[17];
+  logic [18:0] register_select;
+  logic [31:0] register_read_data[19];
   logic [0:0] external_register_select;
   logic [0:0] external_register_ready;
   logic [1:0] external_register_status[1];
+  logic [1:0] ier;
+  logic [1:0] isr;
   logic [15:0] bit_field_0_0_value;
   logic [15:0] bit_field_0_1_value;
   logic [31:0] bit_field_1_0_value;
@@ -57,6 +66,10 @@ module sample_0 (
   logic [32:0] register_5_shadow_index[2][4];
   logic [15:0] bit_field_5_0_value[2][4];
   logic [15:0] bit_field_5_1_value[2][4];
+  logic bit_field_6_0_value;
+  logic bit_field_6_1_value;
+  logic bit_field_7_0_value;
+  logic bit_field_7_1_value;
   rggen_host_if_apb #(
     .DATA_WIDTH           (32),
     .HOST_ADDRESS_WIDTH   (16),
@@ -87,7 +100,7 @@ module sample_0 (
   );
   rggen_response_mux #(
     .DATA_WIDTH               (32),
-    .TOTAL_REGISTERS          (17),
+    .TOTAL_REGISTERS          (19),
     .TOTAL_EXTERNAL_REGISTERS (1)
   ) u_response_mux (
     .clk                        (clk),
@@ -103,9 +116,18 @@ module sample_0 (
     .i_external_register_ready  (external_register_ready),
     .i_external_register_status (external_register_status)
   );
+  assign ier = {bit_field_2_1_value, bit_field_2_1_value};
+  assign isr = {bit_field_6_0_value, bit_field_6_1_value};
+  rggen_irq_controller #(
+    .TOTAL_INTERRUPTS (2)
+  ) u_irq_controller (
+    .clk    (clk),
+    .rst_n  (rst_n),
+    .i_ier  (ier),
+    .i_isr  (isr),
+    .o_irq  (o_irq)
+  );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (6),
     .START_ADDRESS      (6'h00),
     .END_ADDRESS        (6'h00),
@@ -149,8 +171,6 @@ module sample_0 (
     .o_value          (bit_field_0_1_value)
   );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (6),
     .START_ADDRESS      (6'h01),
     .END_ADDRESS        (6'h01),
@@ -180,8 +200,6 @@ module sample_0 (
     .o_value          (bit_field_1_0_value)
   );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (6),
     .START_ADDRESS      (6'h02),
     .END_ADDRESS        (6'h02),
@@ -196,7 +214,12 @@ module sample_0 (
     .o_select       (register_select[2])
   );
   assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
-  assign bit_field_2_0_value = i_bit_field_2_0;
+  rggen_bit_field_ro #(
+    .WIDTH  (1)
+  ) u_bit_field_2_0 (
+    .i_value  (i_bit_field_2_0),
+    .o_value  (bit_field_2_0_value)
+  );
   assign o_bit_field_2_1 = bit_field_2_1_value;
   rggen_bit_field_rw #(
     .WIDTH          (1),
@@ -212,8 +235,6 @@ module sample_0 (
     .o_value          (bit_field_2_1_value)
   );
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (0),
     .ADDRESS_WIDTH      (6),
     .START_ADDRESS      (6'h03),
     .END_ADDRESS        (6'h03),
@@ -228,13 +249,16 @@ module sample_0 (
     .o_select       (register_select[3])
   );
   assign register_read_data[3] = {bit_field_3_0_value};
-  assign bit_field_3_0_value = i_bit_field_3_0;
+  rggen_bit_field_ro #(
+    .WIDTH  (32)
+  ) u_bit_field_3_0 (
+    .i_value  (i_bit_field_3_0),
+    .o_value  (bit_field_3_0_value)
+  );
   generate if (1) begin : g_register_4
     genvar g_i;
     for (g_i = 0;g_i < 4;g_i++) begin : g
       rggen_address_decoder #(
-        .READABLE           (1),
-        .WRITABLE           (1),
         .ADDRESS_WIDTH      (6),
         .START_ADDRESS      (6'h04 + g_i),
         .END_ADDRESS        (6'h04 + g_i),
@@ -249,7 +273,12 @@ module sample_0 (
         .o_select       (register_select[4+g_i])
       );
       assign register_read_data[4+g_i] = {bit_field_4_0_value[g_i], bit_field_4_1_value[g_i]};
-      assign bit_field_4_0_value[g_i] = i_bit_field_4_0[g_i];
+      rggen_bit_field_ro #(
+        .WIDTH  (16)
+      ) u_bit_field_4_0 (
+        .i_value  (i_bit_field_4_0[g_i]),
+        .o_value  (bit_field_4_0_value[g_i])
+      );
       assign o_bit_field_4_1[g_i] = bit_field_4_1_value[g_i];
       rggen_bit_field_rw #(
         .WIDTH          (16),
@@ -272,8 +301,6 @@ module sample_0 (
       for (g_j = 0;g_j < 4;g_j++) begin : g
         assign register_5_shadow_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
         rggen_address_decoder #(
-          .READABLE           (1),
-          .WRITABLE           (1),
           .ADDRESS_WIDTH      (6),
           .START_ADDRESS      (6'h08),
           .END_ADDRESS        (6'h08),
@@ -288,7 +315,12 @@ module sample_0 (
           .o_select       (register_select[8+4*g_i+g_j])
         );
         assign register_read_data[8+4*g_i+g_j] = {bit_field_5_0_value[g_i][g_j], bit_field_5_1_value[g_i][g_j]};
-        assign bit_field_5_0_value[g_i][g_j] = i_bit_field_5_0[g_i][g_j];
+        rggen_bit_field_ro #(
+          .WIDTH  (16)
+        ) u_bit_field_5_0 (
+          .i_value  (i_bit_field_5_0[g_i][g_j]),
+          .o_value  (bit_field_5_0_value[g_i][g_j])
+        );
         assign o_bit_field_5_1[g_i][g_j] = bit_field_5_1_value[g_i][g_j];
         rggen_bit_field_rw #(
           .WIDTH          (16),
@@ -307,11 +339,9 @@ module sample_0 (
     end
   end endgenerate
   rggen_address_decoder #(
-    .READABLE           (1),
-    .WRITABLE           (1),
     .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h20),
-    .END_ADDRESS        (6'h3f),
+    .START_ADDRESS      (6'h09),
+    .END_ADDRESS        (6'h09),
     .USE_SHADOW_INDEX   (0),
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
@@ -322,33 +352,125 @@ module sample_0 (
     .i_shadow_index (1'h0),
     .o_select       (register_select[16])
   );
-  assign external_register_select[0] = register_select[16];
+  assign register_read_data[16] = {23'h000000, bit_field_6_0_value, 7'h00, bit_field_6_1_value};
+  rggen_bit_field_w0c_w1c #(
+    .WIDTH          (1),
+    .INITIAL_VALUE  (1'h0),
+    .CLEAR_VALUE    (1'b0)
+  ) u_bit_field_6_0 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_set            (i_bit_field_6_0_set),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[16]),
+    .i_write          (write),
+    .i_write_data     (write_data[8]),
+    .i_write_mask     (write_mask[8]),
+    .o_value          (bit_field_6_0_value)
+  );
+  rggen_bit_field_w0c_w1c #(
+    .WIDTH          (1),
+    .INITIAL_VALUE  (1'h0),
+    .CLEAR_VALUE    (1'b1)
+  ) u_bit_field_6_1 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_set            (i_bit_field_6_1_set),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[16]),
+    .i_write          (write),
+    .i_write_data     (write_data[0]),
+    .i_write_mask     (write_mask[0]),
+    .o_value          (bit_field_6_1_value)
+  );
+  rggen_address_decoder #(
+    .ADDRESS_WIDTH      (6),
+    .START_ADDRESS      (6'h0a),
+    .END_ADDRESS        (6'h0a),
+    .USE_SHADOW_INDEX   (0),
+    .SHADOW_INDEX_WIDTH (1),
+    .SHADOW_INDEX_VALUE (1'h0)
+  ) u_register_7_address_decoder (
+    .i_read         (read),
+    .i_write        (write),
+    .i_address      (address[7:2]),
+    .i_shadow_index (1'h0),
+    .o_select       (register_select[17])
+  );
+  assign register_read_data[17] = {23'h000000, bit_field_7_0_value, 7'h00, bit_field_7_1_value};
+  assign o_bit_field_7_0 = bit_field_7_0_value;
+  rggen_bit_field_w0s_w1s #(
+    .WIDTH          (1),
+    .INITIAL_VALUE  (1'h0),
+    .SET_VALUE      (1'b0)
+  ) u_bit_field_7_0 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_clear          (i_bit_field_7_0_clear),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[17]),
+    .i_write          (write),
+    .i_write_data     (write_data[8]),
+    .i_write_mask     (write_mask[8]),
+    .o_value          (bit_field_7_0_value)
+  );
+  assign o_bit_field_7_1 = bit_field_7_1_value;
+  rggen_bit_field_w0s_w1s #(
+    .WIDTH          (1),
+    .INITIAL_VALUE  (1'h0),
+    .SET_VALUE      (1'b1)
+  ) u_bit_field_7_1 (
+    .clk              (clk),
+    .rst_n            (rst_n),
+    .i_clear          (i_bit_field_7_1_clear),
+    .i_command_valid  (command_valid),
+    .i_select         (register_select[17]),
+    .i_write          (write),
+    .i_write_data     (write_data[0]),
+    .i_write_mask     (write_mask[0]),
+    .o_value          (bit_field_7_1_value)
+  );
+  rggen_address_decoder #(
+    .ADDRESS_WIDTH      (6),
+    .START_ADDRESS      (6'h20),
+    .END_ADDRESS        (6'h3f),
+    .USE_SHADOW_INDEX   (0),
+    .SHADOW_INDEX_WIDTH (1),
+    .SHADOW_INDEX_VALUE (1'h0)
+  ) u_register_8_address_decoder (
+    .i_read         (read),
+    .i_write        (write),
+    .i_address      (address[7:2]),
+    .i_shadow_index (1'h0),
+    .o_select       (register_select[18])
+  );
+  assign external_register_select[0] = register_select[18];
   rggen_bus_exporter #(
     .DATA_WIDTH             (32),
     .LOCAL_ADDRESS_WIDTH    (8),
     .EXTERNAL_ADDRESS_WIDTH (7),
     .START_ADDRESS          (8'h80)
-  ) u_register_6_bus_exporter (
+  ) u_register_8_bus_exporter (
     .clk          (clk),
     .rst_n        (rst_n),
     .i_valid      (command_valid),
-    .i_select     (register_select[16]),
+    .i_select     (register_select[18]),
     .i_write      (write),
     .i_read       (read),
     .i_address    (address),
     .i_strobe     (strobe),
     .i_write_data (write_data),
     .o_ready      (external_register_ready[0]),
-    .o_read_data  (register_read_data[16]),
+    .o_read_data  (register_read_data[18]),
     .o_status     (external_register_status[0]),
-    .o_valid      (o_register_6_valid),
-    .o_write      (o_register_6_write),
-    .o_read       (o_register_6_read),
-    .o_address    (o_register_6_address),
-    .o_strobe     (o_register_6_strobe),
-    .o_write_data (o_register_6_write_data),
-    .i_ready      (i_register_6_ready),
-    .i_read_data  (i_register_6_read_data),
-    .i_status     (i_register_6_status)
+    .o_valid      (o_register_8_valid),
+    .o_write      (o_register_8_write),
+    .o_read       (o_register_8_read),
+    .o_address    (o_register_8_address),
+    .o_strobe     (o_register_8_strobe),
+    .o_write_data (o_register_8_write_data),
+    .i_ready      (i_register_8_ready),
+    .i_read_data  (i_register_8_read_data),
+    .i_status     (i_register_8_status)
   );
 endmodule