rggen 0.3.0

data/ral/rggen_ral_shadow_reg.svh

@@ -0,0 +1,188 @@
+`ifndef __RGEN_RAL_SHADOW_REG_SVH__
+`define __RGEN_RAL_SHADOW_REG_SVH__
+typedef class rgen_ral_shadow_reg_index;
+typedef class rgen_ral_shadow_reg_ftdr_seq;
+
+class rgen_ral_shadow_reg extends rgen_ral_reg;
+  protected rgen_ral_shadow_reg_index shadow_reg_indexes[$];
+
+  extern function new(string name, int unsigned n_bits, int has_coverage);
+
+  extern function void configure(
+    uvm_object    cfg,
+    uvm_reg_block blk_parent,
+    uvm_reg_file  regfile_parent,
+    int           indexes[$],
+    string        hdl_path = ""
+  );
+
+  extern virtual function uvm_reg_frontdoor create_frontdoor();
+  extern virtual function bit is_active();
+
+  extern protected virtual function void configure_shadow_indexes();
+  extern protected function void set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
+endclass
+
+function rgen_ral_shadow_reg::new(string name, int unsigned n_bits, int has_coverage);
+  super.new(name, n_bits, has_coverage);
+endfunction
+
+function void rgen_ral_shadow_reg::configure(
+  uvm_object    cfg,
+  uvm_reg_block blk_parent,
+  uvm_reg_file  regfile_parent,
+  int           indexes[$],
+  string        hdl_path
+);
+  super.configure(cfg, blk_parent, regfile_parent, indexes, hdl_path);
+  configure_shadow_indexes();
+endfunction
+
+function uvm_reg_frontdoor rgen_ral_shadow_reg::create_frontdoor();
+  rgen_ral_shadow_reg_ftdr_seq  fd  = new(shadow_reg_indexes);
+  return fd;
+endfunction
+
+function bit rgen_ral_shadow_reg::is_active();
+  foreach (shadow_reg_indexes[i]) begin
+    if (!shadow_reg_indexes[i].is_matched()) begin
+      return 0;
+    end
+  end
+  return 1;
+endfunction
+
+function void rgen_ral_shadow_reg::configure_shadow_indexes();
+endfunction
+
+function void rgen_ral_shadow_reg::set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
+  rgen_ral_shadow_reg_index shadow_reg_index;
+  shadow_reg_index  = new(this, reg_name, field_name, value);
+  shadow_reg_indexes.push_back(shadow_reg_index);
+endfunction
+
+class rgen_ral_shadow_reg_index;
+  protected rgen_ral_shadow_reg shadow_reg;
+  protected string              reg_name;
+  protected string              field_name;
+  protected uvm_reg_data_t      value;
+  protected uvm_reg_field       index_field;
+
+  extern function new(
+    rgen_ral_shadow_reg shadow_reg,
+    string              reg_name,
+    string              field_name,
+    uvm_reg_data_t      value
+  );
+
+  extern virtual function bit is_matched();
+  extern virtual task update(
+    output  uvm_status_e      status,
+    input   uvm_path_e        path      = UVM_DEFAULT_PATH,
+    input   uvm_reg_map       map       = null,
+    input   uvm_sequence_base parent    = null,
+    input   int               prior     = -1,
+    input   uvm_object        extension = null,
+    input   string            fname     = "",
+    input   int               lineno    = 0
+  );
+
+  extern protected virtual function uvm_reg_field get_index_field();
+endclass
+
+function rgen_ral_shadow_reg_index::new(
+  rgen_ral_shadow_reg shadow_reg,
+  string              reg_name,
+  string              field_name,
+  uvm_reg_data_t      value
+);
+  this.shadow_reg = shadow_reg;
+  this.reg_name   = reg_name;
+  this.field_name = field_name;
+  this.value      = value;
+endfunction
+
+function bit rgen_ral_shadow_reg_index::is_matched();
+  uvm_reg_field field = get_index_field();
+  return (field.value == value) ? 1 : 0;
+endfunction
+
+task rgen_ral_shadow_reg_index::update(
+  output  uvm_status_e      status,
+  input   uvm_path_e        path,
+  input   uvm_reg_map       map,
+  input   uvm_sequence_base parent,
+  input   int               prior,
+  input   uvm_object        extension,
+  input   string            fname,
+  input   int               lineno
+);
+  uvm_reg_field field       = get_index_field();
+  uvm_reg       parent_reg  = field.get_parent();
+  field.set(value);
+  parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
+endtask
+
+function uvm_reg_field rgen_ral_shadow_reg_index::get_index_field();
+  if (index_field == null) begin
+    uvm_reg_block parent_block  = shadow_reg.get_parent();
+    uvm_reg       index_reg;
+
+    index_reg = parent_block.get_reg_by_name(reg_name);
+    if (index_reg == null) begin
+      `uvm_fatal("rgen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
+      return null;
+    end
+
+    index_field = index_reg.get_field_by_name(field_name);
+    if (index_field == null) begin
+      `uvm_fatal("rgen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
+      return null;
+    end
+  end
+  return index_field;
+endfunction
+
+class rgen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
+  protected rgen_ral_shadow_reg_index shadow_indexes[$];
+
+  extern function new(ref rgen_ral_shadow_reg_index shadow_indexes[$]);
+
+  extern virtual task body();
+endclass
+
+function rgen_ral_shadow_reg_ftdr_seq::new(ref rgen_ral_shadow_reg_index shadow_indexes[$]);
+  super.new("rgen_ral_shadow_reg_ftdr_seq");
+  foreach (shadow_indexes[i]) begin
+    this.shadow_indexes.push_back(shadow_indexes[i]);
+  end
+endfunction
+
+task rgen_ral_shadow_reg_ftdr_seq::body();
+  foreach (shadow_indexes[i]) begin
+    uvm_status_e  status;
+    shadow_indexes[i].update(
+      status,
+      rw_info.path,
+      rw_info.map,
+      rw_info.parent,
+      rw_info.prior,
+      rw_info.extension,
+      rw_info.fname,
+      rw_info.lineno
+    );
+    if (status == UVM_NOT_OK) begin
+      `uvm_warning("rgen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
+      rw_info.status  = status;
+      return;
+    end
+  end
+
+  if (rw_info.kind == UVM_WRITE) begin
+    rw_info.local_map.do_write(rw_info);
+  end
+  else begin
+    rw_info.local_map.do_read(rw_info);
+  end
+endtask
+`endif

data/rggen.gemspec

@@ -0,0 +1,45 @@
+# coding: utf-8
+lib = File.expand_path('../lib', __FILE__)
+$LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
+require 'rggen/version'
+
+Gem::Specification.new do |spec|
+  spec.name                   = 'rggen'
+  spec.version                = RgGen::VERSION
+  spec.required_ruby_version  = '>= 2.0'
+  spec.authors                = ['Taichi Ishitani']
+  spec.email                  = ['taichi730@gmail.com']
+
+  spec.summary        = 'Code generation tool for control registers in a SoC design.'
+  spec.description    = <<-EOS
+    RgGen is a code generation tool for SoC designers.
+    You can automatically generate soruce code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
+    You can also customize RgGen, so you can build your specific generation tool.
+  EOS
+  spec.homepage       = ''
+  spec.license        = 'MIT'
+
+  spec.files          = `git ls-files -z`.split("\x0").reject { |f|
+    f =~ %r{^(?:
+      bin/setup
+      |spec/.*
+      |Gemfile
+      |Rakefile
+      |.gitignore
+      |.rspec
+      |.travis.yml
+    )$}x
+  }
+  spec.bindir         = 'bin'
+  spec.executables    = ['rggen']
+  spec.require_paths  = ['lib']
+
+  spec.add_runtime_dependency 'baby_erubis', '>= 2.0'
+  spec.add_runtime_dependency 'facets'     , '>= 3.0'
+  spec.add_runtime_dependency 'roo'        , '>= 2.1.1'
+  spec.add_runtime_dependency 'spreadsheet', '>= 1.0.3'
+
+  spec.add_development_dependency 'rake'   , '~> 10.0'
+  spec.add_development_dependency 'rspec'  , '>=  3.3'
+  spec.add_development_dependency 'rubocop', '>=  0.35'
+end

data/rtl/bit_field/rggen_bit_field_rw.sv

@@ -0,0 +1,28 @@
+module rggen_bit_field_rw #(
+  parameter WIDTH         = 1,
+  parameter INITIAL_VALUE = 0
+)(
+  input               clk,
+  input               rst_n,
+  input               i_command_valid,
+  input               i_select,
+  input               i_write,
+  input   [WIDTH-1:0] i_write_data,
+  input   [WIDTH-1:0] i_write_mask,
+  output  [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] write_data;
+  logic [WIDTH-1:0] value;
+
+  assign  o_value     = value;
+  assign  write_data  = (i_write_data & ( i_write_mask))
+                      | (value        & (~i_write_mask));
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else if (i_command_valid && i_select && i_write) begin
+      value <= write_data;
+    end
+  end
+endmodule

data/rtl/register/rggen_address_decoder.sv

@@ -0,0 +1,49 @@
+module rggen_address_decoder #(
+  parameter READABLE            = 1,
+  parameter WRITABLE            = 1,
+  parameter ADDRESS_WIDTH       = 16,
+  parameter START_ADDRESS       = 'h00,
+  parameter END_ADDRESS         = 'h00,
+  parameter USE_SHADOW_INDEX    = 0,
+  parameter SHADOW_INDEX_WIDTH  = 1,
+  parameter SHADOW_INDEX_VALUE  = 'h00
+)(
+  input                             i_read,
+  input                             i_write,
+  input   [ADDRESS_WIDTH-1:0]       i_address,
+  input   [SHADOW_INDEX_WIDTH-1:0]  i_shadow_index,
+  output                            o_select
+);
+  localparam  READ_ONLY   = (READABLE && (!WRITABLE)) ? 1 : 0;
+  localparam  WRITE_ONLY  = (WRITABLE && (!READABLE)) ? 1 : 0;
+
+  logic match;
+  logic match_address;
+  logic match_shadow_index;
+
+  assign  match = (match_address && match_shadow_index) ? 1'b1 : 1'b0;
+
+  if (START_ADDRESS == END_ADDRESS) begin
+    assign  match_address = (i_address == START_ADDRESS) ? 1'b1 : 1'b0;
+  end
+  else begin
+    assign  match_address = (i_address inside {[START_ADDRESS:END_ADDRESS]}) ? 1'b1 : 1'b0;
+  end
+
+  if (USE_SHADOW_INDEX) begin
+    assign  match_shadow_index  = (i_shadow_index == SHADOW_INDEX_VALUE) ? 1'b1 : 1'b0;
+  end
+  else begin
+    assign  match_shadow_index  = 1'b1;
+  end
+
+  if (READ_ONLY) begin
+    assign  o_select  = (match && i_read) ? 1'b1 : 1'b0;
+  end
+  else if (WRITE_ONLY) begin
+    assign  o_select  = (match && i_write) ? 1'b1 : 1'b0;
+  end
+  else begin
+    assign  o_select  = match;
+  end
+endmodule

data/rtl/register_block/rggen_host_if_apb.sv

@@ -0,0 +1,40 @@
+module rggen_host_if_apb #(
+  parameter DATA_WIDTH          = 32,
+  parameter HOST_ADDRESS_WIDTH  = 16,
+  parameter LOCAL_ADDRESS_WIDTH = 16
+)(
+  input                             clk,
+  input                             rst_n,
+  input   [HOST_ADDRESS_WIDTH-1:0]  i_paddr,
+  input   [2:0]                     i_pprot,
+  input                             i_psel,
+  input                             i_penable,
+  input                             i_pwrite,
+  input   [DATA_WIDTH-1:0]          i_pwdata,
+  input   [DATA_WIDTH/8-1:0]        i_pstrb,
+  output                            o_pready,
+  output  [DATA_WIDTH-1:0]          o_prdata,
+  output                            o_pslverr,
+  output                            o_command_valid,
+  output                            o_write,
+  output                            o_read,
+  output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
+  output  [DATA_WIDTH-1:0]          o_write_data,
+  output  [DATA_WIDTH-1:0]          o_write_mask,
+  input                             i_response_ready,
+  input   [DATA_WIDTH-1:0]          i_read_data,
+  input   [1:0]                     i_status
+);
+  assign  o_pready  = i_response_ready;
+  assign  o_prdata  = i_read_data;
+  assign  o_pslverr = i_status[0];
+
+  assign  o_command_valid = i_psel;
+  assign  o_write         = i_pwrite;
+  assign  o_read          = ~i_pwrite;
+  assign  o_address       = i_paddr[LOCAL_ADDRESS_WIDTH-1:0];
+  assign  o_write_data    = i_pwdata;
+  for (genvar i = 0;i < DATA_WIDTH / 8;i++) begin
+    assign  o_write_mask[i*8+:8]  = {8{i_pstrb[i]}};
+  end
+endmodule

data/rtl/register_block/rggen_response_mux.sv

@@ -0,0 +1,82 @@
+module rggen_response_mux #(
+  parameter DATA_WIDTH      = 32,
+  parameter TOTAL_REGISTERS = 1
+)(
+  input                         clk,
+  input                         rst_n,
+  input                         i_command_valid,
+  input                         i_read,
+  output                        o_response_ready,
+  output  [DATA_WIDTH-1:0]      o_read_data,
+  output  [1:0]                 o_status,
+  input   [TOTAL_REGISTERS-1:0] i_register_select,
+  input   [DATA_WIDTH-1:0]      i_register_read_data[TOTAL_REGISTERS]
+);
+  //  Response ready
+  logic response_valid;
+  logic response_ready;
+
+  assign  o_response_ready  = response_ready;
+  assign  response_valid    = (i_command_valid && (!response_ready)) ? 1'b1 : 1'b0;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      response_ready  <= 1'b0;
+    end
+    else if (response_valid) begin
+      response_ready  <= 1'b1;
+    end
+    else begin
+      response_ready  <= 1'b0;
+    end
+  end
+
+  //  Status
+  logic       slave_error;
+  logic       exokay;
+  logic [1:0] status;
+
+  assign  o_status      = status;
+  assign  slave_error   = (TOTAL_REGISTERS == 1) ? ~i_register_select[0] : ~|i_register_select;
+  assign  exokay        = 1'b0;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      status  <= 2'b00;
+    end
+    else if (response_valid) begin
+      status  <= {exokay, slave_error};
+    end
+    else begin
+      status  <= 2'b00;
+    end
+  end
+
+  //  Read data
+  logic [DATA_WIDTH-1:0]  read_data;
+  logic [DATA_WIDTH-1:0]  selected_data;
+
+  assign  o_read_data = read_data;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n)  begin
+      read_data <= {DATA_WIDTH{1'b0}};
+    end
+    else if (response_valid && i_read) begin
+      read_data <= selected_data;
+    end
+    else begin
+      read_data <= {DATA_WIDTH{1'b0}};
+    end
+  end
+
+  if (TOTAL_REGISTERS > 1) begin
+    for (genvar i = 0;i < DATA_WIDTH;i++) begin
+      logic [TOTAL_REGISTERS-1:0] temp;
+      assign  selected_data[i]  = |temp;
+      for (genvar j = 0;j < TOTAL_REGISTERS;j++) begin
+        assign  temp[j] = i_register_select[j] & i_register_read_data[j][i];
+      end
+    end
+  end
+  else begin
+    assign  selected_data = i_register_read_data[0];
+  end
+endmodule

data/sample/sample.csv

@@ -0,0 +1,14 @@
+,block name,block_0,,,,,,,
+,byte size,256,,,,,,,
+,,,,,,,,,
+,offset address,registe name,array dimension,shadow index,assignment,field name,type,initial value,reference
+,0x00,register_0,,,[31:16],bit_field_0_0,rw,0,
+,,,,,[15:0],bit_field_0_1,rw,0,
+,0x04,register_1,,,[31:0],bit_field_1_0,rw,0,
+,0x08,register_2,,,[16],bit_field_2_0,ro,,
+,,,,,[0],bit_field_2_1,rw,0,
+,0x0C,register_3,,,[31:0],bit_field_3_0,ro,,
+,0x10 - 0x1F,register_4,[4],,[31:16],bit_field_4_0,ro,,
+,,,,,[15:0],bit_field_4_1,rw,0,
+,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",[31:16],bit_field_5_0,ro,,
+,,,,,[15:0],bit_field_5_1,rw,0,

data/sample/sample.json

@@ -0,0 +1,4 @@
+{
+  "address_width": 16,
+  "host_if"      : "apb"
+}

data/sample/sample.yaml

@@ -0,0 +1,2 @@
+address_width: 16
+host_if: apb